Merge branch 'develop' -- breaking changes 2022-05-28.

88 files changed, 2124 insertions, 1420 deletions

diff --git a/platforms/arm_atsam/pin_defs.h b/platforms/arm_atsam/_pin_defs.h
index 5b50b23910..5b50b23910 100644
--- a/platforms/arm_atsam/pin_defs.h
+++ b/platforms/arm_atsam/_pin_defs.h
diff --git a/platforms/arm_atsam/bootloaders/md_boot.c b/platforms/arm_atsam/bootloaders/md_boot.c
index 32cf850448..1cf7aec62c 100644
--- a/platforms/arm_atsam/bootloaders/md_boot.c
+++ b/platforms/arm_atsam/bootloaders/md_boot.c
@@ -63,3 +63,7 @@ void bootloader_jump(void) {
     while (1)
         ; // Wait on timeout
 }
+
+__attribute__((weak)) void mcu_reset(void) {
+    NVIC_SystemReset();
+}
diff --git a/platforms/arm_atsam/hardware_id.c b/platforms/arm_atsam/hardware_id.c
new file mode 100644
index 0000000000..8b3b35a492
--- /dev/null
+++ b/platforms/arm_atsam/hardware_id.c
@@ -0,0 +1,9 @@
+// Copyright 2022 QMK
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "hardware_id.h"
+
+hardware_id_t get_hardware_id(void) {
+    hardware_id_t id = {0};
+    return id;
+}
diff --git a/platforms/avr/pin_defs.h b/platforms/avr/_pin_defs.h
index 3889704a87..3889704a87 100644
--- a/platforms/avr/pin_defs.h
+++ b/platforms/avr/_pin_defs.h
diff --git a/platforms/avr/bootloaders/bootloadhid.c b/platforms/avr/bootloaders/bootloadhid.c
index ae58760d7d..b91dca6d27 100644
--- a/platforms/avr/bootloaders/bootloadhid.c
+++ b/platforms/avr/bootloaders/bootloadhid.c
@@ -31,3 +31,10 @@ __attribute__((weak)) void bootloader_jump(void) {
     for (;;)
         ;
 }
+
+__attribute__((weak)) void mcu_reset(void) {
+    // watchdog reset
+    wdt_enable(WDTO_250MS);
+    for (;;)
+        ;
+}
diff --git a/platforms/avr/bootloaders/caterina.c b/platforms/avr/bootloaders/caterina.c
index 82a16a3765..2b5f613d6d 100644
--- a/platforms/avr/bootloaders/caterina.c
+++ b/platforms/avr/bootloaders/caterina.c
@@ -37,3 +37,12 @@ __attribute__((weak)) void bootloader_jump(void) {
     while (1) {
     }
 }
+
+__attribute__((weak)) void mcu_reset(void) {
+    // setup watchdog timeout
+    wdt_enable(WDTO_60MS);
+
+    // wait for watchdog timer to trigger
+    while (1) {
+    }
+}
diff --git a/platforms/avr/bootloaders/custom.c b/platforms/avr/bootloaders/custom.c
index 624fbe242a..72b19f6671 100644
--- a/platforms/avr/bootloaders/custom.c
+++ b/platforms/avr/bootloaders/custom.c
@@ -15,5 +15,14 @@
  */
 
 #include "bootloader.h"
+#include <avr/wdt.h>
 
 __attribute__((weak)) void bootloader_jump(void) {}
+__attribute__((weak)) void mcu_reset(void) {
+    // setup watchdog timeout
+    wdt_enable(WDTO_60MS);
+
+    // wait for watchdog timer to trigger
+    while (1) {
+    }
+}
diff --git a/platforms/avr/bootloaders/dfu.c b/platforms/avr/bootloaders/dfu.c
index 06b2c8963a..dbbb5f4ab6 100644
--- a/platforms/avr/bootloaders/dfu.c
+++ b/platforms/avr/bootloaders/dfu.c
@@ -34,8 +34,15 @@ __attribute__((weak)) void bootloader_jump(void) {
     UCSR1B = 0;
     _delay_ms(5); // 5 seems to work fine
 
-    // watchdog reset
     reset_key = BOOTLOADER_RESET_KEY;
+    // watchdog reset
+    wdt_enable(WDTO_250MS);
+    for (;;)
+        ;
+}
+
+__attribute__((weak)) void mcu_reset(void) {
+    // watchdog reset
     wdt_enable(WDTO_250MS);
     for (;;)
         ;
diff --git a/platforms/avr/bootloaders/halfkay.c b/platforms/avr/bootloaders/halfkay.c
index 651696f988..402f5f2778 100644
--- a/platforms/avr/bootloaders/halfkay.c
+++ b/platforms/avr/bootloaders/halfkay.c
@@ -17,6 +17,7 @@
 #include "bootloader.h"
 
 #include <avr/interrupt.h>
+#include <avr/wdt.h>
 #include <util/delay.h>
 
 __attribute__((weak)) void bootloader_jump(void) {
@@ -126,3 +127,12 @@ __attribute__((weak)) void bootloader_jump(void) {
     asm volatile("jmp 0x1FC00");
 #endif
 }
+
+__attribute__((weak)) void mcu_reset(void) {
+    // setup watchdog timeout
+    wdt_enable(WDTO_60MS);
+
+    // wait for watchdog timer to trigger
+    while (1) {
+    }
+}
diff --git a/platforms/avr/bootloaders/usbasploader.c b/platforms/avr/bootloaders/usbasploader.c
index 008bd16069..333010eefa 100644
--- a/platforms/avr/bootloaders/usbasploader.c
+++ b/platforms/avr/bootloaders/usbasploader.c
@@ -54,3 +54,12 @@ __attribute__((weak)) void bootloader_jump(void) {
 #endif
                    [bootaddrme] "M"((((FLASH_SIZE - BOOTLOADER_SIZE) >> 1) >> 8) & 0xff), [bootaddrlo] "M"((((FLASH_SIZE - BOOTLOADER_SIZE) >> 1) >> 0) & 0xff));
 }
+
+__attribute__((weak)) void mcu_reset(void) {
+    // setup watchdog timeout
+    wdt_enable(WDTO_15MS);
+
+    // wait for watchdog timer to trigger
+    while (1) {
+    }
+}
diff --git a/platforms/avr/drivers/hd44780.c b/platforms/avr/drivers/hd44780.c
deleted file mode 100644
index f15d7d0da8..0000000000
--- a/platforms/avr/drivers/hd44780.c
+++ /dev/null
@@ -1,542 +0,0 @@
-/****************************************************************************
- Title:     HD44780U LCD library
- Author:    Peter Fleury <pfleury@gmx.ch>  http://tinyurl.com/peterfleury
- License:   GNU General Public License Version 3
- File:	    $Id: lcd.c,v 1.15.2.2 2015/01/17 12:16:05 peter Exp $
- Software:  AVR-GCC 3.3
- Target:    any AVR device, memory mapped mode only for AT90S4414/8515/Mega
-
- DESCRIPTION
-       Basic routines for interfacing a HD44780U-based text lcd display
-
-       Originally based on Volker Oth's lcd library,
-       changed lcd_init(), added additional constants for lcd_command(),
-       added 4-bit I/O mode, improved and optimized code.
-
-       Library can be operated in memory mapped mode (LCD_IO_MODE=0) or in
-       4-bit IO port mode (LCD_IO_MODE=1). 8-bit IO port mode not supported.
-
-       Memory mapped mode compatible with Kanda STK200, but supports also
-       generation of R/W signal through A8 address line.
-
- USAGE
-       See the C include lcd.h file for a description of each function
-
-*****************************************************************************/
-#include <inttypes.h>
-#include <avr/io.h>
-#include <avr/pgmspace.h>
-#include <util/delay.h>
-#include "hd44780.h"
-
-/*
-** constants/macros
-*/
-#define DDR(x) (*(&x - 1)) /* address of data direction register of port x */
-#if defined(__AVR_ATmega64__) || defined(__AVR_ATmega128__)
-/* on ATmega64/128 PINF is on port 0x00 and not 0x60 */
-#    define PIN(x) (&PORTF == &(x) ? _SFR_IO8(0x00) : (*(&x - 2)))
-#else
-#    define PIN(x) (*(&x - 2)) /* address of input register of port x          */
-#endif
-
-#if LCD_IO_MODE
-#    define lcd_e_delay() _delay_us(LCD_DELAY_ENABLE_PULSE)
-#    define lcd_e_high() LCD_E_PORT |= _BV(LCD_E_PIN);
-#    define lcd_e_low() LCD_E_PORT &= ~_BV(LCD_E_PIN);
-#    define lcd_e_toggle() toggle_e()
-#    define lcd_rw_high() LCD_RW_PORT |= _BV(LCD_RW_PIN)
-#    define lcd_rw_low() LCD_RW_PORT &= ~_BV(LCD_RW_PIN)
-#    define lcd_rs_high() LCD_RS_PORT |= _BV(LCD_RS_PIN)
-#    define lcd_rs_low() LCD_RS_PORT &= ~_BV(LCD_RS_PIN)
-#endif
-
-#if LCD_IO_MODE
-#    if LCD_LINES == 1
-#        define LCD_FUNCTION_DEFAULT LCD_FUNCTION_4BIT_1LINE
-#    else
-#        define LCD_FUNCTION_DEFAULT LCD_FUNCTION_4BIT_2LINES
-#    endif
-#else
-#    if LCD_LINES == 1
-#        define LCD_FUNCTION_DEFAULT LCD_FUNCTION_8BIT_1LINE
-#    else
-#        define LCD_FUNCTION_DEFAULT LCD_FUNCTION_8BIT_2LINES
-#    endif
-#endif
-
-#if LCD_CONTROLLER_KS0073
-#    if LCD_LINES == 4
-
-#        define KS0073_EXTENDED_FUNCTION_REGISTER_ON 0x2C  /* |0|010|1100 4-bit mode, extension-bit RE = 1 */
-#        define KS0073_EXTENDED_FUNCTION_REGISTER_OFF 0x28 /* |0|010|1000 4-bit mode, extension-bit RE = 0 */
-#        define KS0073_4LINES_MODE 0x09                    /* |0|000|1001 4 lines mode */
-
-#    endif
-#endif
-
-/*
-** function prototypes
-*/
-#if LCD_IO_MODE
-static void toggle_e(void);
-#endif
-
-/*
-** local functions
-*/
-
-/*************************************************************************
-delay for a minimum of <us> microseconds
-the number of loops is calculated at compile-time from MCU clock frequency
-*************************************************************************/
-#define delay(us) _delay_us(us)
-
-#if LCD_IO_MODE
-/* toggle Enable Pin to initiate write */
-static void toggle_e(void) {
-    lcd_e_high();
-    lcd_e_delay();
-    lcd_e_low();
-}
-#endif
-
-/*************************************************************************
-Low-level function to write byte to LCD controller
-Input:    data   byte to write to LCD
-          rs     1: write data
-                 0: write instruction
-Returns:  none
-*************************************************************************/
-#if LCD_IO_MODE
-static void lcd_write(uint8_t data, uint8_t rs) {
-    unsigned char dataBits;
-
-    if (rs) { /* write data        (RS=1, RW=0) */
-        lcd_rs_high();
-    } else { /* write instruction (RS=0, RW=0) */
-        lcd_rs_low();
-    }
-    lcd_rw_low(); /* RW=0  write mode      */
-
-    if ((&LCD_DATA0_PORT == &LCD_DATA1_PORT) && (&LCD_DATA1_PORT == &LCD_DATA2_PORT) && (&LCD_DATA2_PORT == &LCD_DATA3_PORT) && (LCD_DATA0_PIN == 0) && (LCD_DATA1_PIN == 1) && (LCD_DATA2_PIN == 2) && (LCD_DATA3_PIN == 3)) {
-        /* configure data pins as output */
-        DDR(LCD_DATA0_PORT) |= 0x0F;
-
-        /* output high nibble first */
-        dataBits       = LCD_DATA0_PORT & 0xF0;
-        LCD_DATA0_PORT = dataBits | ((data >> 4) & 0x0F);
-        lcd_e_toggle();
-
-        /* output low nibble */
-        LCD_DATA0_PORT = dataBits | (data & 0x0F);
-        lcd_e_toggle();
-
-        /* all data pins high (inactive) */
-        LCD_DATA0_PORT = dataBits | 0x0F;
-    } else {
-        /* configure data pins as output */
-        DDR(LCD_DATA0_PORT) |= _BV(LCD_DATA0_PIN);
-        DDR(LCD_DATA1_PORT) |= _BV(LCD_DATA1_PIN);
-        DDR(LCD_DATA2_PORT) |= _BV(LCD_DATA2_PIN);
-        DDR(LCD_DATA3_PORT) |= _BV(LCD_DATA3_PIN);
-
-        /* output high nibble first */
-        LCD_DATA3_PORT &= ~_BV(LCD_DATA3_PIN);
-        LCD_DATA2_PORT &= ~_BV(LCD_DATA2_PIN);
-        LCD_DATA1_PORT &= ~_BV(LCD_DATA1_PIN);
-        LCD_DATA0_PORT &= ~_BV(LCD_DATA0_PIN);
-        if (data & 0x80) LCD_DATA3_PORT |= _BV(LCD_DATA3_PIN);
-        if (data & 0x40) LCD_DATA2_PORT |= _BV(LCD_DATA2_PIN);
-        if (data & 0x20) LCD_DATA1_PORT |= _BV(LCD_DATA1_PIN);
-        if (data & 0x10) LCD_DATA0_PORT |= _BV(LCD_DATA0_PIN);
-        lcd_e_toggle();
-
-        /* output low nibble */
-        LCD_DATA3_PORT &= ~_BV(LCD_DATA3_PIN);
-        LCD_DATA2_PORT &= ~_BV(LCD_DATA2_PIN);
-        LCD_DATA1_PORT &= ~_BV(LCD_DATA1_PIN);
-        LCD_DATA0_PORT &= ~_BV(LCD_DATA0_PIN);
-        if (data & 0x08) LCD_DATA3_PORT |= _BV(LCD_DATA3_PIN);
-        if (data & 0x04) LCD_DATA2_PORT |= _BV(LCD_DATA2_PIN);
-        if (data & 0x02) LCD_DATA1_PORT |= _BV(LCD_DATA1_PIN);
-        if (data & 0x01) LCD_DATA0_PORT |= _BV(LCD_DATA0_PIN);
-        lcd_e_toggle();
-
-        /* all data pins high (inactive) */
-        LCD_DATA0_PORT |= _BV(LCD_DATA0_PIN);
-        LCD_DATA1_PORT |= _BV(LCD_DATA1_PIN);
-        LCD_DATA2_PORT |= _BV(LCD_DATA2_PIN);
-        LCD_DATA3_PORT |= _BV(LCD_DATA3_PIN);
-    }
-}
-#else
-#    define lcd_write(d, rs)                        \
-        if (rs)                                     \
-            *(volatile uint8_t *)(LCD_IO_DATA) = d; \
-        else                                        \
-            *(volatile uint8_t *)(LCD_IO_FUNCTION) = d;
-/* rs==0 -> write instruction to LCD_IO_FUNCTION */
-/* rs==1 -> write data to LCD_IO_DATA */
-#endif
-
-/*************************************************************************
-Low-level function to read byte from LCD controller
-Input:    rs     1: read data
-                 0: read busy flag / address counter
-Returns:  byte read from LCD controller
-*************************************************************************/
-#if LCD_IO_MODE
-static uint8_t lcd_read(uint8_t rs) {
-    uint8_t data;
-
-    if (rs)
-        lcd_rs_high(); /* RS=1: read data      */
-    else
-        lcd_rs_low(); /* RS=0: read busy flag */
-    lcd_rw_high();    /* RW=1  read mode      */
-
-    if ((&LCD_DATA0_PORT == &LCD_DATA1_PORT) && (&LCD_DATA1_PORT == &LCD_DATA2_PORT) && (&LCD_DATA2_PORT == &LCD_DATA3_PORT) && (LCD_DATA0_PIN == 0) && (LCD_DATA1_PIN == 1) && (LCD_DATA2_PIN == 2) && (LCD_DATA3_PIN == 3)) {
-        DDR(LCD_DATA0_PORT) &= 0xF0; /* configure data pins as input */
-
-        lcd_e_high();
-        lcd_e_delay();
-        data = PIN(LCD_DATA0_PORT) << 4; /* read high nibble first */
-        lcd_e_low();
-
-        lcd_e_delay(); /* Enable 500ns low       */
-
-        lcd_e_high();
-        lcd_e_delay();
-        data |= PIN(LCD_DATA0_PORT) & 0x0F; /* read low nibble        */
-        lcd_e_low();
-    } else {
-        /* configure data pins as input */
-        DDR(LCD_DATA0_PORT) &= ~_BV(LCD_DATA0_PIN);
-        DDR(LCD_DATA1_PORT) &= ~_BV(LCD_DATA1_PIN);
-        DDR(LCD_DATA2_PORT) &= ~_BV(LCD_DATA2_PIN);
-        DDR(LCD_DATA3_PORT) &= ~_BV(LCD_DATA3_PIN);
-
-        /* read high nibble first */
-        lcd_e_high();
-        lcd_e_delay();
-        data = 0;
-        if (PIN(LCD_DATA0_PORT) & _BV(LCD_DATA0_PIN)) data |= 0x10;
-        if (PIN(LCD_DATA1_PORT) & _BV(LCD_DATA1_PIN)) data |= 0x20;
-        if (PIN(LCD_DATA2_PORT) & _BV(LCD_DATA2_PIN)) data |= 0x40;
-        if (PIN(LCD_DATA3_PORT) & _BV(LCD_DATA3_PIN)) data |= 0x80;
-        lcd_e_low();
-
-        lcd_e_delay(); /* Enable 500ns low       */
-
-        /* read low nibble */
-        lcd_e_high();
-        lcd_e_delay();
-        if (PIN(LCD_DATA0_PORT) & _BV(LCD_DATA0_PIN)) data |= 0x01;
-        if (PIN(LCD_DATA1_PORT) & _BV(LCD_DATA1_PIN)) data |= 0x02;
-        if (PIN(LCD_DATA2_PORT) & _BV(LCD_DATA2_PIN)) data |= 0x04;
-        if (PIN(LCD_DATA3_PORT) & _BV(LCD_DATA3_PIN)) data |= 0x08;
-        lcd_e_low();
-    }
-    return data;
-}
-#else
-#    define lcd_read(rs) (rs) ? *(volatile uint8_t *)(LCD_IO_DATA + LCD_IO_READ) : *(volatile uint8_t *)(LCD_IO_FUNCTION + LCD_IO_READ)
-/* rs==0 -> read instruction from LCD_IO_FUNCTION */
-/* rs==1 -> read data from LCD_IO_DATA */
-#endif
-
-/*************************************************************************
-loops while lcd is busy, returns address counter
-*************************************************************************/
-static uint8_t lcd_waitbusy(void)
-
-{
-    register uint8_t c;
-
-    /* wait until busy flag is cleared */
-    while ((c = lcd_read(0)) & (1 << LCD_BUSY)) {
-    }
-
-    /* the address counter is updated 4us after the busy flag is cleared */
-    delay(LCD_DELAY_BUSY_FLAG);
-
-    /* now read the address counter */
-    return (lcd_read(0)); // return address counter
-
-} /* lcd_waitbusy */
-
-/*************************************************************************
-Move cursor to the start of next line or to the first line if the cursor
-is already on the last line.
-*************************************************************************/
-static inline void lcd_newline(uint8_t pos) {
-    register uint8_t addressCounter;
-
-#if LCD_LINES == 1
-    addressCounter = 0;
-#endif
-#if LCD_LINES == 2
-    if (pos < (LCD_START_LINE2))
-        addressCounter = LCD_START_LINE2;
-    else
-        addressCounter = LCD_START_LINE1;
-#endif
-#if LCD_LINES == 4
-#    if KS0073_4LINES_MODE
-    if (pos < LCD_START_LINE2)
-        addressCounter = LCD_START_LINE2;
-    else if ((pos >= LCD_START_LINE2) && (pos < LCD_START_LINE3))
-        addressCounter = LCD_START_LINE3;
-    else if ((pos >= LCD_START_LINE3) && (pos < LCD_START_LINE4))
-        addressCounter = LCD_START_LINE4;
-    else
-        addressCounter = LCD_START_LINE1;
-#    else
-    if (pos < LCD_START_LINE3)
-        addressCounter = LCD_START_LINE2;
-    else if ((pos >= LCD_START_LINE2) && (pos < LCD_START_LINE4))
-        addressCounter = LCD_START_LINE3;
-    else if ((pos >= LCD_START_LINE3) && (pos < LCD_START_LINE2))
-        addressCounter = LCD_START_LINE4;
-    else
-        addressCounter = LCD_START_LINE1;
-#    endif
-#endif
-    lcd_command((1 << LCD_DDRAM) + addressCounter);
-
-} /* lcd_newline */
-
-/*
-** PUBLIC FUNCTIONS
-*/
-
-/*************************************************************************
-Send LCD controller instruction command
-Input:   instruction to send to LCD controller, see HD44780 data sheet
-Returns: none
-*************************************************************************/
-void lcd_command(uint8_t cmd) {
-    lcd_waitbusy();
-    lcd_write(cmd, 0);
-}
-
-/*************************************************************************
-Send data byte to LCD controller
-Input:   data to send to LCD controller, see HD44780 data sheet
-Returns: none
-*************************************************************************/
-void lcd_data(uint8_t data) {
-    lcd_waitbusy();
-    lcd_write(data, 1);
-}
-
-/*************************************************************************
-Set cursor to specified position
-Input:    x  horizontal position  (0: left most position)
-          y  vertical position    (0: first line)
-Returns:  none
-*************************************************************************/
-void lcd_gotoxy(uint8_t x, uint8_t y) {
-#if LCD_LINES == 1
-    lcd_command((1 << LCD_DDRAM) + LCD_START_LINE1 + x);
-#endif
-#if LCD_LINES == 2
-    if (y == 0)
-        lcd_command((1 << LCD_DDRAM) + LCD_START_LINE1 + x);
-    else
-        lcd_command((1 << LCD_DDRAM) + LCD_START_LINE2 + x);
-#endif
-#if LCD_LINES == 4
-    if (y == 0)
-        lcd_command((1 << LCD_DDRAM) + LCD_START_LINE1 + x);
-    else if (y == 1)
-        lcd_command((1 << LCD_DDRAM) + LCD_START_LINE2 + x);
-    else if (y == 2)
-        lcd_command((1 << LCD_DDRAM) + LCD_START_LINE3 + x);
-    else /* y==3 */
-        lcd_command((1 << LCD_DDRAM) + LCD_START_LINE4 + x);
-#endif
-
-} /* lcd_gotoxy */
-
-/*************************************************************************
-*************************************************************************/
-int lcd_getxy(void) {
-    return lcd_waitbusy();
-}
-
-/*************************************************************************
-Clear display and set cursor to home position
-*************************************************************************/
-void lcd_clrscr(void) {
-    lcd_command(1 << LCD_CLR);
-}
-
-/*************************************************************************
-Set cursor to home position
-*************************************************************************/
-void lcd_home(void) {
-    lcd_command(1 << LCD_HOME);
-}
-
-/*************************************************************************
-Display character at current cursor position
-Input:    character to be displayed
-Returns:  none
-*************************************************************************/
-void lcd_putc(char c) {
-    uint8_t pos;
-
-    pos = lcd_waitbusy(); // read busy-flag and address counter
-    if (c == '\n') {
-        lcd_newline(pos);
-    } else {
-#if LCD_WRAP_LINES == 1
-#    if LCD_LINES == 1
-        if (pos == LCD_START_LINE1 + LCD_DISP_LENGTH) {
-            lcd_write((1 << LCD_DDRAM) + LCD_START_LINE1, 0);
-        }
-#    elif LCD_LINES == 2
-        if (pos == LCD_START_LINE1 + LCD_DISP_LENGTH) {
-            lcd_write((1 << LCD_DDRAM) + LCD_START_LINE2, 0);
-        } else if (pos == LCD_START_LINE2 + LCD_DISP_LENGTH) {
-            lcd_write((1 << LCD_DDRAM) + LCD_START_LINE1, 0);
-        }
-#    elif LCD_LINES == 4
-        if (pos == LCD_START_LINE1 + LCD_DISP_LENGTH) {
-            lcd_write((1 << LCD_DDRAM) + LCD_START_LINE2, 0);
-        } else if (pos == LCD_START_LINE2 + LCD_DISP_LENGTH) {
-            lcd_write((1 << LCD_DDRAM) + LCD_START_LINE3, 0);
-        } else if (pos == LCD_START_LINE3 + LCD_DISP_LENGTH) {
-            lcd_write((1 << LCD_DDRAM) + LCD_START_LINE4, 0);
-        } else if (pos == LCD_START_LINE4 + LCD_DISP_LENGTH) {
-            lcd_write((1 << LCD_DDRAM) + LCD_START_LINE1, 0);
-        }
-#    endif
-        lcd_waitbusy();
-#endif
-        lcd_write(c, 1);
-    }
-
-} /* lcd_putc */
-
-/*************************************************************************
-Display string without auto linefeed
-Input:    string to be displayed
-Returns:  none
-*************************************************************************/
-void lcd_puts(const char *s)
-/* print string on lcd (no auto linefeed) */
-{
-    register char c;
-
-    while ((c = *s++)) {
-        lcd_putc(c);
-    }
-
-} /* lcd_puts */
-
-/*************************************************************************
-Display string from program memory without auto linefeed
-Input:     string from program memory be be displayed
-Returns:   none
-*************************************************************************/
-void lcd_puts_p(const char *progmem_s)
-/* print string from program memory on lcd (no auto linefeed) */
-{
-    register char c;
-
-    while ((c = pgm_read_byte(progmem_s++))) {
-        lcd_putc(c);
-    }
-
-} /* lcd_puts_p */
-
-/*************************************************************************
-Initialize display and select type of cursor
-Input:    dispAttr LCD_DISP_OFF            display off
-                   LCD_DISP_ON             display on, cursor off
-                   LCD_DISP_ON_CURSOR      display on, cursor on
-                   LCD_DISP_CURSOR_BLINK   display on, cursor on flashing
-Returns:  none
-*************************************************************************/
-void lcd_init(uint8_t dispAttr) {
-#if LCD_IO_MODE
-    /*
-     *  Initialize LCD to 4 bit I/O mode
-     */
-
-    if ((&LCD_DATA0_PORT == &LCD_DATA1_PORT) && (&LCD_DATA1_PORT == &LCD_DATA2_PORT) && (&LCD_DATA2_PORT == &LCD_DATA3_PORT) && (&LCD_RS_PORT == &LCD_DATA0_PORT) && (&LCD_RW_PORT == &LCD_DATA0_PORT) && (&LCD_E_PORT == &LCD_DATA0_PORT) && (LCD_DATA0_PIN == 0) && (LCD_DATA1_PIN == 1) && (LCD_DATA2_PIN == 2) && (LCD_DATA3_PIN == 3) && (LCD_RS_PIN == 4) && (LCD_RW_PIN == 5) && (LCD_E_PIN == 6)) {
-        /* configure all port bits as output (all LCD lines on same port) */
-        DDR(LCD_DATA0_PORT) |= 0x7F;
-    } else if ((&LCD_DATA0_PORT == &LCD_DATA1_PORT) && (&LCD_DATA1_PORT == &LCD_DATA2_PORT) && (&LCD_DATA2_PORT == &LCD_DATA3_PORT) && (LCD_DATA0_PIN == 0) && (LCD_DATA1_PIN == 1) && (LCD_DATA2_PIN == 2) && (LCD_DATA3_PIN == 3)) {
-        /* configure all port bits as output (all LCD data lines on same port, but control lines on different ports) */
-        DDR(LCD_DATA0_PORT) |= 0x0F;
-        DDR(LCD_RS_PORT) |= _BV(LCD_RS_PIN);
-        DDR(LCD_RW_PORT) |= _BV(LCD_RW_PIN);
-        DDR(LCD_E_PORT) |= _BV(LCD_E_PIN);
-    } else {
-        /* configure all port bits as output (LCD data and control lines on different ports */
-        DDR(LCD_RS_PORT) |= _BV(LCD_RS_PIN);
-        DDR(LCD_RW_PORT) |= _BV(LCD_RW_PIN);
-        DDR(LCD_E_PORT) |= _BV(LCD_E_PIN);
-        DDR(LCD_DATA0_PORT) |= _BV(LCD_DATA0_PIN);
-        DDR(LCD_DATA1_PORT) |= _BV(LCD_DATA1_PIN);
-        DDR(LCD_DATA2_PORT) |= _BV(LCD_DATA2_PIN);
-        DDR(LCD_DATA3_PORT) |= _BV(LCD_DATA3_PIN);
-    }
-    delay(LCD_DELAY_BOOTUP); /* wait 16ms or more after power-on       */
-
-    /* initial write to lcd is 8bit */
-    LCD_DATA1_PORT |= _BV(LCD_DATA1_PIN); // LCD_FUNCTION>>4;
-    LCD_DATA0_PORT |= _BV(LCD_DATA0_PIN); // LCD_FUNCTION_8BIT>>4;
-    lcd_e_toggle();
-    delay(LCD_DELAY_INIT); /* delay, busy flag can't be checked here */
-
-    /* repeat last command */
-    lcd_e_toggle();
-    delay(LCD_DELAY_INIT_REP); /* delay, busy flag can't be checked here */
-
-    /* repeat last command a third time */
-    lcd_e_toggle();
-    delay(LCD_DELAY_INIT_REP); /* delay, busy flag can't be checked here */
-
-    /* now configure for 4bit mode */
-    LCD_DATA0_PORT &= ~_BV(LCD_DATA0_PIN); // LCD_FUNCTION_4BIT_1LINE>>4
-    lcd_e_toggle();
-    delay(LCD_DELAY_INIT_4BIT); /* some displays need this additional delay */
-
-    /* from now the LCD only accepts 4 bit I/O, we can use lcd_command() */
-#else
-    /*
-     * Initialize LCD to 8 bit memory mapped mode
-     */
-
-    /* enable external SRAM (memory mapped lcd) and one wait state */
-    MCUCR = _BV(SRE) | _BV(SRW);
-
-    /* reset LCD */
-    delay(LCD_DELAY_BOOTUP);               /* wait 16ms after power-on     */
-    lcd_write(LCD_FUNCTION_8BIT_1LINE, 0); /* function set: 8bit interface */
-    delay(LCD_DELAY_INIT);                 /* wait 5ms                     */
-    lcd_write(LCD_FUNCTION_8BIT_1LINE, 0); /* function set: 8bit interface */
-    delay(LCD_DELAY_INIT_REP);             /* wait 64us                    */
-    lcd_write(LCD_FUNCTION_8BIT_1LINE, 0); /* function set: 8bit interface */
-    delay(LCD_DELAY_INIT_REP);             /* wait 64us                    */
-#endif
-
-#if KS0073_4LINES_MODE
-    /* Display with KS0073 controller requires special commands for enabling 4 line mode */
-    lcd_command(KS0073_EXTENDED_FUNCTION_REGISTER_ON);
-    lcd_command(KS0073_4LINES_MODE);
-    lcd_command(KS0073_EXTENDED_FUNCTION_REGISTER_OFF);
-#else
-    lcd_command(LCD_FUNCTION_DEFAULT);     /* function set: display lines  */
-#endif
-    lcd_command(LCD_DISP_OFF);     /* display off                  */
-    lcd_clrscr();                  /* display clear                */
-    lcd_command(LCD_MODE_DEFAULT); /* set entry mode               */
-    lcd_command(dispAttr);         /* display/cursor control       */
-
-} /* lcd_init */
diff --git a/platforms/avr/drivers/hd44780.h b/platforms/avr/drivers/hd44780.h
deleted file mode 100644
index 08e60f8a44..0000000000
--- a/platforms/avr/drivers/hd44780.h
+++ /dev/null
@@ -1,348 +0,0 @@
-/*************************************************************************
- Title	:   C include file for the HD44780U LCD library (lcd.c)
- Author:    Peter Fleury <pfleury@gmx.ch>  http://tinyurl.com/peterfleury
- License:   GNU General Public License Version 3
- File:	    $Id: lcd.h,v 1.14.2.4 2015/01/20 17:16:07 peter Exp $
- Software:  AVR-GCC 4.x
- Hardware:  any AVR device, memory mapped mode only for AVR with
-            memory mapped interface (AT90S8515/ATmega8515/ATmega128)
-***************************************************************************/
-
-/**
- @mainpage
- Collection of libraries for AVR-GCC
- @author Peter Fleury pfleury@gmx.ch http://tinyurl.com/peterfleury
- @copyright (C) 2015 Peter Fleury, GNU General Public License Version 3
-
- @file
- @defgroup pfleury_lcd LCD library <lcd.h>
- @code #include <lcd.h> @endcode
-
- @brief Basic routines for interfacing a HD44780U-based character LCD display
-
- LCD character displays can be found in many devices, like espresso machines, laser printers.
- The Hitachi HD44780 controller and its compatible controllers like Samsung KS0066U have become an industry standard for these types of displays.
-
- This library allows easy interfacing with a HD44780 compatible display and can be
- operated in memory mapped mode (LCD_IO_MODE defined as 0 in the include file lcd.h.) or in
- 4-bit IO port mode (LCD_IO_MODE defined as 1). 8-bit IO port mode is not supported.
-
- Memory mapped mode is compatible with old Kanda STK200 starter kit, but also supports
- generation of R/W signal through A8 address line.
-
- @see The chapter <a href=" http://homepage.hispeed.ch/peterfleury/avr-lcd44780.html" target="_blank">Interfacing a HD44780 Based LCD to an AVR</a>
-      on my home page, which shows example circuits how to connect an LCD to an AVR controller.
-
- @author Peter Fleury pfleury@gmx.ch http://tinyurl.com/peterfleury
-
- @version   2.0
-
- @copyright (C) 2015 Peter Fleury, GNU General Public License Version 3
-
-*/
-
-#pragma once
-
-#include <inttypes.h>
-#include <avr/pgmspace.h>
-
-#if (__GNUC__ * 100 + __GNUC_MINOR__) < 405
-#    error "This library requires AVR-GCC 4.5 or later, update to newer AVR-GCC compiler !"
-#endif
-
-/**@{*/
-
-/*
- * LCD and target specific definitions below can be defined in a separate include file with name lcd_definitions.h instead modifying this file
- * by adding -D_LCD_DEFINITIONS_FILE to the CDEFS section in the Makefile
- * All definitions added to the file lcd_definitions.h will override the default definitions from lcd.h
- */
-#ifdef _LCD_DEFINITIONS_FILE
-#    include "lcd_definitions.h"
-#endif
-
-/**
- * @name  Definition for LCD controller type
- * Use 0 for HD44780 controller, change to 1 for displays with KS0073 controller.
- */
-#ifndef LCD_CONTROLLER_KS0073
-#    define LCD_CONTROLLER_KS0073 0 /**< Use 0 for HD44780 controller, 1 for KS0073 controller */
-#endif
-
-/**
- * @name  Definitions for Display Size
- * Change these definitions to adapt setting to your display
- *
- * These definitions can be defined in a separate include file \b lcd_definitions.h instead modifying this file by
- * adding -D_LCD_DEFINITIONS_FILE to the CDEFS section in the Makefile.
- * All definitions added to the file lcd_definitions.h will override the default definitions from lcd.h
- *
- */
-#ifndef LCD_LINES
-#    define LCD_LINES 2 /**< number of visible lines of the display */
-#endif
-#ifndef LCD_DISP_LENGTH
-#    define LCD_DISP_LENGTH 16 /**< visibles characters per line of the display */
-#endif
-#ifndef LCD_LINE_LENGTH
-#    define LCD_LINE_LENGTH 0x40 /**< internal line length of the display    */
-#endif
-#ifndef LCD_START_LINE1
-#    define LCD_START_LINE1 0x00 /**< DDRAM address of first char of line 1 */
-#endif
-#ifndef LCD_START_LINE2
-#    define LCD_START_LINE2 0x40 /**< DDRAM address of first char of line 2 */
-#endif
-#ifndef LCD_START_LINE3
-#    define LCD_START_LINE3 0x14 /**< DDRAM address of first char of line 3 */
-#endif
-#ifndef LCD_START_LINE4
-#    define LCD_START_LINE4 0x54 /**< DDRAM address of first char of line 4 */
-#endif
-#ifndef LCD_WRAP_LINES
-#    define LCD_WRAP_LINES 0 /**< 0: no wrap, 1: wrap at end of visibile line */
-#endif
-
-/**
- * @name Definitions for 4-bit IO mode
- *
- * The four LCD data lines and the three control lines RS, RW, E can be on the
- * same port or on different ports.
- * Change LCD_RS_PORT, LCD_RW_PORT, LCD_E_PORT if you want the control lines on
- * different ports.
- *
- * Normally the four data lines should be mapped to bit 0..3 on one port, but it
- * is possible to connect these data lines in different order or even on different
- * ports by adapting the LCD_DATAx_PORT and LCD_DATAx_PIN definitions.
- *
- * Adjust these definitions to your target.\n
- * These definitions can be defined in a separate include file \b lcd_definitions.h instead modifying this file by
- * adding \b -D_LCD_DEFINITIONS_FILE to the \b CDEFS section in the Makefile.
- * All definitions added to the file lcd_definitions.h will override the default definitions from lcd.h
- *
- */
-#define LCD_IO_MODE 1 /**< 0: memory mapped mode, 1: IO port mode */
-
-#if LCD_IO_MODE
-
-#    ifndef LCD_PORT
-#        define LCD_PORT PORTA /**< port for the LCD lines   */
-#    endif
-#    ifndef LCD_DATA0_PORT
-#        define LCD_DATA0_PORT LCD_PORT /**< port for 4bit data bit 0 */
-#    endif
-#    ifndef LCD_DATA1_PORT
-#        define LCD_DATA1_PORT LCD_PORT /**< port for 4bit data bit 1 */
-#    endif
-#    ifndef LCD_DATA2_PORT
-#        define LCD_DATA2_PORT LCD_PORT /**< port for 4bit data bit 2 */
-#    endif
-#    ifndef LCD_DATA3_PORT
-#        define LCD_DATA3_PORT LCD_PORT /**< port for 4bit data bit 3 */
-#    endif
-#    ifndef LCD_DATA0_PIN
-#        define LCD_DATA0_PIN 4 /**< pin for 4bit data bit 0  */
-#    endif
-#    ifndef LCD_DATA1_PIN
-#        define LCD_DATA1_PIN 5 /**< pin for 4bit data bit 1  */
-#    endif
-#    ifndef LCD_DATA2_PIN
-#        define LCD_DATA2_PIN 6 /**< pin for 4bit data bit 2  */
-#    endif
-#    ifndef LCD_DATA3_PIN
-#        define LCD_DATA3_PIN 7 /**< pin for 4bit data bit 3  */
-#    endif
-#    ifndef LCD_RS_PORT
-#        define LCD_RS_PORT LCD_PORT /**< port for RS line         */
-#    endif
-#    ifndef LCD_RS_PIN
-#        define LCD_RS_PIN 3 /**< pin  for RS line         */
-#    endif
-#    ifndef LCD_RW_PORT
-#        define LCD_RW_PORT LCD_PORT /**< port for RW line         */
-#    endif
-#    ifndef LCD_RW_PIN
-#        define LCD_RW_PIN 2 /**< pin  for RW line         */
-#    endif
-#    ifndef LCD_E_PORT
-#        define LCD_E_PORT LCD_PORT /**< port for Enable line     */
-#    endif
-#    ifndef LCD_E_PIN
-#        define LCD_E_PIN 1 /**< pin  for Enable line     */
-#    endif
-
-#elif defined(__AVR_AT90S4414__) || defined(__AVR_AT90S8515__) || defined(__AVR_ATmega64__) || defined(__AVR_ATmega8515__) || defined(__AVR_ATmega103__) || defined(__AVR_ATmega128__) || defined(__AVR_ATmega161__) || defined(__AVR_ATmega162__)
-/*
- * memory mapped mode is only supported when the device has an external data memory interface
- */
-#    define LCD_IO_DATA 0xC000     /* A15=E=1, A14=RS=1                 */
-#    define LCD_IO_FUNCTION 0x8000 /* A15=E=1, A14=RS=0                 */
-#    define LCD_IO_READ 0x0100     /* A8 =R/W=1 (R/W: 1=Read, 0=Write   */
-
-#else
-#    error "external data memory interface not available for this device, use 4-bit IO port mode"
-
-#endif
-
-/**
- * @name Definitions of delays
- * Used to calculate delay timers.
- * Adapt the F_CPU define in the Makefile to the clock frequency in Hz of your target
- *
- * These delay times can be adjusted, if some displays require different delays.\n
- * These definitions can be defined in a separate include file \b lcd_definitions.h instead modifying this file by
- * adding \b -D_LCD_DEFINITIONS_FILE to the \b CDEFS section in the Makefile.
- * All definitions added to the file lcd_definitions.h will override the default definitions from lcd.h
- */
-#ifndef LCD_DELAY_BOOTUP
-#    define LCD_DELAY_BOOTUP 16000 /**< delay in micro seconds after power-on  */
-#endif
-#ifndef LCD_DELAY_INIT
-#    define LCD_DELAY_INIT 5000 /**< delay in micro seconds after initialization command sent  */
-#endif
-#ifndef LCD_DELAY_INIT_REP
-#    define LCD_DELAY_INIT_REP 64 /**< delay in micro seconds after initialization command repeated */
-#endif
-#ifndef LCD_DELAY_INIT_4BIT
-#    define LCD_DELAY_INIT_4BIT 64 /**< delay in micro seconds after setting 4-bit mode */
-#endif
-#ifndef LCD_DELAY_BUSY_FLAG
-#    define LCD_DELAY_BUSY_FLAG 4 /**< time in micro seconds the address counter is updated after busy flag is cleared */
-#endif
-#ifndef LCD_DELAY_ENABLE_PULSE
-#    define LCD_DELAY_ENABLE_PULSE 1 /**< enable signal pulse width in micro seconds */
-#endif
-
-/**
- * @name Definitions for LCD command instructions
- * The constants define the various LCD controller instructions which can be passed to the
- * function lcd_command(), see HD44780 data sheet for a complete description.
- */
-
-/* instruction register bit positions, see HD44780U data sheet */
-#define LCD_CLR 0             /* DB0: clear display                  */
-#define LCD_HOME 1            /* DB1: return to home position        */
-#define LCD_ENTRY_MODE 2      /* DB2: set entry mode                 */
-#define LCD_ENTRY_INC 1       /*   DB1: 1=increment, 0=decrement     */
-#define LCD_ENTRY_SHIFT 0     /*   DB2: 1=display shift on           */
-#define LCD_ON 3              /* DB3: turn lcd/cursor on             */
-#define LCD_ON_DISPLAY 2      /*   DB2: turn display on              */
-#define LCD_ON_CURSOR 1       /*   DB1: turn cursor on               */
-#define LCD_ON_BLINK 0        /*     DB0: blinking cursor ?          */
-#define LCD_MOVE 4            /* DB4: move cursor/display            */
-#define LCD_MOVE_DISP 3       /*   DB3: move display (0-> cursor) ?  */
-#define LCD_MOVE_RIGHT 2      /*   DB2: move right (0-> left) ?      */
-#define LCD_FUNCTION 5        /* DB5: function set                   */
-#define LCD_FUNCTION_8BIT 4   /*   DB4: set 8BIT mode (0->4BIT mode) */
-#define LCD_FUNCTION_2LINES 3 /*   DB3: two lines (0->one line)      */
-#define LCD_FUNCTION_10DOTS 2 /*   DB2: 5x10 font (0->5x7 font)      */
-#define LCD_CGRAM 6           /* DB6: set CG RAM address             */
-#define LCD_DDRAM 7           /* DB7: set DD RAM address             */
-#define LCD_BUSY 7            /* DB7: LCD is busy                    */
-
-/* set entry mode: display shift on/off, dec/inc cursor move direction */
-#define LCD_ENTRY_DEC 0x04       /* display shift off, dec cursor move dir */
-#define LCD_ENTRY_DEC_SHIFT 0x05 /* display shift on,  dec cursor move dir */
-#define LCD_ENTRY_INC_ 0x06      /* display shift off, inc cursor move dir */
-#define LCD_ENTRY_INC_SHIFT 0x07 /* display shift on,  inc cursor move dir */
-
-/* display on/off, cursor on/off, blinking char at cursor position */
-#define LCD_DISP_OFF 0x08             /* display off                            */
-#define LCD_DISP_ON 0x0C              /* display on, cursor off                 */
-#define LCD_DISP_ON_BLINK 0x0D        /* display on, cursor off, blink char     */
-#define LCD_DISP_ON_CURSOR 0x0E       /* display on, cursor on                  */
-#define LCD_DISP_ON_CURSOR_BLINK 0x0F /* display on, cursor on, blink char      */
-
-/* move cursor/shift display */
-#define LCD_MOVE_CURSOR_LEFT 0x10  /* move cursor left  (decrement)          */
-#define LCD_MOVE_CURSOR_RIGHT 0x14 /* move cursor right (increment)          */
-#define LCD_MOVE_DISP_LEFT 0x18    /* shift display left                     */
-#define LCD_MOVE_DISP_RIGHT 0x1C   /* shift display right                    */
-
-/* function set: set interface data length and number of display lines */
-#define LCD_FUNCTION_4BIT_1LINE 0x20  /* 4-bit interface, single line, 5x7 dots */
-#define LCD_FUNCTION_4BIT_2LINES 0x28 /* 4-bit interface, dual line,   5x7 dots */
-#define LCD_FUNCTION_8BIT_1LINE 0x30  /* 8-bit interface, single line, 5x7 dots */
-#define LCD_FUNCTION_8BIT_2LINES 0x38 /* 8-bit interface, dual line,   5x7 dots */
-
-#define LCD_MODE_DEFAULT ((1 << LCD_ENTRY_MODE) | (1 << LCD_ENTRY_INC))
-
-/**
- *  @name Functions
- */
-
-/**
- @brief    Initialize display and select type of cursor
- @param    dispAttr \b LCD_DISP_OFF display off\n
-                    \b LCD_DISP_ON display on, cursor off\n
-                    \b LCD_DISP_ON_CURSOR display on, cursor on\n
-                    \b LCD_DISP_ON_CURSOR_BLINK display on, cursor on flashing
- @return  none
-*/
-extern void lcd_init(uint8_t dispAttr);
-
-/**
- @brief    Clear display and set cursor to home position
- @return   none
-*/
-extern void lcd_clrscr(void);
-
-/**
- @brief    Set cursor to home position
- @return   none
-*/
-extern void lcd_home(void);
-
-/**
- @brief    Set cursor to specified position
-
- @param    x horizontal position\n (0: left most position)
- @param    y vertical position\n   (0: first line)
- @return   none
-*/
-extern void lcd_gotoxy(uint8_t x, uint8_t y);
-
-/**
- @brief    Display character at current cursor position
- @param    c character to be displayed
- @return   none
-*/
-extern void lcd_putc(char c);
-
-/**
- @brief    Display string without auto linefeed
- @param    s string to be displayed
- @return   none
-*/
-extern void lcd_puts(const char *s);
-
-/**
- @brief    Display string from program memory without auto linefeed
- @param    progmem_s string from program memory be be displayed
- @return   none
- @see      lcd_puts_P
-*/
-extern void lcd_puts_p(const char *progmem_s);
-
-/**
- @brief    Send LCD controller instruction command
- @param    cmd instruction to send to LCD controller, see HD44780 data sheet
- @return   none
-*/
-extern void lcd_command(uint8_t cmd);
-
-/**
- @brief    Send data byte to LCD controller
-
- Similar to lcd_putc(), but without interpreting LF
- @param    data byte to send to LCD controller, see HD44780 data sheet
- @return   none
-*/
-extern void lcd_data(uint8_t data);
-
-/**
- @brief macros for automatically storing string constant in program memory
-*/
-#define lcd_puts_P(__s) lcd_puts_p(PSTR(__s))
-
-/**@}*/
diff --git a/platforms/avr/hardware_id.c b/platforms/avr/hardware_id.c
new file mode 100644
index 0000000000..b61f0d92df
--- /dev/null
+++ b/platforms/avr/hardware_id.c
@@ -0,0 +1,19 @@
+// Copyright 2022 QMK
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+// For some reason this bit is undocumented for some AVR parts and not defined in their avr-libc IO headers
+// See https://stackoverflow.com/questions/12350914/how-to-read-atmega-32-signature-row
+#ifndef SIGRD
+#    define SIGRD 5
+#endif // SIGRD
+
+#include <avr/boot.h>
+#include "hardware_id.h"
+
+hardware_id_t get_hardware_id(void) {
+    hardware_id_t id = {0};
+    for (uint8_t i = 0; i < 10; i += 1) {
+        ((uint8_t*)&id)[i] = boot_signature_byte_get(i + 0x0E);
+    }
+    return id;
+}
diff --git a/platforms/avr/platform.c b/platforms/avr/platform.c
index 3e35b4fe4c..37decb6ec8 100644
--- a/platforms/avr/platform.c
+++ b/platforms/avr/platform.c
@@ -16,6 +16,17 @@
 
 #include "platform_deps.h"
 
+static void disable_jtag(void) {
+// To use PF4-7 (PC2-5 on ATmega32A), disable JTAG by writing JTD bit twice within four cycles.
+#if (defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB647__) || defined(__AVR_AT90USB1286__) || defined(__AVR_AT90USB1287__) || defined(__AVR_ATmega16U4__) || defined(__AVR_ATmega32U4__))
+    MCUCR |= _BV(JTD);
+    MCUCR |= _BV(JTD);
+#elif defined(__AVR_ATmega32A__)
+    MCUCSR |= _BV(JTD);
+    MCUCSR |= _BV(JTD);
+#endif
+}
+
 void platform_setup(void) {
-    // do nothing
+    disable_jtag();
 }
diff --git a/platforms/avr/platform.mk b/platforms/avr/platform.mk
index 4d9cafaeef..978199b385 100644
--- a/platforms/avr/platform.mk
+++ b/platforms/avr/platform.mk
@@ -12,12 +12,24 @@ HEX = $(OBJCOPY) -O $(FORMAT) -R .eeprom -R .fuse -R .lock -R .signature
 EEP = $(OBJCOPY) -j .eeprom --set-section-flags=.eeprom="alloc,load" --change-section-lma .eeprom=0 --no-change-warnings -O $(FORMAT)
 BIN =
 
+# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105523
+ifneq ($(findstring 12.,$(shell avr-gcc --version 2>/dev/null)),)
+COMPILEFLAGS += --param=min-pagesize=0
+endif
+
 COMPILEFLAGS += -funsigned-char
 COMPILEFLAGS += -funsigned-bitfields
 COMPILEFLAGS += -ffunction-sections
 COMPILEFLAGS += -fdata-sections
 COMPILEFLAGS += -fpack-struct
 COMPILEFLAGS += -fshort-enums
+COMPILEFLAGS += -mcall-prologues
+
+# Linker relaxation is only possible if
+# link time optimizations are not enabled.
+ifeq ($(strip $(LTO_ENABLE)), no)
+	COMPILEFLAGS += -mrelax
+endif
 
 ASFLAGS += $(AVR_ASFLAGS)
 
@@ -28,7 +40,16 @@ CFLAGS += -fno-strict-aliasing
 CXXFLAGS += $(COMPILEFLAGS)
 CXXFLAGS += -fno-exceptions -std=c++11
 
-LDFLAGS +=-Wl,--gc-sections
+LDFLAGS += -Wl,--gc-sections
+
+# Use AVR's libc minimal printf implementation which has less features
+# and thus can shave ~400 bytes. Usually we use the xprintf
+# implementation but keyboards that use s(n)printf automatically
+# pull in the AVR libc implementation, which is ~900 bytes heavy.
+AVR_USE_MINIMAL_PRINTF ?= no
+ifeq ($(strip $(AVR_USE_MINIMAL_PRINTF)), yes)
+	LDFLAGS += -Wl,--whole-archive -lprintf_min -Wl,--no-whole-archive
+endif
 
 OPT_DEFS += -DF_CPU=$(F_CPU)UL
 
diff --git a/platforms/bootloader.h b/platforms/bootloader.h
index 25ebd95288..77c6c80287 100644
--- a/platforms/bootloader.h
+++ b/platforms/bootloader.h
@@ -19,3 +19,4 @@ along with this program.  If not, see <http://www.gnu.org/licenses/>.
 
 /* give code for your bootloader to come up if needed */
 void bootloader_jump(void);
+void mcu_reset(void);
diff --git a/platforms/chibios/_pin_defs.h b/platforms/chibios/_pin_defs.h
new file mode 100644
index 0000000000..0d96e2fc3b
--- /dev/null
+++ b/platforms/chibios/_pin_defs.h
@@ -0,0 +1,289 @@
+/* Copyright 2021 QMK
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+
+#if defined(MCU_KINETIS)
+// TODO: including this avoids "error: expected identifier before '(' token" errors
+//       here just to please KINETIS builds...
+#    include <hal.h>
+#endif
+
+#define A0 PAL_LINE(GPIOA, 0)
+#define A1 PAL_LINE(GPIOA, 1)
+#define A2 PAL_LINE(GPIOA, 2)
+#define A3 PAL_LINE(GPIOA, 3)
+#define A4 PAL_LINE(GPIOA, 4)
+#define A5 PAL_LINE(GPIOA, 5)
+#define A6 PAL_LINE(GPIOA, 6)
+#define A7 PAL_LINE(GPIOA, 7)
+#define A8 PAL_LINE(GPIOA, 8)
+#define A9 PAL_LINE(GPIOA, 9)
+#define A10 PAL_LINE(GPIOA, 10)
+#define A11 PAL_LINE(GPIOA, 11)
+#define A12 PAL_LINE(GPIOA, 12)
+#define A13 PAL_LINE(GPIOA, 13)
+#define A14 PAL_LINE(GPIOA, 14)
+#define A15 PAL_LINE(GPIOA, 15)
+#define A16 PAL_LINE(GPIOA, 16)
+#define A17 PAL_LINE(GPIOA, 17)
+#define A18 PAL_LINE(GPIOA, 18)
+#define A19 PAL_LINE(GPIOA, 19)
+#define A20 PAL_LINE(GPIOA, 20)
+#define A21 PAL_LINE(GPIOA, 21)
+#define A22 PAL_LINE(GPIOA, 22)
+#define A23 PAL_LINE(GPIOA, 23)
+#define A24 PAL_LINE(GPIOA, 24)
+#define A25 PAL_LINE(GPIOA, 25)
+#define A26 PAL_LINE(GPIOA, 26)
+#define A27 PAL_LINE(GPIOA, 27)
+#define A28 PAL_LINE(GPIOA, 28)
+#define A29 PAL_LINE(GPIOA, 29)
+#define A30 PAL_LINE(GPIOA, 30)
+#define A31 PAL_LINE(GPIOA, 31)
+#define A32 PAL_LINE(GPIOA, 32)
+#define B0 PAL_LINE(GPIOB, 0)
+#define B1 PAL_LINE(GPIOB, 1)
+#define B2 PAL_LINE(GPIOB, 2)
+#define B3 PAL_LINE(GPIOB, 3)
+#define B4 PAL_LINE(GPIOB, 4)
+#define B5 PAL_LINE(GPIOB, 5)
+#define B6 PAL_LINE(GPIOB, 6)
+#define B7 PAL_LINE(GPIOB, 7)
+#define B8 PAL_LINE(GPIOB, 8)
+#define B9 PAL_LINE(GPIOB, 9)
+#define B10 PAL_LINE(GPIOB, 10)
+#define B11 PAL_LINE(GPIOB, 11)
+#define B12 PAL_LINE(GPIOB, 12)
+#define B13 PAL_LINE(GPIOB, 13)
+#define B14 PAL_LINE(GPIOB, 14)
+#define B15 PAL_LINE(GPIOB, 15)
+#define B16 PAL_LINE(GPIOB, 16)
+#define B17 PAL_LINE(GPIOB, 17)
+#define B18 PAL_LINE(GPIOB, 18)
+#define B19 PAL_LINE(GPIOB, 19)
+#define B20 PAL_LINE(GPIOB, 20)
+#define B21 PAL_LINE(GPIOB, 21)
+#define B22 PAL_LINE(GPIOB, 22)
+#define B23 PAL_LINE(GPIOB, 23)
+#define B24 PAL_LINE(GPIOB, 24)
+#define B25 PAL_LINE(GPIOB, 25)
+#define B26 PAL_LINE(GPIOB, 26)
+#define B27 PAL_LINE(GPIOB, 27)
+#define B28 PAL_LINE(GPIOB, 28)
+#define B29 PAL_LINE(GPIOB, 29)
+#define B30 PAL_LINE(GPIOB, 30)
+#define B31 PAL_LINE(GPIOB, 31)
+#define B32 PAL_LINE(GPIOB, 32)
+#define C0 PAL_LINE(GPIOC, 0)
+#define C1 PAL_LINE(GPIOC, 1)
+#define C2 PAL_LINE(GPIOC, 2)
+#define C3 PAL_LINE(GPIOC, 3)
+#define C4 PAL_LINE(GPIOC, 4)
+#define C5 PAL_LINE(GPIOC, 5)
+#define C6 PAL_LINE(GPIOC, 6)
+#define C7 PAL_LINE(GPIOC, 7)
+#define C8 PAL_LINE(GPIOC, 8)
+#define C9 PAL_LINE(GPIOC, 9)
+#define C10 PAL_LINE(GPIOC, 10)
+#define C11 PAL_LINE(GPIOC, 11)
+#define C12 PAL_LINE(GPIOC, 12)
+#define C13 PAL_LINE(GPIOC, 13)
+#define C14 PAL_LINE(GPIOC, 14)
+#define C15 PAL_LINE(GPIOC, 15)
+#define C16 PAL_LINE(GPIOC, 16)
+#define C17 PAL_LINE(GPIOC, 17)
+#define C18 PAL_LINE(GPIOC, 18)
+#define C19 PAL_LINE(GPIOC, 19)
+#define C20 PAL_LINE(GPIOC, 20)
+#define C21 PAL_LINE(GPIOC, 21)
+#define C22 PAL_LINE(GPIOC, 22)
+#define C23 PAL_LINE(GPIOC, 23)
+#define C24 PAL_LINE(GPIOC, 24)
+#define C25 PAL_LINE(GPIOC, 25)
+#define C26 PAL_LINE(GPIOC, 26)
+#define C27 PAL_LINE(GPIOC, 27)
+#define C28 PAL_LINE(GPIOC, 28)
+#define C29 PAL_LINE(GPIOC, 29)
+#define C30 PAL_LINE(GPIOC, 30)
+#define C31 PAL_LINE(GPIOC, 31)
+#define C32 PAL_LINE(GPIOC, 32)
+#define D0 PAL_LINE(GPIOD, 0)
+#define D1 PAL_LINE(GPIOD, 1)
+#define D2 PAL_LINE(GPIOD, 2)
+#define D3 PAL_LINE(GPIOD, 3)
+#define D4 PAL_LINE(GPIOD, 4)
+#define D5 PAL_LINE(GPIOD, 5)
+#define D6 PAL_LINE(GPIOD, 6)
+#define D7 PAL_LINE(GPIOD, 7)
+#define D8 PAL_LINE(GPIOD, 8)
+#define D9 PAL_LINE(GPIOD, 9)
+#define D10 PAL_LINE(GPIOD, 10)
+#define D11 PAL_LINE(GPIOD, 11)
+#define D12 PAL_LINE(GPIOD, 12)
+#define D13 PAL_LINE(GPIOD, 13)
+#define D14 PAL_LINE(GPIOD, 14)
+#define D15 PAL_LINE(GPIOD, 15)
+#define D16 PAL_LINE(GPIOD, 16)
+#define D17 PAL_LINE(GPIOD, 17)
+#define D18 PAL_LINE(GPIOD, 18)
+#define D19 PAL_LINE(GPIOD, 19)
+#define D20 PAL_LINE(GPIOD, 20)
+#define D21 PAL_LINE(GPIOD, 21)
+#define D22 PAL_LINE(GPIOD, 22)
+#define D23 PAL_LINE(GPIOD, 23)
+#define D24 PAL_LINE(GPIOD, 24)
+#define D25 PAL_LINE(GPIOD, 25)
+#define D26 PAL_LINE(GPIOD, 26)
+#define D27 PAL_LINE(GPIOD, 27)
+#define D28 PAL_LINE(GPIOD, 28)
+#define D29 PAL_LINE(GPIOD, 29)
+#define D30 PAL_LINE(GPIOD, 30)
+#define D31 PAL_LINE(GPIOD, 31)
+#define D32 PAL_LINE(GPIOD, 32)
+#define E0 PAL_LINE(GPIOE, 0)
+#define E1 PAL_LINE(GPIOE, 1)
+#define E2 PAL_LINE(GPIOE, 2)
+#define E3 PAL_LINE(GPIOE, 3)
+#define E4 PAL_LINE(GPIOE, 4)
+#define E5 PAL_LINE(GPIOE, 5)
+#define E6 PAL_LINE(GPIOE, 6)
+#define E7 PAL_LINE(GPIOE, 7)
+#define E8 PAL_LINE(GPIOE, 8)
+#define E9 PAL_LINE(GPIOE, 9)
+#define E10 PAL_LINE(GPIOE, 10)
+#define E11 PAL_LINE(GPIOE, 11)
+#define E12 PAL_LINE(GPIOE, 12)
+#define E13 PAL_LINE(GPIOE, 13)
+#define E14 PAL_LINE(GPIOE, 14)
+#define E15 PAL_LINE(GPIOE, 15)
+#define E16 PAL_LINE(GPIOE, 16)
+#define E17 PAL_LINE(GPIOE, 17)
+#define E18 PAL_LINE(GPIOE, 18)
+#define E19 PAL_LINE(GPIOE, 19)
+#define E20 PAL_LINE(GPIOE, 20)
+#define E21 PAL_LINE(GPIOE, 21)
+#define E22 PAL_LINE(GPIOE, 22)
+#define E23 PAL_LINE(GPIOE, 23)
+#define E24 PAL_LINE(GPIOE, 24)
+#define E25 PAL_LINE(GPIOE, 25)
+#define E26 PAL_LINE(GPIOE, 26)
+#define E27 PAL_LINE(GPIOE, 27)
+#define E28 PAL_LINE(GPIOE, 28)
+#define E29 PAL_LINE(GPIOE, 29)
+#define E30 PAL_LINE(GPIOE, 30)
+#define E31 PAL_LINE(GPIOE, 31)
+#define E32 PAL_LINE(GPIOE, 32)
+#define F0 PAL_LINE(GPIOF, 0)
+#define F1 PAL_LINE(GPIOF, 1)
+#define F2 PAL_LINE(GPIOF, 2)
+#define F3 PAL_LINE(GPIOF, 3)
+#define F4 PAL_LINE(GPIOF, 4)
+#define F5 PAL_LINE(GPIOF, 5)
+#define F6 PAL_LINE(GPIOF, 6)
+#define F7 PAL_LINE(GPIOF, 7)
+#define F8 PAL_LINE(GPIOF, 8)
+#define F9 PAL_LINE(GPIOF, 9)
+#define F10 PAL_LINE(GPIOF, 10)
+#define F11 PAL_LINE(GPIOF, 11)
+#define F12 PAL_LINE(GPIOF, 12)
+#define F13 PAL_LINE(GPIOF, 13)
+#define F14 PAL_LINE(GPIOF, 14)
+#define F15 PAL_LINE(GPIOF, 15)
+#define G0 PAL_LINE(GPIOG, 0)
+#define G1 PAL_LINE(GPIOG, 1)
+#define G2 PAL_LINE(GPIOG, 2)
+#define G3 PAL_LINE(GPIOG, 3)
+#define G4 PAL_LINE(GPIOG, 4)
+#define G5 PAL_LINE(GPIOG, 5)
+#define G6 PAL_LINE(GPIOG, 6)
+#define G7 PAL_LINE(GPIOG, 7)
+#define G8 PAL_LINE(GPIOG, 8)
+#define G9 PAL_LINE(GPIOG, 9)
+#define G10 PAL_LINE(GPIOG, 10)
+#define G11 PAL_LINE(GPIOG, 11)
+#define G12 PAL_LINE(GPIOG, 12)
+#define G13 PAL_LINE(GPIOG, 13)
+#define G14 PAL_LINE(GPIOG, 14)
+#define G15 PAL_LINE(GPIOG, 15)
+#define H0 PAL_LINE(GPIOH, 0)
+#define H1 PAL_LINE(GPIOH, 1)
+#define H2 PAL_LINE(GPIOH, 2)
+#define H3 PAL_LINE(GPIOH, 3)
+#define H4 PAL_LINE(GPIOH, 4)
+#define H5 PAL_LINE(GPIOH, 5)
+#define H6 PAL_LINE(GPIOH, 6)
+#define H7 PAL_LINE(GPIOH, 7)
+#define H8 PAL_LINE(GPIOH, 8)
+#define H9 PAL_LINE(GPIOH, 9)
+#define H10 PAL_LINE(GPIOH, 10)
+#define H11 PAL_LINE(GPIOH, 11)
+#define H12 PAL_LINE(GPIOH, 12)
+#define H13 PAL_LINE(GPIOH, 13)
+#define H14 PAL_LINE(GPIOH, 14)
+#define H15 PAL_LINE(GPIOH, 15)
+#define I0 PAL_LINE(GPIOI, 0)
+#define I1 PAL_LINE(GPIOI, 1)
+#define I2 PAL_LINE(GPIOI, 2)
+#define I3 PAL_LINE(GPIOI, 3)
+#define I4 PAL_LINE(GPIOI, 4)
+#define I5 PAL_LINE(GPIOI, 5)
+#define I6 PAL_LINE(GPIOI, 6)
+#define I7 PAL_LINE(GPIOI, 7)
+#define I8 PAL_LINE(GPIOI, 8)
+#define I9 PAL_LINE(GPIOI, 9)
+#define I10 PAL_LINE(GPIOI, 10)
+#define I11 PAL_LINE(GPIOI, 11)
+#define I12 PAL_LINE(GPIOI, 12)
+#define I13 PAL_LINE(GPIOI, 13)
+#define I14 PAL_LINE(GPIOI, 14)
+#define I15 PAL_LINE(GPIOI, 15)
+#define J0 PAL_LINE(GPIOJ, 0)
+#define J1 PAL_LINE(GPIOJ, 1)
+#define J2 PAL_LINE(GPIOJ, 2)
+#define J3 PAL_LINE(GPIOJ, 3)
+#define J4 PAL_LINE(GPIOJ, 4)
+#define J5 PAL_LINE(GPIOJ, 5)
+#define J6 PAL_LINE(GPIOJ, 6)
+#define J7 PAL_LINE(GPIOJ, 7)
+#define J8 PAL_LINE(GPIOJ, 8)
+#define J9 PAL_LINE(GPIOJ, 9)
+#define J10 PAL_LINE(GPIOJ, 10)
+#define J11 PAL_LINE(GPIOJ, 11)
+#define J12 PAL_LINE(GPIOJ, 12)
+#define J13 PAL_LINE(GPIOJ, 13)
+#define J14 PAL_LINE(GPIOJ, 14)
+#define J15 PAL_LINE(GPIOJ, 15)
+// Keyboards can `#define KEYBOARD_REQUIRES_GPIOK` if they need to access GPIO-K pins. These conflict with a whole
+// bunch of layout definitions, so it's intentionally left out unless absolutely required -- in that case, the
+// keyboard designer should use a different symbol when defining their layout macros.
+#ifdef KEYBOARD_REQUIRES_GPIOK
+#    define K0 PAL_LINE(GPIOK, 0)
+#    define K1 PAL_LINE(GPIOK, 1)
+#    define K2 PAL_LINE(GPIOK, 2)
+#    define K3 PAL_LINE(GPIOK, 3)
+#    define K4 PAL_LINE(GPIOK, 4)
+#    define K5 PAL_LINE(GPIOK, 5)
+#    define K6 PAL_LINE(GPIOK, 6)
+#    define K7 PAL_LINE(GPIOK, 7)
+#    define K8 PAL_LINE(GPIOK, 8)
+#    define K9 PAL_LINE(GPIOK, 9)
+#    define K10 PAL_LINE(GPIOK, 10)
+#    define K11 PAL_LINE(GPIOK, 11)
+#    define K12 PAL_LINE(GPIOK, 12)
+#    define K13 PAL_LINE(GPIOK, 13)
+#    define K14 PAL_LINE(GPIOK, 14)
+#    define K15 PAL_LINE(GPIOK, 15)
+#endif
diff --git a/platforms/chibios/boards/BLACKPILL_STM32_F401/configs/board.h b/platforms/chibios/boards/BLACKPILL_STM32_F401/configs/board.h
index 30af6b0c86..78dcbac05c 100644
--- a/platforms/chibios/boards/BLACKPILL_STM32_F401/configs/board.h
+++ b/platforms/chibios/boards/BLACKPILL_STM32_F401/configs/board.h
@@ -17,4 +17,61 @@
 
 #include_next "board.h"
 
+// Force B9 as input to align with qmk defaults
+#undef VAL_GPIOB_MODER
+#define VAL_GPIOB_MODER             (PIN_MODE_INPUT(GPIOB_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN2) |           \
+                                     PIN_MODE_ALTERNATE(GPIOB_SWO) |        \
+                                     PIN_MODE_INPUT(GPIOB_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOB_LSM303DLHC_SCL) | \
+                                     PIN_MODE_INPUT(GPIOB_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOB_LSM303DLHC_SDA) | \
+                                     PIN_MODE_ALTERNATE(GPIOB_MP45DT02_CLK_IN) |\
+                                     PIN_MODE_INPUT(GPIOB_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN15))
+
+#undef VAL_GPIOB_PUPDR
+#define VAL_GPIOB_PUPDR             (PIN_PUPDR_PULLUP(GPIOB_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_SWO) |          \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_LSM303DLHC_SCL) |\
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_LSM303DLHC_SDA) |\
+                                     PIN_PUPDR_FLOATING(GPIOB_MP45DT02_CLK_IN) |\
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN15))
+
+#undef VAL_GPIOB_AFRL
+#define VAL_GPIOB_AFRL              (PIN_AFIO_AF(GPIOB_PIN0, 0U) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN1, 0U) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN2, 0U) |          \
+                                     PIN_AFIO_AF(GPIOB_SWO, 0U) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN4, 0U) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN5, 0U) |          \
+                                     PIN_AFIO_AF(GPIOB_LSM303DLHC_SCL, 0) | \
+                                     PIN_AFIO_AF(GPIOB_PIN7, 0U))
+
+#undef VAL_GPIOB_AFRH
+#define VAL_GPIOB_AFRH              (PIN_AFIO_AF(GPIOB_PIN8, 0U) |          \
+                                     PIN_AFIO_AF(GPIOB_LSM303DLHC_SDA, 0) | \
+                                     PIN_AFIO_AF(GPIOB_MP45DT02_CLK_IN, 5U) |\
+                                     PIN_AFIO_AF(GPIOB_PIN11, 0U) |         \
+                                     PIN_AFIO_AF(GPIOB_PIN12, 0U) |         \
+                                     PIN_AFIO_AF(GPIOB_PIN13, 0U) |         \
+                                     PIN_AFIO_AF(GPIOB_PIN14, 0U) |         \
+                                     PIN_AFIO_AF(GPIOB_PIN15, 0U))
+
 #undef STM32_HSE_BYPASS
diff --git a/platforms/chibios/boards/GENERIC_STM32_F303XC/configs/mcuconf.h b/platforms/chibios/boards/GENERIC_STM32_F303XC/configs/mcuconf.h
index c6f5a8ac52..e0af4a276b 100644
--- a/platforms/chibios/boards/GENERIC_STM32_F303XC/configs/mcuconf.h
+++ b/platforms/chibios/boards/GENERIC_STM32_F303XC/configs/mcuconf.h
@@ -1,5 +1,5 @@
 /*
-    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -186,7 +186,6 @@
 /*
  * PWM driver system settings.
  */
-#define STM32_PWM_USE_ADVANCED              FALSE
 #define STM32_PWM_USE_TIM1                  FALSE
 #define STM32_PWM_USE_TIM2                  FALSE
 #define STM32_PWM_USE_TIM3                  FALSE
diff --git a/platforms/chibios/boards/GENERIC_STM32_F401XC/board/board.mk b/platforms/chibios/boards/GENERIC_STM32_F401XC/board/board.mk
new file mode 100644
index 0000000000..fddf7dace4
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_STM32_F401XC/board/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F401C_DISCOVERY/board.c
+
+# Required include directories
+BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32F401C_DISCOVERY
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/platforms/chibios/boards/GENERIC_STM32_F401XC/configs/board.h b/platforms/chibios/boards/GENERIC_STM32_F401XC/configs/board.h
new file mode 100644
index 0000000000..78dcbac05c
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_STM32_F401XC/configs/board.h
@@ -0,0 +1,77 @@
+/* Copyright 2020 Nick Brassel (tzarc)
+ *
+ *  This program is free software: you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation, either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ */
+#pragma once
+
+#include_next "board.h"
+
+// Force B9 as input to align with qmk defaults
+#undef VAL_GPIOB_MODER
+#define VAL_GPIOB_MODER             (PIN_MODE_INPUT(GPIOB_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN2) |           \
+                                     PIN_MODE_ALTERNATE(GPIOB_SWO) |        \
+                                     PIN_MODE_INPUT(GPIOB_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOB_LSM303DLHC_SCL) | \
+                                     PIN_MODE_INPUT(GPIOB_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOB_LSM303DLHC_SDA) | \
+                                     PIN_MODE_ALTERNATE(GPIOB_MP45DT02_CLK_IN) |\
+                                     PIN_MODE_INPUT(GPIOB_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN15))
+
+#undef VAL_GPIOB_PUPDR
+#define VAL_GPIOB_PUPDR             (PIN_PUPDR_PULLUP(GPIOB_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_SWO) |          \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_LSM303DLHC_SCL) |\
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_LSM303DLHC_SDA) |\
+                                     PIN_PUPDR_FLOATING(GPIOB_MP45DT02_CLK_IN) |\
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN15))
+
+#undef VAL_GPIOB_AFRL
+#define VAL_GPIOB_AFRL              (PIN_AFIO_AF(GPIOB_PIN0, 0U) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN1, 0U) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN2, 0U) |          \
+                                     PIN_AFIO_AF(GPIOB_SWO, 0U) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN4, 0U) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN5, 0U) |          \
+                                     PIN_AFIO_AF(GPIOB_LSM303DLHC_SCL, 0) | \
+                                     PIN_AFIO_AF(GPIOB_PIN7, 0U))
+
+#undef VAL_GPIOB_AFRH
+#define VAL_GPIOB_AFRH              (PIN_AFIO_AF(GPIOB_PIN8, 0U) |          \
+                                     PIN_AFIO_AF(GPIOB_LSM303DLHC_SDA, 0) | \
+                                     PIN_AFIO_AF(GPIOB_MP45DT02_CLK_IN, 5U) |\
+                                     PIN_AFIO_AF(GPIOB_PIN11, 0U) |         \
+                                     PIN_AFIO_AF(GPIOB_PIN12, 0U) |         \
+                                     PIN_AFIO_AF(GPIOB_PIN13, 0U) |         \
+                                     PIN_AFIO_AF(GPIOB_PIN14, 0U) |         \
+                                     PIN_AFIO_AF(GPIOB_PIN15, 0U))
+
+#undef STM32_HSE_BYPASS
diff --git a/platforms/chibios/boards/GENERIC_STM32_F401XC/configs/config.h b/platforms/chibios/boards/GENERIC_STM32_F401XC/configs/config.h
new file mode 100644
index 0000000000..e06ca0b725
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_STM32_F401XC/configs/config.h
@@ -0,0 +1,22 @@
+/* Copyright 2020 Nick Brassel (tzarc)
+ *
+ *  This program is free software: you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation, either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ */
+#pragma once
+
+#define BOARD_OTG_NOVBUSSENS 1
+
+#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
+#    define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
+#endif
diff --git a/platforms/chibios/boards/GENERIC_STM32_F401XC/configs/mcuconf.h b/platforms/chibios/boards/GENERIC_STM32_F401XC/configs/mcuconf.h
new file mode 100644
index 0000000000..24cec7137d
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_STM32_F401XC/configs/mcuconf.h
@@ -0,0 +1,244 @@
+/*
+    ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef MCUCONF_H
+#define MCUCONF_H
+
+/*
+ * STM32F4xx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 15...0       Lowest...Highest.
+ *
+ * DMA priorities:
+ * 0...3        Lowest...Highest.
+ */
+
+#define STM32F4xx_MCUCONF
+#define STM32F401_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define STM32_NO_INIT                       FALSE
+#define STM32_PVD_ENABLE                    FALSE
+#define STM32_PLS                           STM32_PLS_LEV0
+#define STM32_BKPRAM_ENABLE                 FALSE
+#define STM32_HSI_ENABLED                   TRUE
+#define STM32_LSI_ENABLED                   TRUE
+#define STM32_HSE_ENABLED                   TRUE
+#define STM32_LSE_ENABLED                   FALSE
+#define STM32_CLOCK48_REQUIRED              TRUE
+#define STM32_SW                            STM32_SW_PLL
+#define STM32_PLLSRC                        STM32_PLLSRC_HSE
+#define STM32_PLLM_VALUE                    4
+#define STM32_PLLN_VALUE                    168
+#define STM32_PLLP_VALUE                    4
+#define STM32_PLLQ_VALUE                    7
+#define STM32_HPRE                          STM32_HPRE_DIV1
+#define STM32_PPRE1                         STM32_PPRE1_DIV2  
+#define STM32_PPRE2                         STM32_PPRE2_DIV1 
+#define STM32_RTCSEL                        STM32_RTCSEL_LSI
+#define STM32_RTCPRE_VALUE                  8
+#define STM32_MCO1SEL                       STM32_MCO1SEL_HSI
+#define STM32_MCO1PRE                       STM32_MCO1PRE_DIV1
+#define STM32_MCO2SEL                       STM32_MCO2SEL_SYSCLK
+#define STM32_MCO2PRE                       STM32_MCO2PRE_DIV5
+#define STM32_I2SSRC                        STM32_I2SSRC_CKIN
+#define STM32_PLLI2SN_VALUE                 192
+#define STM32_PLLI2SR_VALUE                 5
+
+/*
+ * IRQ system settings.
+ */
+#define STM32_IRQ_EXTI0_PRIORITY            6
+#define STM32_IRQ_EXTI1_PRIORITY            6
+#define STM32_IRQ_EXTI2_PRIORITY            6
+#define STM32_IRQ_EXTI3_PRIORITY            6
+#define STM32_IRQ_EXTI4_PRIORITY            6
+#define STM32_IRQ_EXTI5_9_PRIORITY          6
+#define STM32_IRQ_EXTI10_15_PRIORITY        6
+#define STM32_IRQ_EXTI16_PRIORITY           6
+#define STM32_IRQ_EXTI17_PRIORITY           15
+#define STM32_IRQ_EXTI18_PRIORITY           6
+#define STM32_IRQ_EXTI19_PRIORITY           6
+#define STM32_IRQ_EXTI20_PRIORITY           6
+#define STM32_IRQ_EXTI21_PRIORITY           15
+#define STM32_IRQ_EXTI22_PRIORITY           15
+
+#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY    7
+#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY    7
+#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
+#define STM32_IRQ_TIM1_CC_PRIORITY          7
+#define STM32_IRQ_TIM2_PRIORITY             7
+#define STM32_IRQ_TIM3_PRIORITY             7
+#define STM32_IRQ_TIM4_PRIORITY             7
+#define STM32_IRQ_TIM5_PRIORITY             7
+
+#define STM32_IRQ_USART1_PRIORITY           12
+#define STM32_IRQ_USART2_PRIORITY           12
+#define STM32_IRQ_USART6_PRIORITY           12
+
+/*
+ * ADC driver system settings.
+ */
+#define STM32_ADC_ADCPRE                    ADC_CCR_ADCPRE_DIV4
+#define STM32_ADC_USE_ADC1                  FALSE
+#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(2, 4)
+#define STM32_ADC_ADC1_DMA_PRIORITY         2
+#define STM32_ADC_IRQ_PRIORITY              6
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     6
+
+/*
+ * GPT driver system settings.
+ */
+#define STM32_GPT_USE_TIM1                  FALSE
+#define STM32_GPT_USE_TIM2                  FALSE
+#define STM32_GPT_USE_TIM3                  FALSE
+#define STM32_GPT_USE_TIM4                  FALSE
+#define STM32_GPT_USE_TIM5                  FALSE
+#define STM32_GPT_USE_TIM9                  FALSE
+#define STM32_GPT_USE_TIM10                 FALSE
+#define STM32_GPT_USE_TIM11                 FALSE
+
+/*
+ * I2C driver system settings.
+ */
+#define STM32_I2C_USE_I2C1                  FALSE
+#define STM32_I2C_USE_I2C2                  FALSE
+#define STM32_I2C_USE_I2C3                  FALSE
+#define STM32_I2C_BUSY_TIMEOUT              50
+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2C_I2C1_IRQ_PRIORITY         5
+#define STM32_I2C_I2C2_IRQ_PRIORITY         5
+#define STM32_I2C_I2C3_IRQ_PRIORITY         5
+#define STM32_I2C_I2C1_DMA_PRIORITY         3
+#define STM32_I2C_I2C2_DMA_PRIORITY         3
+#define STM32_I2C_I2C3_DMA_PRIORITY         3
+#define STM32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure")
+
+/*
+ * I2S driver system settings.
+ */
+#define STM32_I2S_USE_SPI2                  FALSE
+#define STM32_I2S_USE_SPI3                  FALSE
+#define STM32_I2S_SPI2_IRQ_PRIORITY         10
+#define STM32_I2S_SPI3_IRQ_PRIORITY         10
+#define STM32_I2S_SPI2_DMA_PRIORITY         1
+#define STM32_I2S_SPI3_DMA_PRIORITY         1
+#define STM32_I2S_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2S_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2S_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
+#define STM32_I2S_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2S_DMA_ERROR_HOOK(i2sp)      osalSysHalt("DMA failure")
+
+/*
+ * ICU driver system settings.
+ */
+#define STM32_ICU_USE_TIM1                  FALSE
+#define STM32_ICU_USE_TIM2                  FALSE
+#define STM32_ICU_USE_TIM3                  FALSE
+#define STM32_ICU_USE_TIM4                  FALSE
+#define STM32_ICU_USE_TIM5                  FALSE
+#define STM32_ICU_USE_TIM9                  FALSE
+#define STM32_ICU_USE_TIM10                 FALSE
+#define STM32_ICU_USE_TIM11                 FALSE
+
+/*
+ * PWM driver system settings.
+ */
+#define STM32_PWM_USE_TIM1                  FALSE
+#define STM32_PWM_USE_TIM2                  FALSE
+#define STM32_PWM_USE_TIM3                  FALSE
+#define STM32_PWM_USE_TIM4                  FALSE
+#define STM32_PWM_USE_TIM5                  FALSE
+#define STM32_PWM_USE_TIM9                  FALSE
+#define STM32_PWM_USE_TIM10                 FALSE
+#define STM32_PWM_USE_TIM11                 FALSE
+
+/*
+ * SERIAL driver system settings.
+ */
+#define STM32_SERIAL_USE_USART1             FALSE
+#define STM32_SERIAL_USE_USART2             FALSE
+#define STM32_SERIAL_USE_USART6             FALSE
+
+/*
+ * SPI driver system settings.
+ */
+#define STM32_SPI_USE_SPI1                  FALSE
+#define STM32_SPI_USE_SPI2                  FALSE
+#define STM32_SPI_USE_SPI3                  FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 0)
+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 3)
+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
+#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_SPI_SPI1_DMA_PRIORITY         1
+#define STM32_SPI_SPI2_DMA_PRIORITY         1
+#define STM32_SPI_SPI3_DMA_PRIORITY         1
+#define STM32_SPI_SPI1_IRQ_PRIORITY         10
+#define STM32_SPI_SPI2_IRQ_PRIORITY         10
+#define STM32_SPI_SPI3_IRQ_PRIORITY         10
+#define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure")
+
+/*
+ * ST driver system settings.
+ */
+#define STM32_ST_IRQ_PRIORITY               8
+#define STM32_ST_USE_TIMER                  2
+
+/*
+ * UART driver system settings.
+ */
+#define STM32_UART_USE_USART1               FALSE
+#define STM32_UART_USE_USART2               FALSE
+#define STM32_UART_USE_USART6               FALSE
+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART6_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 2)
+#define STM32_UART_USART6_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART1_DMA_PRIORITY      0
+#define STM32_UART_USART2_DMA_PRIORITY      0
+#define STM32_UART_USART6_DMA_PRIORITY      0
+#define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")
+
+/*
+ * USB driver system settings.
+ */
+#define STM32_USB_USE_OTG1                  TRUE
+#define STM32_USB_OTG1_IRQ_PRIORITY         14
+#define STM32_USB_OTG1_RX_FIFO_SIZE         512
+#define STM32_USB_HOST_WAKEUP_DURATION      2
+
+/*
+ * WDG driver system settings.
+ */
+#define STM32_WDG_USE_IWDG                  FALSE
+
+#endif /* MCUCONF_H */
diff --git a/platforms/chibios/boards/GENERIC_STM32_F405XG/configs/mcuconf.h b/platforms/chibios/boards/GENERIC_STM32_F405XG/configs/mcuconf.h
index 908a580a91..394e750256 100644
--- a/platforms/chibios/boards/GENERIC_STM32_F405XG/configs/mcuconf.h
+++ b/platforms/chibios/boards/GENERIC_STM32_F405XG/configs/mcuconf.h
@@ -1,5 +1,5 @@
 /*
-    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -86,6 +86,28 @@
 #define STM32_IRQ_EXTI21_PRIORITY           15
 #define STM32_IRQ_EXTI22_PRIORITY           15
 
+#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY    7
+#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY    7
+#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
+#define STM32_IRQ_TIM1_CC_PRIORITY          7
+#define STM32_IRQ_TIM2_PRIORITY             7
+#define STM32_IRQ_TIM3_PRIORITY             7
+#define STM32_IRQ_TIM4_PRIORITY             7
+#define STM32_IRQ_TIM5_PRIORITY             7
+#define STM32_IRQ_TIM6_PRIORITY             7
+#define STM32_IRQ_TIM7_PRIORITY             7
+#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY   7
+#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY    7
+#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7
+#define STM32_IRQ_TIM8_CC_PRIORITY          7
+
+#define STM32_IRQ_USART1_PRIORITY           12
+#define STM32_IRQ_USART2_PRIORITY           12
+#define STM32_IRQ_USART3_PRIORITY           12
+#define STM32_IRQ_UART4_PRIORITY            12
+#define STM32_IRQ_UART5_PRIORITY            12
+#define STM32_IRQ_USART6_PRIORITY           12
+
 /*
  * ADC driver system settings.
  */
@@ -137,21 +159,11 @@
 #define STM32_GPT_USE_TIM7                  FALSE
 #define STM32_GPT_USE_TIM8                  FALSE
 #define STM32_GPT_USE_TIM9                  FALSE
+#define STM32_GPT_USE_TIM10                 FALSE
 #define STM32_GPT_USE_TIM11                 FALSE
 #define STM32_GPT_USE_TIM12                 FALSE
+#define STM32_GPT_USE_TIM13                 FALSE
 #define STM32_GPT_USE_TIM14                 FALSE
-#define STM32_GPT_TIM1_IRQ_PRIORITY         7
-#define STM32_GPT_TIM2_IRQ_PRIORITY         7
-#define STM32_GPT_TIM3_IRQ_PRIORITY         7
-#define STM32_GPT_TIM4_IRQ_PRIORITY         7
-#define STM32_GPT_TIM5_IRQ_PRIORITY         7
-#define STM32_GPT_TIM6_IRQ_PRIORITY         7
-#define STM32_GPT_TIM7_IRQ_PRIORITY         7
-#define STM32_GPT_TIM8_IRQ_PRIORITY         7
-#define STM32_GPT_TIM9_IRQ_PRIORITY         7
-#define STM32_GPT_TIM11_IRQ_PRIORITY        7
-#define STM32_GPT_TIM12_IRQ_PRIORITY        7
-#define STM32_GPT_TIM14_IRQ_PRIORITY        7
 
 /*
  * I2C driver system settings.
@@ -199,13 +211,11 @@
 #define STM32_ICU_USE_TIM5                  FALSE
 #define STM32_ICU_USE_TIM8                  FALSE
 #define STM32_ICU_USE_TIM9                  FALSE
-#define STM32_ICU_TIM1_IRQ_PRIORITY         7
-#define STM32_ICU_TIM2_IRQ_PRIORITY         7
-#define STM32_ICU_TIM3_IRQ_PRIORITY         7
-#define STM32_ICU_TIM4_IRQ_PRIORITY         7
-#define STM32_ICU_TIM5_IRQ_PRIORITY         7
-#define STM32_ICU_TIM8_IRQ_PRIORITY         7
-#define STM32_ICU_TIM9_IRQ_PRIORITY         7
+#define STM32_ICU_USE_TIM10                 FALSE
+#define STM32_ICU_USE_TIM11                 FALSE
+#define STM32_ICU_USE_TIM12                 FALSE
+#define STM32_ICU_USE_TIM13                 FALSE
+#define STM32_ICU_USE_TIM14                 FALSE
 
 /*
  * MAC driver system settings.
@@ -221,7 +231,6 @@
 /*
  * PWM driver system settings.
  */
-#define STM32_PWM_USE_ADVANCED              FALSE
 #define STM32_PWM_USE_TIM1                  FALSE
 #define STM32_PWM_USE_TIM2                  FALSE
 #define STM32_PWM_USE_TIM3                  FALSE
@@ -229,13 +238,11 @@
 #define STM32_PWM_USE_TIM5                  FALSE
 #define STM32_PWM_USE_TIM8                  FALSE
 #define STM32_PWM_USE_TIM9                  FALSE
-#define STM32_PWM_TIM1_IRQ_PRIORITY         7
-#define STM32_PWM_TIM2_IRQ_PRIORITY         7
-#define STM32_PWM_TIM3_IRQ_PRIORITY         7
-#define STM32_PWM_TIM4_IRQ_PRIORITY         7
-#define STM32_PWM_TIM5_IRQ_PRIORITY         7
-#define STM32_PWM_TIM8_IRQ_PRIORITY         7
-#define STM32_PWM_TIM9_IRQ_PRIORITY         7
+#define STM32_PWM_USE_TIM10                 FALSE
+#define STM32_PWM_USE_TIM11                 FALSE
+#define STM32_PWM_USE_TIM12                 FALSE
+#define STM32_PWM_USE_TIM13                 FALSE
+#define STM32_PWM_USE_TIM14                 FALSE
 
 /*
  * RTC driver system settings.
@@ -265,12 +272,6 @@
 #define STM32_SERIAL_USE_UART4              FALSE
 #define STM32_SERIAL_USE_UART5              FALSE
 #define STM32_SERIAL_USE_USART6             FALSE
-#define STM32_SERIAL_USART1_PRIORITY        12
-#define STM32_SERIAL_USART2_PRIORITY        12
-#define STM32_SERIAL_USART3_PRIORITY        12
-#define STM32_SERIAL_UART4_PRIORITY         12
-#define STM32_SERIAL_UART5_PRIORITY         12
-#define STM32_SERIAL_USART6_PRIORITY        12
 
 /*
  * SPI driver system settings.
@@ -319,12 +320,6 @@
 #define STM32_UART_UART5_TX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 7)
 #define STM32_UART_USART6_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 2)
 #define STM32_UART_USART6_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)
-#define STM32_UART_USART1_IRQ_PRIORITY      12
-#define STM32_UART_USART2_IRQ_PRIORITY      12
-#define STM32_UART_USART3_IRQ_PRIORITY      12
-#define STM32_UART_UART4_IRQ_PRIORITY       12
-#define STM32_UART_UART5_IRQ_PRIORITY       12
-#define STM32_UART_USART6_IRQ_PRIORITY      12
 #define STM32_UART_USART1_DMA_PRIORITY      0
 #define STM32_UART_USART2_DMA_PRIORITY      0
 #define STM32_UART_USART3_DMA_PRIORITY      0
diff --git a/platforms/chibios/boards/GENERIC_STM32_F407XE/configs/mcuconf.h b/platforms/chibios/boards/GENERIC_STM32_F407XE/configs/mcuconf.h
index 928ee56c71..07399ad2f7 100644
--- a/platforms/chibios/boards/GENERIC_STM32_F407XE/configs/mcuconf.h
+++ b/platforms/chibios/boards/GENERIC_STM32_F407XE/configs/mcuconf.h
@@ -1,5 +1,5 @@
 /*
-    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -86,6 +86,28 @@
 #define STM32_IRQ_EXTI21_PRIORITY           15
 #define STM32_IRQ_EXTI22_PRIORITY           15
 
+#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY    7
+#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY    7
+#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
+#define STM32_IRQ_TIM1_CC_PRIORITY          7
+#define STM32_IRQ_TIM2_PRIORITY             7
+#define STM32_IRQ_TIM3_PRIORITY             7
+#define STM32_IRQ_TIM4_PRIORITY             7
+#define STM32_IRQ_TIM5_PRIORITY             7
+#define STM32_IRQ_TIM6_PRIORITY             7
+#define STM32_IRQ_TIM7_PRIORITY             7
+#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY   7
+#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY    7
+#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7
+#define STM32_IRQ_TIM8_CC_PRIORITY          7
+
+#define STM32_IRQ_USART1_PRIORITY           12
+#define STM32_IRQ_USART2_PRIORITY           12
+#define STM32_IRQ_USART3_PRIORITY           12
+#define STM32_IRQ_UART4_PRIORITY            12
+#define STM32_IRQ_UART5_PRIORITY            12
+#define STM32_IRQ_USART6_PRIORITY           12
+
 /*
  * ADC driver system settings.
  */
@@ -137,21 +159,11 @@
 #define STM32_GPT_USE_TIM7                  FALSE
 #define STM32_GPT_USE_TIM8                  FALSE
 #define STM32_GPT_USE_TIM9                  FALSE
+#define STM32_GPT_USE_TIM10                 FALSE
 #define STM32_GPT_USE_TIM11                 FALSE
 #define STM32_GPT_USE_TIM12                 FALSE
+#define STM32_GPT_USE_TIM13                 FALSE
 #define STM32_GPT_USE_TIM14                 FALSE
-#define STM32_GPT_TIM1_IRQ_PRIORITY         7
-#define STM32_GPT_TIM2_IRQ_PRIORITY         7
-#define STM32_GPT_TIM3_IRQ_PRIORITY         7
-#define STM32_GPT_TIM4_IRQ_PRIORITY         7
-#define STM32_GPT_TIM5_IRQ_PRIORITY         7
-#define STM32_GPT_TIM6_IRQ_PRIORITY         7
-#define STM32_GPT_TIM7_IRQ_PRIORITY         7
-#define STM32_GPT_TIM8_IRQ_PRIORITY         7
-#define STM32_GPT_TIM9_IRQ_PRIORITY         7
-#define STM32_GPT_TIM11_IRQ_PRIORITY        7
-#define STM32_GPT_TIM12_IRQ_PRIORITY        7
-#define STM32_GPT_TIM14_IRQ_PRIORITY        7
 
 /*
  * I2C driver system settings.
@@ -199,13 +211,11 @@
 #define STM32_ICU_USE_TIM5                  FALSE
 #define STM32_ICU_USE_TIM8                  FALSE
 #define STM32_ICU_USE_TIM9                  FALSE
-#define STM32_ICU_TIM1_IRQ_PRIORITY         7
-#define STM32_ICU_TIM2_IRQ_PRIORITY         7
-#define STM32_ICU_TIM3_IRQ_PRIORITY         7
-#define STM32_ICU_TIM4_IRQ_PRIORITY         7
-#define STM32_ICU_TIM5_IRQ_PRIORITY         7
-#define STM32_ICU_TIM8_IRQ_PRIORITY         7
-#define STM32_ICU_TIM9_IRQ_PRIORITY         7
+#define STM32_ICU_USE_TIM10                 FALSE
+#define STM32_ICU_USE_TIM11                 FALSE
+#define STM32_ICU_USE_TIM12                 FALSE
+#define STM32_ICU_USE_TIM13                 FALSE
+#define STM32_ICU_USE_TIM14                 FALSE
 
 /*
  * MAC driver system settings.
@@ -221,7 +231,6 @@
 /*
  * PWM driver system settings.
  */
-#define STM32_PWM_USE_ADVANCED              FALSE
 #define STM32_PWM_USE_TIM1                  FALSE
 #define STM32_PWM_USE_TIM2                  FALSE
 #define STM32_PWM_USE_TIM3                  FALSE
@@ -229,13 +238,11 @@
 #define STM32_PWM_USE_TIM5                  FALSE
 #define STM32_PWM_USE_TIM8                  FALSE
 #define STM32_PWM_USE_TIM9                  FALSE
-#define STM32_PWM_TIM1_IRQ_PRIORITY         7
-#define STM32_PWM_TIM2_IRQ_PRIORITY         7
-#define STM32_PWM_TIM3_IRQ_PRIORITY         7
-#define STM32_PWM_TIM4_IRQ_PRIORITY         7
-#define STM32_PWM_TIM5_IRQ_PRIORITY         7
-#define STM32_PWM_TIM8_IRQ_PRIORITY         7
-#define STM32_PWM_TIM9_IRQ_PRIORITY         7
+#define STM32_PWM_USE_TIM10                 FALSE
+#define STM32_PWM_USE_TIM11                 FALSE
+#define STM32_PWM_USE_TIM12                 FALSE
+#define STM32_PWM_USE_TIM13                 FALSE
+#define STM32_PWM_USE_TIM14                 FALSE
 
 /*
  * RTC driver system settings.
@@ -265,12 +272,6 @@
 #define STM32_SERIAL_USE_UART4              FALSE
 #define STM32_SERIAL_USE_UART5              FALSE
 #define STM32_SERIAL_USE_USART6             FALSE
-#define STM32_SERIAL_USART1_PRIORITY        12
-#define STM32_SERIAL_USART2_PRIORITY        12
-#define STM32_SERIAL_USART3_PRIORITY        12
-#define STM32_SERIAL_UART4_PRIORITY         12
-#define STM32_SERIAL_UART5_PRIORITY         12
-#define STM32_SERIAL_USART6_PRIORITY        12
 
 /*
  * SPI driver system settings.
@@ -319,12 +320,6 @@
 #define STM32_UART_UART5_TX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 7)
 #define STM32_UART_USART6_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 2)
 #define STM32_UART_USART6_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)
-#define STM32_UART_USART1_IRQ_PRIORITY      12
-#define STM32_UART_USART2_IRQ_PRIORITY      12
-#define STM32_UART_USART3_IRQ_PRIORITY      12
-#define STM32_UART_UART4_IRQ_PRIORITY       12
-#define STM32_UART_UART5_IRQ_PRIORITY       12
-#define STM32_UART_USART6_IRQ_PRIORITY      12
 #define STM32_UART_USART1_DMA_PRIORITY      0
 #define STM32_UART_USART2_DMA_PRIORITY      0
 #define STM32_UART_USART3_DMA_PRIORITY      0
diff --git a/platforms/chibios/boards/GENERIC_STM32_F411XE/board/board.mk b/platforms/chibios/boards/GENERIC_STM32_F411XE/board/board.mk
new file mode 100644
index 0000000000..bb00b1a2b0
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_STM32_F411XE/board/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F411RE/board.c
+
+# Required include directories
+BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F411RE
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/platforms/chibios/boards/GENERIC_STM32_F411XE/configs/board.h b/platforms/chibios/boards/GENERIC_STM32_F411XE/configs/board.h
new file mode 100644
index 0000000000..30af6b0c86
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_STM32_F411XE/configs/board.h
@@ -0,0 +1,20 @@
+/* Copyright 2020 Nick Brassel (tzarc)
+ *
+ *  This program is free software: you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation, either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ */
+#pragma once
+
+#include_next "board.h"
+
+#undef STM32_HSE_BYPASS
diff --git a/platforms/chibios/boards/GENERIC_STM32_F411XE/configs/config.h b/platforms/chibios/boards/GENERIC_STM32_F411XE/configs/config.h
new file mode 100644
index 0000000000..e06ca0b725
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_STM32_F411XE/configs/config.h
@@ -0,0 +1,22 @@
+/* Copyright 2020 Nick Brassel (tzarc)
+ *
+ *  This program is free software: you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation, either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ */
+#pragma once
+
+#define BOARD_OTG_NOVBUSSENS 1
+
+#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
+#    define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
+#endif
diff --git a/platforms/chibios/boards/GENERIC_STM32_F411XE/configs/mcuconf.h b/platforms/chibios/boards/GENERIC_STM32_F411XE/configs/mcuconf.h
new file mode 100644
index 0000000000..e1d45ca487
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_STM32_F411XE/configs/mcuconf.h
@@ -0,0 +1,252 @@
+/*
+    ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef MCUCONF_H
+#define MCUCONF_H
+
+/*
+ * STM32F4xx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 15...0       Lowest...Highest.
+ *
+ * DMA priorities:
+ * 0...3        Lowest...Highest.
+ */
+
+#define STM32F4xx_MCUCONF
+#define STM32F411_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define STM32_NO_INIT                       FALSE
+#define STM32_PVD_ENABLE                    FALSE
+#define STM32_PLS                           STM32_PLS_LEV0
+#define STM32_BKPRAM_ENABLE                 FALSE
+#define STM32_HSI_ENABLED                   TRUE
+#define STM32_LSI_ENABLED                   TRUE
+#define STM32_HSE_ENABLED                   TRUE
+#define STM32_LSE_ENABLED                   FALSE
+#define STM32_CLOCK48_REQUIRED              TRUE
+#define STM32_SW                            STM32_SW_PLL
+#define STM32_PLLSRC                        STM32_PLLSRC_HSE
+#define STM32_PLLM_VALUE                    4
+#define STM32_PLLN_VALUE                    96
+#define STM32_PLLP_VALUE                    2
+#define STM32_PLLQ_VALUE                    4
+#define STM32_HPRE                          STM32_HPRE_DIV1
+#define STM32_PPRE1                         STM32_PPRE1_DIV2
+#define STM32_PPRE2                         STM32_PPRE2_DIV1
+#define STM32_RTCSEL                        STM32_RTCSEL_LSI
+#define STM32_RTCPRE_VALUE                  8
+#define STM32_MCO1SEL                       STM32_MCO1SEL_HSI
+#define STM32_MCO1PRE                       STM32_MCO1PRE_DIV1
+#define STM32_MCO2SEL                       STM32_MCO2SEL_SYSCLK
+#define STM32_MCO2PRE                       STM32_MCO2PRE_DIV5
+#define STM32_I2SSRC                        STM32_I2SSRC_CKIN
+#define STM32_PLLI2SN_VALUE                 192
+#define STM32_PLLI2SR_VALUE                 5
+
+/*
+ * IRQ system settings.
+ */
+#define STM32_IRQ_EXTI0_PRIORITY            6
+#define STM32_IRQ_EXTI1_PRIORITY            6
+#define STM32_IRQ_EXTI2_PRIORITY            6
+#define STM32_IRQ_EXTI3_PRIORITY            6
+#define STM32_IRQ_EXTI4_PRIORITY            6
+#define STM32_IRQ_EXTI5_9_PRIORITY          6
+#define STM32_IRQ_EXTI10_15_PRIORITY        6
+#define STM32_IRQ_EXTI16_PRIORITY           6
+#define STM32_IRQ_EXTI17_PRIORITY           15
+#define STM32_IRQ_EXTI18_PRIORITY           6
+#define STM32_IRQ_EXTI19_PRIORITY           6
+#define STM32_IRQ_EXTI20_PRIORITY           6
+#define STM32_IRQ_EXTI21_PRIORITY           15
+#define STM32_IRQ_EXTI22_PRIORITY           15
+
+#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY    7
+#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY    7
+#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
+#define STM32_IRQ_TIM1_CC_PRIORITY          7
+#define STM32_IRQ_TIM2_PRIORITY             7
+#define STM32_IRQ_TIM3_PRIORITY             7
+#define STM32_IRQ_TIM4_PRIORITY             7
+#define STM32_IRQ_TIM5_PRIORITY             7
+
+#define STM32_IRQ_USART1_PRIORITY           12
+#define STM32_IRQ_USART2_PRIORITY           12
+#define STM32_IRQ_USART6_PRIORITY           12
+
+/*
+ * ADC driver system settings.
+ */
+#define STM32_ADC_ADCPRE                    ADC_CCR_ADCPRE_DIV4
+#define STM32_ADC_USE_ADC1                  FALSE
+#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(2, 4)
+#define STM32_ADC_ADC1_DMA_PRIORITY         2
+#define STM32_ADC_IRQ_PRIORITY              6
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     6
+
+/*
+ * GPT driver system settings.
+ */
+#define STM32_GPT_USE_TIM1                  FALSE
+#define STM32_GPT_USE_TIM2                  FALSE
+#define STM32_GPT_USE_TIM3                  FALSE
+#define STM32_GPT_USE_TIM4                  FALSE
+#define STM32_GPT_USE_TIM5                  FALSE
+#define STM32_GPT_USE_TIM9                  FALSE
+#define STM32_GPT_USE_TIM10                 FALSE
+#define STM32_GPT_USE_TIM11                 FALSE
+
+/*
+ * I2C driver system settings.
+ */
+#define STM32_I2C_USE_I2C1                  FALSE
+#define STM32_I2C_USE_I2C2                  FALSE
+#define STM32_I2C_USE_I2C3                  FALSE
+#define STM32_I2C_BUSY_TIMEOUT              50
+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2C_I2C1_IRQ_PRIORITY         5
+#define STM32_I2C_I2C2_IRQ_PRIORITY         5
+#define STM32_I2C_I2C3_IRQ_PRIORITY         5
+#define STM32_I2C_I2C1_DMA_PRIORITY         3
+#define STM32_I2C_I2C2_DMA_PRIORITY         3
+#define STM32_I2C_I2C3_DMA_PRIORITY         3
+#define STM32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure")
+
+/*
+ * I2S driver system settings.
+ */
+#define STM32_I2S_USE_SPI2                  FALSE
+#define STM32_I2S_USE_SPI3                  FALSE
+#define STM32_I2S_SPI2_IRQ_PRIORITY         10
+#define STM32_I2S_SPI3_IRQ_PRIORITY         10
+#define STM32_I2S_SPI2_DMA_PRIORITY         1
+#define STM32_I2S_SPI3_DMA_PRIORITY         1
+#define STM32_I2S_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2S_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2S_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
+#define STM32_I2S_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2S_DMA_ERROR_HOOK(i2sp)      osalSysHalt("DMA failure")
+
+/*
+ * ICU driver system settings.
+ */
+#define STM32_ICU_USE_TIM1                  FALSE
+#define STM32_ICU_USE_TIM2                  FALSE
+#define STM32_ICU_USE_TIM3                  FALSE
+#define STM32_ICU_USE_TIM4                  FALSE
+#define STM32_ICU_USE_TIM5                  FALSE
+#define STM32_ICU_USE_TIM9                  FALSE
+#define STM32_ICU_USE_TIM10                 FALSE
+#define STM32_ICU_USE_TIM11                 FALSE
+
+/*
+ * PWM driver system settings.
+ */
+#define STM32_PWM_USE_TIM1                  FALSE
+#define STM32_PWM_USE_TIM2                  FALSE
+#define STM32_PWM_USE_TIM3                  FALSE
+#define STM32_PWM_USE_TIM4                  FALSE
+#define STM32_PWM_USE_TIM5                  FALSE
+#define STM32_PWM_USE_TIM9                  FALSE
+#define STM32_PWM_USE_TIM10                 FALSE
+#define STM32_PWM_USE_TIM11                 FALSE
+
+/*
+ * RTC driver system settings.
+ */
+#define STM32_RTC_PRESA_VALUE               32
+#define STM32_RTC_PRESS_VALUE               1024
+#define STM32_RTC_CR_INIT                   0
+#define STM32_RTC_TAMPCR_INIT               0
+
+/*
+ * SERIAL driver system settings.
+ */
+#define STM32_SERIAL_USE_USART1             FALSE
+#define STM32_SERIAL_USE_USART2             FALSE
+#define STM32_SERIAL_USE_USART6             FALSE
+
+/*
+ * SPI driver system settings.
+ */
+#define STM32_SPI_USE_SPI1                  FALSE
+#define STM32_SPI_USE_SPI2                  FALSE
+#define STM32_SPI_USE_SPI3                  FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 0)
+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 3)
+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
+#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_SPI_SPI1_DMA_PRIORITY         1
+#define STM32_SPI_SPI2_DMA_PRIORITY         1
+#define STM32_SPI_SPI3_DMA_PRIORITY         1
+#define STM32_SPI_SPI1_IRQ_PRIORITY         10
+#define STM32_SPI_SPI2_IRQ_PRIORITY         10
+#define STM32_SPI_SPI3_IRQ_PRIORITY         10
+#define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure")
+
+/*
+ * ST driver system settings.
+ */
+#define STM32_ST_IRQ_PRIORITY               8
+#define STM32_ST_USE_TIMER                  2
+
+/*
+ * UART driver system settings.
+ */
+#define STM32_UART_USE_USART1               FALSE
+#define STM32_UART_USE_USART2               FALSE
+#define STM32_UART_USE_USART6               FALSE
+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART6_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 2)
+#define STM32_UART_USART6_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART1_DMA_PRIORITY      0
+#define STM32_UART_USART2_DMA_PRIORITY      0
+#define STM32_UART_USART6_DMA_PRIORITY      0
+#define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")
+
+/*
+ * USB driver system settings.
+ */
+#define STM32_USB_USE_OTG1                  TRUE
+#define STM32_USB_OTG1_IRQ_PRIORITY         14
+#define STM32_USB_OTG1_RX_FIFO_SIZE         512
+#define STM32_USB_HOST_WAKEUP_DURATION      2
+
+/*
+ * WDG driver system settings.
+ */
+#define STM32_WDG_USE_IWDG                  FALSE
+
+#endif /* MCUCONF_H */
diff --git a/platforms/chibios/boards/GENERIC_STM32_G431XB/configs/mcuconf.h b/platforms/chibios/boards/GENERIC_STM32_G431XB/configs/mcuconf.h
index d115028300..fd00280115 100644
--- a/platforms/chibios/boards/GENERIC_STM32_G431XB/configs/mcuconf.h
+++ b/platforms/chibios/boards/GENERIC_STM32_G431XB/configs/mcuconf.h
@@ -1,5 +1,5 @@
 /*
-    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -39,6 +39,7 @@
  * HAL driver system settings.
  */
 #define STM32_NO_INIT                       FALSE
+#define STM32_CLOCK_DYNAMIC                 FALSE
 #define STM32_VOS                           STM32_VOS_RANGE1
 #define STM32_PWR_BOOST                     TRUE
 #define STM32_PWR_CR2                       (PWR_CR2_PLS_LEV0)
@@ -227,7 +228,6 @@
 /*
  * PWM driver system settings.
  */
-#define STM32_PWM_USE_ADVANCED              FALSE
 #define STM32_PWM_USE_TIM1                  FALSE
 #define STM32_PWM_USE_TIM2                  FALSE
 #define STM32_PWM_USE_TIM3                  FALSE
@@ -240,6 +240,13 @@
 /*
  * RTC driver system settings.
  */
+#define STM32_RTC_PRESA_VALUE               32
+#define STM32_RTC_PRESS_VALUE               1024
+#define STM32_RTC_CR_INIT                   0
+#define STM32_TAMP_CR1_INIT                 0
+#define STM32_TAMP_CR2_INIT                 0
+#define STM32_TAMP_FLTCR_INIT               0
+#define STM32_TAMP_IER_INIT                 0
 
 /*
  * SDC driver system settings.
@@ -255,6 +262,15 @@
 #define STM32_SERIAL_USE_LPUART1            FALSE
 
 /*
+ * SIO driver system settings.
+ */
+#define STM32_SIO_USE_USART1                FALSE
+#define STM32_SIO_USE_USART2                FALSE
+#define STM32_SIO_USE_USART3                FALSE
+#define STM32_SIO_USE_UART4                 FALSE
+#define STM32_SIO_USE_LPUART1               FALSE
+
+/*
  * SPI driver system settings.
  */
 #define STM32_SPI_USE_SPI1                  FALSE
diff --git a/platforms/chibios/boards/GENERIC_STM32_G474XE/configs/mcuconf.h b/platforms/chibios/boards/GENERIC_STM32_G474XE/configs/mcuconf.h
index 5710e2cb45..d6385da624 100644
--- a/platforms/chibios/boards/GENERIC_STM32_G474XE/configs/mcuconf.h
+++ b/platforms/chibios/boards/GENERIC_STM32_G474XE/configs/mcuconf.h
@@ -1,5 +1,5 @@
 /*
-    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -41,6 +41,7 @@
  * HAL driver system settings.
  */
 #define STM32_NO_INIT                       FALSE
+#define STM32_CLOCK_DYNAMIC                 FALSE
 #define STM32_VOS                           STM32_VOS_RANGE1
 #define STM32_PWR_BOOST                     TRUE
 #define STM32_PWR_CR2                       (PWR_CR2_PLS_LEV0)
@@ -274,7 +275,6 @@
 /*
  * PWM driver system settings.
  */
-#define STM32_PWM_USE_ADVANCED              FALSE
 #define STM32_PWM_USE_TIM1                  FALSE
 #define STM32_PWM_USE_TIM2                  FALSE
 #define STM32_PWM_USE_TIM3                  FALSE
@@ -289,6 +289,13 @@
 /*
  * RTC driver system settings.
  */
+#define STM32_RTC_PRESA_VALUE               32
+#define STM32_RTC_PRESS_VALUE               1024
+#define STM32_RTC_CR_INIT                   0
+#define STM32_TAMP_CR1_INIT                 0
+#define STM32_TAMP_CR2_INIT                 0
+#define STM32_TAMP_FLTCR_INIT               0
+#define STM32_TAMP_IER_INIT                 0
 
 /*
  * SDC driver system settings.
@@ -305,6 +312,16 @@
 #define STM32_SERIAL_USE_LPUART1            FALSE
 
 /*
+ * SIO driver system settings.
+ */
+#define STM32_SIO_USE_USART1                FALSE
+#define STM32_SIO_USE_USART2                FALSE
+#define STM32_SIO_USE_USART3                FALSE
+#define STM32_SIO_USE_UART4                 FALSE
+#define STM32_SIO_USE_UART5                 FALSE
+#define STM32_SIO_USE_LPUART1               FALSE
+
+/*
  * SPI driver system settings.
  */
 #define STM32_SPI_USE_SPI1                  FALSE
@@ -383,5 +400,6 @@
  */
 #define STM32_WSPI_USE_QUADSPI1             FALSE
 #define STM32_WSPI_QUADSPI1_DMA_STREAM      STM32_DMA_STREAM_ID(2, 7)
+#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
 
 #endif /* MCUCONF_H */
diff --git a/platforms/chibios/boards/GENERIC_STM32_L412XB/configs/board.h b/platforms/chibios/boards/GENERIC_STM32_L412XB/configs/board.h
index 2e37d95fe3..de5f85acdd 100644
--- a/platforms/chibios/boards/GENERIC_STM32_L412XB/configs/board.h
+++ b/platforms/chibios/boards/GENERIC_STM32_L412XB/configs/board.h
@@ -18,7 +18,4 @@
 #include_next "board.h"
 
 #undef STM32L432xx
-
-// Pretend that we're an L443xx as the ChibiOS definitions for L4x2/L4x3 mistakenly don't enable GPIOH, I2C2, or SPI2.
-// Until ChibiOS upstream is fixed, this should be kept at L443, as nothing in QMK currently utilises the crypto peripheral on the L443.
-#define STM32L443xx
+#define STM32L422xx
diff --git a/platforms/chibios/boards/GENERIC_STM32_L412XB/configs/config.h b/platforms/chibios/boards/GENERIC_STM32_L412XB/configs/config.h
index fc9055ccfb..d67de4cfe2 100644
--- a/platforms/chibios/boards/GENERIC_STM32_L412XB/configs/config.h
+++ b/platforms/chibios/boards/GENERIC_STM32_L412XB/configs/config.h
@@ -18,8 +18,6 @@
 /* It is chip dependent, the correct number can be looked up by checking against ST's application note AN2606.
  */
 
-#define PAL_STM32_OSPEED_HIGHEST PAL_STM32_OSPEED_HIGH
-
 #ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
 #    define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
 #endif
diff --git a/platforms/chibios/boards/GENERIC_STM32_L412XB/configs/mcuconf.h b/platforms/chibios/boards/GENERIC_STM32_L412XB/configs/mcuconf.h
index 8ad5a8da21..47f1598b74 100644
--- a/platforms/chibios/boards/GENERIC_STM32_L412XB/configs/mcuconf.h
+++ b/platforms/chibios/boards/GENERIC_STM32_L412XB/configs/mcuconf.h
@@ -1,5 +1,5 @@
 /*
-    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -32,12 +32,7 @@
 #define MCUCONF_H
 
 #define STM32L4xx_MCUCONF
-#define STM32L412_MCUCONF
 #define STM32L422_MCUCONF
-#define STM32L432_MCUCONF
-#define STM32L433_MCUCONF
-#define STM32L442_MCUCONF
-#define STM32L443_MCUCONF
 
 /*
  * HAL driver system settings.
@@ -52,16 +47,13 @@
 #define STM32_HSE_ENABLED                   FALSE
 #define STM32_LSE_ENABLED                   FALSE
 #define STM32_MSIPLL_ENABLED                FALSE
-#define STM32_ADC_CLOCK_ENABLED             TRUE
-#define STM32_USB_CLOCK_ENABLED             TRUE
-#define STM32_SAI1_CLOCK_ENABLED            TRUE
-#define STM32_SAI2_CLOCK_ENABLED            TRUE
 #define STM32_MSIRANGE                      STM32_MSIRANGE_4M
 #define STM32_MSISRANGE                     STM32_MSISRANGE_4M
 #define STM32_SW                            STM32_SW_PLL
 #define STM32_PLLSRC                        STM32_PLLSRC_HSI16
 #define STM32_PLLM_VALUE                    4
 #define STM32_PLLN_VALUE                    80
+#define STM32_PLLPDIV_VALUE                 0
 #define STM32_PLLP_VALUE                    7
 #define STM32_PLLQ_VALUE                    4
 #define STM32_PLLR_VALUE                    4
@@ -73,29 +65,22 @@
 #define STM32_MCOPRE                        STM32_MCOPRE_DIV1
 #define STM32_LSCOSEL                       STM32_LSCOSEL_NOCLOCK
 #define STM32_PLLSAI1N_VALUE                72
+#define STM32_PLLSAI1PDIV_VALUE             6
 #define STM32_PLLSAI1P_VALUE                7
 #define STM32_PLLSAI1Q_VALUE                6
 #define STM32_PLLSAI1R_VALUE                6
-#define STM32_PLLSAI2N_VALUE                72
-#define STM32_PLLSAI2P_VALUE                7
-#define STM32_PLLSAI2R_VALUE                6
 
 /*
  * Peripherals clock sources.
  */
 #define STM32_USART1SEL                     STM32_USART1SEL_SYSCLK
 #define STM32_USART2SEL                     STM32_USART2SEL_SYSCLK
-#define STM32_USART3SEL                     STM32_USART3SEL_SYSCLK
-#define STM32_UART4SEL                      STM32_UART4SEL_SYSCLK
-#define STM32_UART5SEL                      STM32_UART5SEL_SYSCLK
 #define STM32_LPUART1SEL                    STM32_LPUART1SEL_SYSCLK
 #define STM32_I2C1SEL                       STM32_I2C1SEL_SYSCLK
-#define STM32_I2C2SEL                       STM32_I2C2SEL_SYSCLK
 #define STM32_I2C3SEL                       STM32_I2C3SEL_SYSCLK
 #define STM32_LPTIM1SEL                     STM32_LPTIM1SEL_PCLK1
 #define STM32_LPTIM2SEL                     STM32_LPTIM2SEL_PCLK1
 #define STM32_SAI1SEL                       STM32_SAI1SEL_OFF
-#define STM32_SAI2SEL                       STM32_SAI2SEL_OFF
 #define STM32_CLK48SEL                      STM32_CLK48SEL_HSI48
 #define STM32_ADCSEL                        STM32_ADCSEL_SYSCLK
 #define STM32_SWPMI1SEL                     STM32_SWPMI1SEL_PCLK1
@@ -127,7 +112,6 @@
 
 #define STM32_IRQ_USART1_PRIORITY           12
 #define STM32_IRQ_USART2_PRIORITY           12
-#define STM32_IRQ_USART3_PRIORITY           12
 #define STM32_IRQ_LPUART1_PRIORITY          12
 
 /*
@@ -137,29 +121,15 @@
 #define STM32_ADC_USE_ADC1                  FALSE
 #define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(1, 1)
 #define STM32_ADC_ADC1_DMA_PRIORITY         2
+#define STM32_ADC_USE_ADC2                  FALSE
+#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(1, 2)
+#define STM32_ADC_ADC2_DMA_PRIORITY         2
 #define STM32_ADC_ADC12_IRQ_PRIORITY        5
 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     5
 #define STM32_ADC_ADC123_CLOCK_MODE         ADC_CCR_CKMODE_AHB_DIV1
 #define STM32_ADC_ADC123_PRESC              ADC_CCR_PRESC_DIV2
 
-/*
- * CAN driver system settings.
- */
-#define STM32_CAN_USE_CAN1                  FALSE
-#define STM32_CAN_CAN1_IRQ_PRIORITY         11
-
-/*
- * DAC driver system settings.
- */
-#define STM32_DAC_DUAL_MODE                 FALSE
-#define STM32_DAC_USE_DAC1_CH1              FALSE
-#define STM32_DAC_USE_DAC1_CH2              FALSE
-#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY     10
-#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY     10
-#define STM32_DAC_DAC1_CH1_DMA_PRIORITY     2
-#define STM32_DAC_DAC1_CH2_DMA_PRIORITY     2
-#define STM32_DAC_DAC1_CH1_DMA_STREAM       STM32_DMA_STREAM_ID(2, 4)
-#define STM32_DAC_DAC1_CH2_DMA_STREAM       STM32_DMA_STREAM_ID(1, 4)
 
 /*
  * GPT driver system settings.
@@ -198,7 +168,6 @@
 /*
  * PWM driver system settings.
  */
-#define STM32_PWM_USE_ADVANCED              FALSE
 #define STM32_PWM_USE_TIM1                  FALSE
 #define STM32_PWM_USE_TIM2                  FALSE
 #define STM32_PWM_USE_TIM15                 FALSE
@@ -218,23 +187,22 @@
 #define STM32_SERIAL_USE_USART1             FALSE
 #define STM32_SERIAL_USE_USART2             FALSE
 #define STM32_SERIAL_USE_LPUART1            FALSE
-#define STM32_SERIAL_USART1_PRIORITY        12
-#define STM32_SERIAL_USART2_PRIORITY        12
-#define STM32_SERIAL_LPUART1_PRIORITY       12
+
+/*
+ * SIO driver system settings.
+ */
+#define STM32_SIO_USE_USART1                FALSE
+#define STM32_SIO_USE_USART2                FALSE
+#define STM32_SIO_USE_LPUART1               FALSE
 
 /*
  * SPI driver system settings.
  */
 #define STM32_SPI_USE_SPI1                  FALSE
-#define STM32_SPI_USE_SPI3                  FALSE
 #define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 3)
 #define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 4)
-#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 1)
-#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 2)
 #define STM32_SPI_SPI1_DMA_PRIORITY         1
-#define STM32_SPI_SPI3_DMA_PRIORITY         1
 #define STM32_SPI_SPI1_IRQ_PRIORITY         10
-#define STM32_SPI_SPI3_IRQ_PRIORITY         10
 #define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure")
 
 /*
diff --git a/platforms/chibios/boards/GENERIC_STM32_L432XC/configs/config.h b/platforms/chibios/boards/GENERIC_STM32_L432XC/configs/config.h
index b1838b30a8..839d031ca4 100644
--- a/platforms/chibios/boards/GENERIC_STM32_L432XC/configs/config.h
+++ b/platforms/chibios/boards/GENERIC_STM32_L432XC/configs/config.h
@@ -2,9 +2,6 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 #pragma once
 
-// Fixup equivalent usages within QMK as the base board definitions only go up to high
-#define PAL_STM32_OSPEED_HIGHEST PAL_STM32_OSPEED_HIGH
-
 #ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
 #    define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
 #endif
diff --git a/platforms/chibios/boards/GENERIC_STM32_L432XC/configs/mcuconf.h b/platforms/chibios/boards/GENERIC_STM32_L432XC/configs/mcuconf.h
index 707134d49e..be64b04812 100644
--- a/platforms/chibios/boards/GENERIC_STM32_L432XC/configs/mcuconf.h
+++ b/platforms/chibios/boards/GENERIC_STM32_L432XC/configs/mcuconf.h
@@ -1,5 +1,5 @@
 /*
-    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -33,7 +33,6 @@
 
 #define STM32L4xx_MCUCONF
 #define STM32L432_MCUCONF
-#define STM32L433_MCUCONF
 
 /*
  * HAL driver system settings.
@@ -183,7 +182,6 @@
 /*
  * PWM driver system settings.
  */
-#define STM32_PWM_USE_ADVANCED              FALSE
 #define STM32_PWM_USE_TIM1                  FALSE
 #define STM32_PWM_USE_TIM2                  FALSE
 #define STM32_PWM_USE_TIM15                 FALSE
@@ -203,9 +201,13 @@
 #define STM32_SERIAL_USE_USART1             FALSE
 #define STM32_SERIAL_USE_USART2             FALSE
 #define STM32_SERIAL_USE_LPUART1            FALSE
-#define STM32_SERIAL_USART1_PRIORITY        12
-#define STM32_SERIAL_USART2_PRIORITY        12
-#define STM32_SERIAL_LPUART1_PRIORITY       12
+
+/*
+ * SIO driver system settings.
+ */
+#define STM32_SIO_USE_USART1                FALSE
+#define STM32_SIO_USE_USART2                FALSE
+#define STM32_SIO_USE_LPUART1               FALSE
 
 /*
  * SPI driver system settings.
diff --git a/platforms/chibios/boards/GENERIC_STM32_L433XC/configs/config.h b/platforms/chibios/boards/GENERIC_STM32_L433XC/configs/config.h
index fc9055ccfb..d67de4cfe2 100644
--- a/platforms/chibios/boards/GENERIC_STM32_L433XC/configs/config.h
+++ b/platforms/chibios/boards/GENERIC_STM32_L433XC/configs/config.h
@@ -18,8 +18,6 @@
 /* It is chip dependent, the correct number can be looked up by checking against ST's application note AN2606.
  */
 
-#define PAL_STM32_OSPEED_HIGHEST PAL_STM32_OSPEED_HIGH
-
 #ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
 #    define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
 #endif
diff --git a/platforms/chibios/boards/GENERIC_WB32_F3G71XX/board/board.h b/platforms/chibios/boards/GENERIC_WB32_F3G71XX/board/board.h
index 51dc84db94..bba1163698 100644
--- a/platforms/chibios/boards/GENERIC_WB32_F3G71XX/board/board.h
+++ b/platforms/chibios/boards/GENERIC_WB32_F3G71XX/board/board.h
@@ -34,7 +34,10 @@
 /*
  * Board identifier.
  */
-#define WB32F3G71x9
+#if !(defined(WB32F3G71x9) || defined(WB32F3G71xB) || defined(WB32F3G71xC))
+  #define WB32F3G71x9
+#endif
+
 #if !defined(WB32F3G71xx)
   #define WB32F3G71xx
 #endif
diff --git a/platforms/chibios/boards/GENERIC_WB32_FQ95XX/board/board.c b/platforms/chibios/boards/GENERIC_WB32_FQ95XX/board/board.c
new file mode 100644
index 0000000000..22b4ff73b5
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_WB32_FQ95XX/board/board.c
@@ -0,0 +1,82 @@
+/*
+    Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+static void wb32_gpio_init(void) {
+
+#if WB32_HAS_GPIOA
+  rccEnableAPB1(RCC_APB1ENR_GPIOAEN);
+#endif
+
+#if WB32_HAS_GPIOB
+  rccEnableAPB1(RCC_APB1ENR_GPIOBEN);
+#endif
+
+#if WB32_HAS_GPIOC
+  rccEnableAPB1(RCC_APB1ENR_GPIOCEN);
+#endif
+
+#if WB32_HAS_GPIOD
+  rccEnableAPB1(RCC_APB1ENR_GPIODEN);
+#endif
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+  wb32_clock_init();
+  wb32_gpio_init();
+}
+/**
+ * @brief   Board-specific initialization code.
+ * @note    You can add your board-specific code here.
+ */
+void boardInit(void) {
+
+}
diff --git a/platforms/chibios/boards/GENERIC_WB32_FQ95XX/board/board.h b/platforms/chibios/boards/GENERIC_WB32_FQ95XX/board/board.h
new file mode 100644
index 0000000000..fb48b75a25
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_WB32_FQ95XX/board/board.h
@@ -0,0 +1,59 @@
+#pragma once
+/*
+    Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
+#ifndef BOARD_H
+#define BOARD_H
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/*
+ * Setup board.
+ */
+
+/*
+ * Board identifier.
+ */
+#if !(defined(WB32FQ95x9) || defined(WB32FQ95xB) || defined(WB32FQ95xC))
+  #define WB32FQ95xB
+#endif
+
+#if !defined(WB32FQ95xx)
+  #define WB32FQ95xx
+#endif
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* BOARD_H */
diff --git a/platforms/chibios/boards/GENERIC_WB32_FQ95XX/board/board.mk b/platforms/chibios/boards/GENERIC_WB32_FQ95XX/board/board.mk
new file mode 100644
index 0000000000..842e335905
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_WB32_FQ95XX/board/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = $(BOARD_PATH)/board/board.c
+
+# Required include directories
+BOARDINC = $(BOARD_PATH)/board
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/platforms/chibios/boards/GENERIC_WB32_FQ95XX/configs/chconf.h b/platforms/chibios/boards/GENERIC_WB32_FQ95XX/configs/chconf.h
new file mode 100644
index 0000000000..e4afddb6a5
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_WB32_FQ95XX/configs/chconf.h
@@ -0,0 +1,26 @@
+/* Copyright 2020 QMK
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * This file was auto-generated by:
+ *    `qmk chibios-confmigrate -i platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/chconf.h -r platforms/chibios/boards/common/configs/chconf.h`
+ */
+
+#pragma once
+
+#define CH_CFG_ST_TIMEDELTA 0
+
+#include_next <chconf.h>
\ No newline at end of file
diff --git a/platforms/chibios/boards/GENERIC_WB32_FQ95XX/configs/config.h b/platforms/chibios/boards/GENERIC_WB32_FQ95XX/configs/config.h
new file mode 100644
index 0000000000..e02e526113
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_WB32_FQ95XX/configs/config.h
@@ -0,0 +1,20 @@
+/*  Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
+ *
+ *  This program is free software: you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation, either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ */
+#pragma once
+
+#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
+#    define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
+#endif
diff --git a/platforms/chibios/boards/GENERIC_WB32_FQ95XX/configs/mcuconf.h b/platforms/chibios/boards/GENERIC_WB32_FQ95XX/configs/mcuconf.h
new file mode 100644
index 0000000000..0867f5a876
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_WB32_FQ95XX/configs/mcuconf.h
@@ -0,0 +1,168 @@
+/*
+    Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef MCUCONF_H
+#define MCUCONF_H
+
+#define WB32FQ95xx_MCUCONF  TRUE
+
+/*
+ * WB32FQ95 drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 15...0       Lowest...Highest.
+ *
+ */
+
+/**
+ * @name    Internal clock sources
+ * @{
+ */
+#define WB32_HSECLK                        12000000
+#define WB32_LSECLK                        32768
+
+/*
+ * HAL driver system settings.
+ */
+#define WB32_NO_INIT                       FALSE
+#define WB32_MHSI_ENABLED                  TRUE
+#define WB32_FHSI_ENABLED                  FALSE
+#define WB32_LSI_ENABLED                   FALSE
+#define WB32_HSE_ENABLED                   TRUE
+#define WB32_LSE_ENABLED                   FALSE
+#define WB32_PLL_ENABLED                   TRUE
+#define WB32_MAINCLKSRC                    WB32_MAINCLKSRC_PLL
+#define WB32_PLLSRC                        WB32_PLLSRC_HSE
+#define WB32_PLLDIV_VALUE                  2
+#define WB32_PLLMUL_VALUE                  12     //The allowed range is 12,16,20,24.
+#define WB32_HPRE                          1
+#define WB32_PPRE1                         1
+#define WB32_PPRE2                         1
+#define WB32_USBPRE                        WB32_USBPRE_DIV1P5
+
+/*
+ * EXTI driver system settings.
+ */
+#define WB32_IRQ_EXTI0_PRIORITY            6
+#define WB32_IRQ_EXTI1_PRIORITY            6
+#define WB32_IRQ_EXTI2_PRIORITY            6
+#define WB32_IRQ_EXTI3_PRIORITY            6
+#define WB32_IRQ_EXTI4_PRIORITY            6
+#define WB32_IRQ_EXTI5_9_PRIORITY          6
+#define WB32_IRQ_EXTI10_15_PRIORITY        6
+#define WB32_IRQ_EXTI16_PRIORITY           6
+#define WB32_IRQ_EXTI17_PRIORITY           6
+#define WB32_IRQ_EXTI18_PRIORITY           6
+#define WB32_IRQ_EXTI19_PRIORITY           6
+
+/*
+ * GPT driver system settings.
+ */
+#define WB32_TIM_MAX_CHANNELS              4
+#define WB32_GPT_USE_TIM1                  FALSE
+#define WB32_GPT_USE_TIM2                  FALSE
+#define WB32_GPT_USE_TIM3                  FALSE
+#define WB32_GPT_USE_TIM4                  FALSE
+#define WB32_GPT_TIM1_IRQ_PRIORITY         7
+#define WB32_GPT_TIM2_IRQ_PRIORITY         7
+#define WB32_GPT_TIM3_IRQ_PRIORITY         7
+#define WB32_GPT_TIM4_IRQ_PRIORITY         7
+
+/*
+ * ICU driver system settings.
+ */
+#define WB32_ICU_USE_TIM1                  FALSE
+#define WB32_ICU_USE_TIM2                  FALSE
+#define WB32_ICU_USE_TIM3                  FALSE
+#define WB32_ICU_USE_TIM4                  FALSE
+#define WB32_ICU_TIM1_IRQ_PRIORITY         7
+#define WB32_ICU_TIM2_IRQ_PRIORITY         7
+#define WB32_ICU_TIM3_IRQ_PRIORITY         7
+#define WB32_ICU_TIM4_IRQ_PRIORITY         7
+
+/*
+ * PWM driver system settings.
+ */
+#define WB32_PWM_USE_ADVANCED              FALSE
+#define WB32_PWM_USE_TIM1                  FALSE
+#define WB32_PWM_USE_TIM2                  FALSE
+#define WB32_PWM_USE_TIM3                  FALSE
+#define WB32_PWM_USE_TIM4                  FALSE
+#define WB32_PWM_TIM1_IRQ_PRIORITY         7
+#define WB32_PWM_TIM2_IRQ_PRIORITY         7
+#define WB32_PWM_TIM3_IRQ_PRIORITY         7
+#define WB32_PWM_TIM4_IRQ_PRIORITY         7
+
+/*
+ * I2C driver system settings.
+ */
+#define WB32_I2C_USE_I2C1                  FALSE
+#define WB32_I2C_USE_I2C2                  FALSE
+#define WB32_I2C_BUSY_TIMEOUT              50
+#define WB32_I2C_I2C1_IRQ_PRIORITY         5
+#define WB32_I2C_I2C2_IRQ_PRIORITY         5
+
+/*
+ * SERIAL driver system settings.
+ */
+#define WB32_SERIAL_USE_UART1             FALSE
+#define WB32_SERIAL_USE_UART2             FALSE
+#define WB32_SERIAL_USE_UART3             FALSE
+#define WB32_SERIAL_USART1_PRIORITY        12
+#define WB32_SERIAL_USART2_PRIORITY        12
+#define WB32_SERIAL_USART3_PRIORITY        12
+
+/*
+ * SPI driver system settings.
+ */
+#define WB32_SPI_USE_QSPI                   FALSE
+#define WB32_SPI_USE_SPIM2                  FALSE
+#define WB32_SPI_USE_SPIS1                  FALSE
+#define WB32_SPI_USE_SPIS2                  FALSE
+#define WB32_SPI_QSPI_IRQ_PRIORITY          10
+#define WB32_SPI_SPIM2_IRQ_PRIORITY         10
+#define WB32_SPI_SPIS1_IRQ_PRIORITY         10
+#define WB32_SPI_SPIS2_IRQ_PRIORITY         10
+
+/*
+ * ST driver system settings.
+ */
+#define WB32_ST_IRQ_PRIORITY                8
+#define WB32_ST_USE_TIMER                   2
+
+/*
+ * UART driver system settings.
+ */
+#define WB32_UART_USE_UART1                 FALSE
+#define WB32_UART_USE_UART2                 FALSE
+#define WB32_UART_USE_UART3                 FALSE
+#define WB32_UART_UART1_IRQ_PRIORITY        12
+#define WB32_UART_UART2_IRQ_PRIORITY        12
+#define WB32_UART_UART3_IRQ_PRIORITY        12
+
+/*
+ * USB driver system settings.
+ */
+#define WB32_USB_USE_USB1                   TRUE
+#define WB32_USB_USB1_IRQ_PRIORITY          13
+#define WB32_USB_HOST_WAKEUP_DURATION       10
+
+
+#endif /* MCUCONF_H */
diff --git a/platforms/chibios/boards/QMK_PROTON_C/configs/chconf.h b/platforms/chibios/boards/QMK_PROTON_C/configs/chconf.h
index f812332960..cc10304a3f 100644
--- a/platforms/chibios/boards/QMK_PROTON_C/configs/chconf.h
+++ b/platforms/chibios/boards/QMK_PROTON_C/configs/chconf.h
@@ -1,5 +1,5 @@
 /*
-    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -29,7 +29,27 @@
 #define CHCONF_H
 
 #define _CHIBIOS_RT_CONF_
-#define _CHIBIOS_RT_CONF_VER_6_1_
+#define _CHIBIOS_RT_CONF_VER_7_0_
+
+/*===========================================================================*/
+/**
+ * @name System settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Handling of instances.
+ * @note    If enabled then threads assigned to various instances can
+ *          interact each other using the same synchronization objects.
+ *          If disabled then each OS instance is a separate world, no
+ *          direct interactions are handled by the OS.
+ */
+#if !defined(CH_CFG_SMP_MODE)
+#define CH_CFG_SMP_MODE                     FALSE
+#endif
+
+/** @} */
 
 /*===========================================================================*/
 /**
@@ -161,6 +181,16 @@
 #endif
 
 /**
+ * @brief   Time Stamps APIs.
+ * @details If enabled then the time stamps APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_TIMESTAMP)
+#define CH_CFG_USE_TIMESTAMP                TRUE
+#endif
+
+/**
  * @brief   Threads registry APIs.
  * @details If enabled then the registry APIs are included in the kernel.
  *
@@ -631,7 +661,7 @@
  * @details User fields added to the end of the @p ch_system_t structure.
  */
 #define CH_CFG_SYSTEM_EXTRA_FIELDS                                          \
-  /* Add threads custom fields here.*/
+  /* Add system custom fields here.*/
 
 /**
  * @brief   System initialization hook.
@@ -639,7 +669,23 @@
  *          just before interrupts are enabled globally.
  */
 #define CH_CFG_SYSTEM_INIT_HOOK() {                                         \
-  /* Add threads initialization code here.*/                                \
+  /* Add system initialization code here.*/                                 \
+}
+
+/**
+ * @brief   OS instance structure extension.
+ * @details User fields added to the end of the @p os_instance_t structure.
+ */
+#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS                                     \
+  /* Add OS instance custom fields here.*/
+
+/**
+ * @brief   OS instance initialization hook.
+ *
+ * @param[in] oip       pointer to the @p os_instance_t structure
+ */
+#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) {                                 \
+  /* Add OS instance initialization code here.*/                            \
 }
 
 /**
@@ -655,6 +701,8 @@
  *
  * @note    It is invoked from within @p _thread_init() and implicitly from all
  *          the threads creation APIs.
+ *
+ * @param[in] tp        pointer to the @p thread_t structure
  */
 #define CH_CFG_THREAD_INIT_HOOK(tp) {                                       \
   /* Add threads initialization code here.*/                                \
@@ -663,6 +711,8 @@
 /**
  * @brief   Threads finalization hook.
  * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @param[in] tp        pointer to the @p thread_t structure
  */
 #define CH_CFG_THREAD_EXIT_HOOK(tp) {                                       \
   /* Add threads finalization code here.*/                                  \
@@ -671,6 +721,9 @@
 /**
  * @brief   Context switch hook.
  * @details This hook is invoked just before switching between threads.
+ *
+ * @param[in] ntp       thread being switched in
+ * @param[in] otp       thread being switched out
  */
 #define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) {                              \
   /* Context switch code here.*/                                            \
@@ -745,6 +798,14 @@
   /* Trace code here.*/                                                     \
 }
 
+/**
+ * @brief   Runtime Faults Collection Unit hook.
+ * @details This hook is invoked each time new faults are collected and stored.
+ */
+#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) {                                  \
+  /* Faults handling code here.*/                                           \
+}
+
 /** @} */
 
 /*===========================================================================*/
diff --git a/platforms/chibios/boards/QMK_PROTON_C/configs/halconf.h b/platforms/chibios/boards/QMK_PROTON_C/configs/halconf.h
index d7a639a6d0..8367328a04 100644
--- a/platforms/chibios/boards/QMK_PROTON_C/configs/halconf.h
+++ b/platforms/chibios/boards/QMK_PROTON_C/configs/halconf.h
@@ -1,5 +1,5 @@
 /*
-    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -29,7 +29,7 @@
 #define HALCONF_H
 
 #define _CHIBIOS_HAL_CONF_
-#define _CHIBIOS_HAL_CONF_VER_7_1_
+#define _CHIBIOS_HAL_CONF_VER_8_0_
 
 #include <mcuconf.h>
 
@@ -416,6 +416,26 @@
 #endif
 
 /*===========================================================================*/
+/* SIO driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ *          default configuration.
+ */
+#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SIO_DEFAULT_BITRATE                 38400
+#endif
+
+/**
+ * @brief   Support for thread synchronization API.
+ */
+#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__)
+#define SIO_USE_SYNCHRONIZATION             TRUE
+#endif
+
+/*===========================================================================*/
 /* SERIAL_USB driver related setting.                                        */
 /*===========================================================================*/
 
@@ -451,11 +471,10 @@
 #endif
 
 /**
- * @brief   Enables circular transfers APIs.
- * @note    Disabling this option saves both code and data space.
+ * @brief   Inserts an assertion on function errors before returning.
  */
-#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__)
-#define SPI_USE_CIRCULAR                    FALSE
+#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__)
+#define SPI_USE_ASSERT_ON_ERROR             TRUE
 #endif
 
 /**
diff --git a/platforms/chibios/boards/QMK_PROTON_C/configs/mcuconf.h b/platforms/chibios/boards/QMK_PROTON_C/configs/mcuconf.h
index 4d7b586c08..cab4c29cf6 100644
--- a/platforms/chibios/boards/QMK_PROTON_C/configs/mcuconf.h
+++ b/platforms/chibios/boards/QMK_PROTON_C/configs/mcuconf.h
@@ -1,5 +1,5 @@
 /*
-    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -186,7 +186,6 @@
 /*
  * PWM driver system settings.
  */
-#define STM32_PWM_USE_ADVANCED              FALSE
 #define STM32_PWM_USE_TIM1                  FALSE
 #define STM32_PWM_USE_TIM2                  FALSE
 #define STM32_PWM_USE_TIM3                  TRUE
diff --git a/platforms/chibios/boards/STM32_F103_STM32DUINO/board/board.c b/platforms/chibios/boards/STM32_F103_STM32DUINO/board/board.c
index 8a34e81f25..cba977da77 100644
--- a/platforms/chibios/boards/STM32_F103_STM32DUINO/board/board.c
+++ b/platforms/chibios/boards/STM32_F103_STM32DUINO/board/board.c
@@ -16,9 +16,6 @@
 
 #include <hal.h>
 
-// Value to place in RTC backup register 10 for persistent bootloader mode
-#define RTC_BOOTLOADER_FLAG 0x424C
-
 /**
  * @brief   PAL setup.
  * @details Digital I/O ports static configuration as defined in @p board.h.
diff --git a/platforms/chibios/boards/STM32_F103_STM32DUINO/configs/chconf.h b/platforms/chibios/boards/STM32_F103_STM32DUINO/configs/chconf.h
new file mode 100644
index 0000000000..0349c11dcc
--- /dev/null
+++ b/platforms/chibios/boards/STM32_F103_STM32DUINO/configs/chconf.h
@@ -0,0 +1,8 @@
+// Copyright 2022 QMK
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#pragma once
+
+#define CH_CFG_ST_TIMEDELTA 0
+
+#include_next <chconf.h>
diff --git a/platforms/chibios/boards/STM32_F103_STM32DUINO/configs/config.h b/platforms/chibios/boards/STM32_F103_STM32DUINO/configs/config.h
new file mode 100644
index 0000000000..d8b852cab7
--- /dev/null
+++ b/platforms/chibios/boards/STM32_F103_STM32DUINO/configs/config.h
@@ -0,0 +1,9 @@
+// Copyright 2022 Nick Brassel (@tzarc)
+// SPDX-License-Identifier: GPL-2.0-or-later
+#pragma once
+
+// Value to place in RTC backup register 10 for persistent bootloader mode
+#define RTC_BOOTLOADER_FLAG 0x424C
+
+// Value to place in RTC backup register 10 for instant reboot mode
+#define RTC_BOOTLOADER_JUST_UPLOADED 0x424D
diff --git a/platforms/chibios/boards/common/configs/chconf.h b/platforms/chibios/boards/common/configs/chconf.h
index 18ad609ca1..5db836e37c 100644
--- a/platforms/chibios/boards/common/configs/chconf.h
+++ b/platforms/chibios/boards/common/configs/chconf.h
@@ -1,5 +1,5 @@
 /*
-    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -29,7 +29,27 @@
 #define CHCONF_H
 
 #define _CHIBIOS_RT_CONF_
-#define _CHIBIOS_RT_CONF_VER_6_1_
+#define _CHIBIOS_RT_CONF_VER_7_0_
+
+/*===========================================================================*/
+/**
+ * @name System settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Handling of instances.
+ * @note    If enabled then threads assigned to various instances can
+ *          interact each other using the same synchronization objects.
+ *          If disabled then each OS instance is a separate world, no
+ *          direct interactions are handled by the OS.
+ */
+#if !defined(CH_CFG_SMP_MODE)
+#define CH_CFG_SMP_MODE                     FALSE
+#endif
+
+/** @} */
 
 /*===========================================================================*/
 /**
@@ -161,6 +181,16 @@
 #endif
 
 /**
+ * @brief   Time Stamps APIs.
+ * @details If enabled then the time stamps APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_TIMESTAMP)
+#define CH_CFG_USE_TIMESTAMP                TRUE
+#endif
+
+/**
  * @brief   Threads registry APIs.
  * @details If enabled then the registry APIs are included in the kernel.
  *
@@ -631,7 +661,7 @@
  * @details User fields added to the end of the @p ch_system_t structure.
  */
 #define CH_CFG_SYSTEM_EXTRA_FIELDS                                          \
-  /* Add threads custom fields here.*/
+  /* Add system custom fields here.*/
 
 /**
  * @brief   System initialization hook.
@@ -639,7 +669,23 @@
  *          just before interrupts are enabled globally.
  */
 #define CH_CFG_SYSTEM_INIT_HOOK() {                                         \
-  /* Add threads initialization code here.*/                                \
+  /* Add system initialization code here.*/                                 \
+}
+
+/**
+ * @brief   OS instance structure extension.
+ * @details User fields added to the end of the @p os_instance_t structure.
+ */
+#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS                                     \
+  /* Add OS instance custom fields here.*/
+
+/**
+ * @brief   OS instance initialization hook.
+ *
+ * @param[in] oip       pointer to the @p os_instance_t structure
+ */
+#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) {                                 \
+  /* Add OS instance initialization code here.*/                            \
 }
 
 /**
@@ -655,6 +701,8 @@
  *
  * @note    It is invoked from within @p _thread_init() and implicitly from all
  *          the threads creation APIs.
+ *
+ * @param[in] tp        pointer to the @p thread_t structure
  */
 #define CH_CFG_THREAD_INIT_HOOK(tp) {                                       \
   /* Add threads initialization code here.*/                                \
@@ -663,6 +711,8 @@
 /**
  * @brief   Threads finalization hook.
  * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @param[in] tp        pointer to the @p thread_t structure
  */
 #define CH_CFG_THREAD_EXIT_HOOK(tp) {                                       \
   /* Add threads finalization code here.*/                                  \
@@ -671,6 +721,9 @@
 /**
  * @brief   Context switch hook.
  * @details This hook is invoked just before switching between threads.
+ *
+ * @param[in] ntp       thread being switched in
+ * @param[in] otp       thread being switched out
  */
 #define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) {                              \
   /* Context switch code here.*/                                            \
@@ -745,6 +798,14 @@
   /* Trace code here.*/                                                     \
 }
 
+/**
+ * @brief   Runtime Faults Collection Unit hook.
+ * @details This hook is invoked each time new faults are collected and stored.
+ */
+#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) {                                  \
+  /* Faults handling code here.*/                                           \
+}
+
 /** @} */
 
 /*===========================================================================*/
diff --git a/platforms/chibios/boards/common/configs/halconf.h b/platforms/chibios/boards/common/configs/halconf.h
index c80f67ee27..1805a77438 100644
--- a/platforms/chibios/boards/common/configs/halconf.h
+++ b/platforms/chibios/boards/common/configs/halconf.h
@@ -1,5 +1,5 @@
 /*
-    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -29,7 +29,7 @@
 #define HALCONF_H
 
 #define _CHIBIOS_HAL_CONF_
-#define _CHIBIOS_HAL_CONF_VER_7_1_
+#define _CHIBIOS_HAL_CONF_VER_8_0_
 
 #include <mcuconf.h>
 
@@ -416,6 +416,26 @@
 #endif
 
 /*===========================================================================*/
+/* SIO driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ *          default configuration.
+ */
+#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SIO_DEFAULT_BITRATE                 38400
+#endif
+
+/**
+ * @brief   Support for thread synchronization API.
+ */
+#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__)
+#define SIO_USE_SYNCHRONIZATION             TRUE
+#endif
+
+/*===========================================================================*/
 /* SERIAL_USB driver related setting.                                        */
 /*===========================================================================*/
 
@@ -451,11 +471,10 @@
 #endif
 
 /**
- * @brief   Enables circular transfers APIs.
- * @note    Disabling this option saves both code and data space.
+ * @brief   Inserts an assertion on function errors before returning.
  */
-#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__)
-#define SPI_USE_CIRCULAR                    FALSE
+#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__)
+#define SPI_USE_ASSERT_ON_ERROR             TRUE
 #endif
 
 /**
diff --git a/platforms/chibios/boards/BLACKPILL_STM32_F401/ld/STM32F401xC_tinyuf2.ld b/platforms/chibios/boards/common/ld/STM32F401xC_tinyuf2.ld
index f4e487dc8f..f4e487dc8f 100644
--- a/platforms/chibios/boards/BLACKPILL_STM32_F401/ld/STM32F401xC_tinyuf2.ld
+++ b/platforms/chibios/boards/common/ld/STM32F401xC_tinyuf2.ld
diff --git a/platforms/chibios/boards/BLACKPILL_STM32_F401/ld/STM32F401xE_tinyuf2.ld b/platforms/chibios/boards/common/ld/STM32F401xE_tinyuf2.ld
index 895d13fa32..895d13fa32 100644
--- a/platforms/chibios/boards/BLACKPILL_STM32_F401/ld/STM32F401xE_tinyuf2.ld
+++ b/platforms/chibios/boards/common/ld/STM32F401xE_tinyuf2.ld
diff --git a/platforms/chibios/boards/BLACKPILL_STM32_F411/ld/STM32F411xC_tinyuf2.ld b/platforms/chibios/boards/common/ld/STM32F411xC_tinyuf2.ld
index 82253d3de5..82253d3de5 100644
--- a/platforms/chibios/boards/BLACKPILL_STM32_F411/ld/STM32F411xC_tinyuf2.ld
+++ b/platforms/chibios/boards/common/ld/STM32F411xC_tinyuf2.ld
diff --git a/platforms/chibios/boards/BLACKPILL_STM32_F411/ld/STM32F411xE_tinyuf2.ld b/platforms/chibios/boards/common/ld/STM32F411xE_tinyuf2.ld
index 1656c67bf7..1656c67bf7 100644
--- a/platforms/chibios/boards/BLACKPILL_STM32_F411/ld/STM32F411xE_tinyuf2.ld
+++ b/platforms/chibios/boards/common/ld/STM32F411xE_tinyuf2.ld
diff --git a/platforms/chibios/bootloaders/custom.c b/platforms/chibios/bootloaders/custom.c
index bba9fc4637..6c5a433953 100644
--- a/platforms/chibios/bootloaders/custom.c
+++ b/platforms/chibios/bootloaders/custom.c
@@ -17,5 +17,6 @@
 #include "bootloader.h"
 
 __attribute__((weak)) void bootloader_jump(void) {}
+__attribute__((weak)) void mcu_reset(void) {}
 
 __attribute__((weak)) void enter_bootloader_mode_if_requested(void) {}
diff --git a/platforms/chibios/bootloaders/gd32v_dfu.c b/platforms/chibios/bootloaders/gd32v_dfu.c
index baa7d1f882..100fc472f8 100644
--- a/platforms/chibios/bootloaders/gd32v_dfu.c
+++ b/platforms/chibios/bootloaders/gd32v_dfu.c
@@ -36,5 +36,12 @@ __attribute__((weak)) void bootloader_jump(void) {
     *DBGMCU_CMD = DBGMCU_CMD_RESET;
 }
 
+__attribute__((weak)) void mcu_reset(void) {
+    // Confirmed by karlk90, there is no actual reset to bootloader.
+    // This just resets the controller.
+    *DBGMCU_KEY = DBGMCU_KEY_UNLOCK;
+    *DBGMCU_CMD = DBGMCU_CMD_RESET;
+}
+
 /* Jumping to bootloader is not possible from user code. */
 void enter_bootloader_mode_if_requested(void) {}
diff --git a/platforms/chibios/bootloaders/halfkay.c b/platforms/chibios/bootloaders/halfkay.c
index 168c2abc23..aa11e6c5f4 100644
--- a/platforms/chibios/bootloaders/halfkay.c
+++ b/platforms/chibios/bootloaders/halfkay.c
@@ -23,3 +23,5 @@ __attribute__((weak)) void bootloader_jump(void) {
     wait_ms(100);
     __BKPT(0);
 }
+
+__attribute__((weak)) void mcu_reset(void) {}
diff --git a/platforms/chibios/bootloaders/kiibohd.c b/platforms/chibios/bootloaders/kiibohd.c
index 911e807092..09a4d49b78 100644
--- a/platforms/chibios/bootloaders/kiibohd.c
+++ b/platforms/chibios/bootloaders/kiibohd.c
@@ -30,3 +30,4 @@ __attribute__((weak)) void bootloader_jump(void) {
     // request reset
     SCB->AIRCR = SCB_AIRCR_VECTKEY_WRITEMAGIC | SCB_AIRCR_SYSRESETREQ_Msk;
 }
+__attribute__((weak)) void mcu_reset(void) {}
diff --git a/platforms/chibios/bootloaders/stm32_dfu.c b/platforms/chibios/bootloaders/stm32_dfu.c
index 0e74111367..ff866bd2bc 100644
--- a/platforms/chibios/bootloaders/stm32_dfu.c
+++ b/platforms/chibios/bootloaders/stm32_dfu.c
@@ -61,6 +61,9 @@ __attribute__((weak)) void bootloader_jump(void) {
     NVIC_SystemReset();
 }
 
+__attribute__((weak)) void mcu_reset(void) {
+    NVIC_SystemReset();
+}
 // not needed at all, but if anybody attempts to invoke it....
 void enter_bootloader_mode_if_requested(void) {}
 
@@ -76,6 +79,10 @@ __attribute__((weak)) void bootloader_jump(void) {
     NVIC_SystemReset();
 }
 
+__attribute__((weak)) void mcu_reset(void) {
+    NVIC_SystemReset();
+}
+
 void enter_bootloader_mode_if_requested(void) {
     unsigned long *check = MAGIC_ADDR;
     if (*check == BOOTLOADER_MAGIC) {
diff --git a/platforms/chibios/bootloaders/stm32duino.c b/platforms/chibios/bootloaders/stm32duino.c
index 53d3ba0adb..e2db7fa16c 100644
--- a/platforms/chibios/bootloaders/stm32duino.c
+++ b/platforms/chibios/bootloaders/stm32duino.c
@@ -21,3 +21,8 @@
 __attribute__((weak)) void bootloader_jump(void) {
     NVIC_SystemReset();
 }
+
+__attribute__((weak)) void mcu_reset(void) {
+    BKP->DR10 = RTC_BOOTLOADER_JUST_UPLOADED;
+    NVIC_SystemReset();
+}
\ No newline at end of file
diff --git a/platforms/chibios/bootloaders/tinyuf2.c b/platforms/chibios/bootloaders/tinyuf2.c
index 9ffca5dec8..e08855b6c4 100644
--- a/platforms/chibios/bootloaders/tinyuf2.c
+++ b/platforms/chibios/bootloaders/tinyuf2.c
@@ -25,6 +25,10 @@
 extern uint32_t _board_dfu_dbl_tap[];
 #define DBL_TAP_REG _board_dfu_dbl_tap[0]
 
+__attribute__((weak)) void mcu_reset(void) {
+    NVIC_SystemReset();
+}
+
 __attribute__((weak)) void bootloader_jump(void) {
     DBL_TAP_REG = DBL_TAP_MAGIC;
     NVIC_SystemReset();
diff --git a/platforms/chibios/bootloaders/wb32_dfu.c b/platforms/chibios/bootloaders/wb32_dfu.c
new file mode 100644
index 0000000000..d021b0863b
--- /dev/null
+++ b/platforms/chibios/bootloaders/wb32_dfu.c
@@ -0,0 +1,53 @@
+/* Copyright 2021 QMK
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "bootloader.h"
+
+#include <ch.h>
+#include <hal.h>
+#include "wait.h"
+
+extern uint32_t __ram0_end__;
+
+/* This code should be checked whether it runs correctly on platforms */
+#define SYMVAL(sym) (uint32_t)(((uint8_t *)&(sym)) - ((uint8_t *)0))
+#define BOOTLOADER_MAGIC 0xDEADBEEF
+#define MAGIC_ADDR (unsigned long *)(SYMVAL(__ram0_end__) - 4)
+
+__attribute__((weak)) void bootloader_jump(void) {
+    *MAGIC_ADDR = BOOTLOADER_MAGIC; // set magic flag => reset handler will jump into boot loader
+    NVIC_SystemReset();
+}
+
+void enter_bootloader_mode_if_requested(void) {
+    unsigned long *check = MAGIC_ADDR;
+    if (*check == BOOTLOADER_MAGIC) {
+        *check = 0;
+        __set_CONTROL(0);
+        __set_MSP(*(__IO uint32_t *)WB32_BOOTLOADER_ADDRESS);
+        __enable_irq();
+
+        typedef void (*BootJump_t)(void);
+        BootJump_t boot_jump = *(BootJump_t *)(WB32_BOOTLOADER_ADDRESS + 4);
+        boot_jump();
+        while (1)
+            ;
+    }
+}
+
+__attribute__((weak)) void mcu_reset(void) {
+    NVIC_SystemReset();
+}
diff --git a/platforms/chibios/chibios_config.h b/platforms/chibios/chibios_config.h
index 67d7541ba2..a7098f2713 100644
--- a/platforms/chibios/chibios_config.h
+++ b/platforms/chibios/chibios_config.h
@@ -55,7 +55,7 @@
 #if defined(MCU_WB32)
 #    define CPU_CLOCK WB32_MAINCLK
 
-#    if defined(WB32F3G71xx)
+#    if defined(WB32F3G71xx) || defined(WB32FQ95xx)
 #        define PAL_OUTPUT_TYPE_OPENDRAIN PAL_WB32_OTYPE_OPENDRAIN
 #        define PAL_OUTPUT_TYPE_PUSHPULL PAL_WB32_OTYPE_PUSHPULL
 #        define PAL_OUTPUT_SPEED_HIGHEST PAL_WB32_OSPEED_HIGH
diff --git a/platforms/chibios/converters/promicro_to_proton_c/_pin_defs.h b/platforms/chibios/converters/promicro_to_proton_c/_pin_defs.h
new file mode 100644
index 0000000000..ad1a81692e
--- /dev/null
+++ b/platforms/chibios/converters/promicro_to_proton_c/_pin_defs.h
@@ -0,0 +1,41 @@
+// Copyright 2022 QMK
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#pragma once
+
+// Left side (front)
+#define D3 PAL_LINE(GPIOA, 9)
+#define D2 PAL_LINE(GPIOA, 10)
+//      GND
+//      GND
+#define D1 PAL_LINE(GPIOB, 7)
+#define D0 PAL_LINE(GPIOB, 6)
+#define D4 PAL_LINE(GPIOB, 5)
+#define C6 PAL_LINE(GPIOB, 4)
+#define D7 PAL_LINE(GPIOB, 3)
+#define E6 PAL_LINE(GPIOB, 2)
+#define B4 PAL_LINE(GPIOB, 1)
+#define B5 PAL_LINE(GPIOB, 0)
+
+// Right side (front)
+//      RAW
+//      GND
+//      RESET
+//      VCC
+#define F4 PAL_LINE(GPIOA, 2)
+#define F5 PAL_LINE(GPIOA, 1)
+#define F6 PAL_LINE(GPIOA, 0)
+#define F7 PAL_LINE(GPIOB, 8)
+#define B1 PAL_LINE(GPIOB, 13)
+#define B3 PAL_LINE(GPIOB, 14)
+#define B2 PAL_LINE(GPIOB, 15)
+#define B6 PAL_LINE(GPIOB, 9)
+
+// LEDs (only D5/C13 uses an actual LED)
+#ifdef CONVERT_TO_PROTON_C_RXLED
+#    define D5 PAL_LINE(GPIOC, 14)
+#    define B0 PAL_LINE(GPIOC, 13)
+#else
+#    define D5 PAL_LINE(GPIOC, 13)
+#    define B0 PAL_LINE(GPIOC, 14)
+#endif
diff --git a/platforms/chibios/boards/QMK_PROTON_C/convert_to_proton_c.mk b/platforms/chibios/converters/promicro_to_proton_c/converter.mk
index 0618154678..406adae32c 100644
--- a/platforms/chibios/boards/QMK_PROTON_C/convert_to_proton_c.mk
+++ b/platforms/chibios/converters/promicro_to_proton_c/converter.mk
@@ -1,9 +1,7 @@
 # Proton C MCU settings for converting AVR projects
-TARGET := $(TARGET)_proton_c
 MCU := STM32F303
 BOARD := QMK_PROTON_C
 BOOTLOADER := stm32-dfu
-OPT_DEFS += -DCONVERT_TO_PROTON_C
 
 # These are defaults based on what has been implemented for ARM boards
 AUDIO_ENABLE ?= yes
diff --git a/platforms/chibios/drivers/i2c_master.c b/platforms/chibios/drivers/i2c_master.c
index d10bdbabc1..21e064b1dc 100644
--- a/platforms/chibios/drivers/i2c_master.c
+++ b/platforms/chibios/drivers/i2c_master.c
@@ -97,7 +97,7 @@ static const I2CConfig i2cconfig = {
     I2C1_OPMODE,
     I2C1_CLOCK_SPEED,
     I2C1_DUTY_CYCLE,
-#elif defined(WB32F3G71xx)
+#elif defined(WB32F3G71xx) || defined(WB32FQ95xx)
     I2C1_OPMODE,
     I2C1_CLOCK_SPEED,
 #else
diff --git a/platforms/chibios/drivers/serial.c b/platforms/chibios/drivers/serial.c
index bb7b3c0554..0cff057d1d 100644
--- a/platforms/chibios/drivers/serial.c
+++ b/platforms/chibios/drivers/serial.c
@@ -5,6 +5,7 @@
 #include "quantum.h"
 #include "serial.h"
 #include "wait.h"
+#include "synchronization_util.h"
 
 #include <hal.h>
 
@@ -86,7 +87,10 @@ static THD_FUNCTION(Thread1, arg) {
     chRegSetThreadName("blinker");
     while (true) {
         palWaitLineTimeout(SOFT_SERIAL_PIN, TIME_INFINITE);
+
+        split_shared_memory_lock();
         interrupt_handler(NULL);
+        split_shared_memory_unlock();
     }
 }
 
@@ -205,14 +209,9 @@ void interrupt_handler(void *arg) {
     chSysUnlockFromISR();
 }
 
-/////////
-//  start transaction by initiator
-//
-// bool  soft_serial_transaction(int sstd_index)
-//
-// this code is very time dependent, so we need to disable interrupts
-bool soft_serial_transaction(int sstd_index) {
+static inline bool initiate_transaction(uint8_t sstd_index) {
     if (sstd_index > NUM_TOTAL_TRANSACTIONS) return false;
+
     split_transaction_desc_t *trans = &split_transaction_table[sstd_index];
 
     // TODO: remove extra delay between transactions
@@ -239,8 +238,7 @@ bool soft_serial_transaction(int sstd_index) {
         return false;
     }
 
-    // if the slave is present syncronize with it
-
+    // if the slave is present synchronize with it
     uint8_t checksum = 0;
     // send data to the slave
     serial_write_byte(sstd_index); // first chunk is transaction id
@@ -286,3 +284,16 @@ bool soft_serial_transaction(int sstd_index) {
     chSysUnlock();
     return true;
 }
+
+/////////
+//  start transaction by initiator
+//
+// bool  soft_serial_transaction(int sstd_index)
+//
+// this code is very time dependent, so we need to disable interrupts
+bool soft_serial_transaction(int sstd_index) {
+    split_shared_memory_lock();
+    bool result = initiate_transaction((uint8_t)sstd_index);
+    split_shared_memory_unlock();
+    return result;
+}
diff --git a/platforms/chibios/drivers/serial_usart.c b/platforms/chibios/drivers/serial_usart.c
index 85c64214d1..e9fa4af7a3 100644
--- a/platforms/chibios/drivers/serial_usart.c
+++ b/platforms/chibios/drivers/serial_usart.c
@@ -15,6 +15,7 @@
  */
 
 #include "serial_usart.h"
+#include "synchronization_util.h"
 
 #if defined(SERIAL_USART_CONFIG)
 static SerialConfig serial_config = SERIAL_USART_CONFIG;
@@ -173,6 +174,7 @@ static THD_FUNCTION(SlaveThread, arg) {
              * Parts of failed transactions or spurious bytes could still be in it. */
             usart_clear();
         }
+        split_shared_memory_unlock();
     }
 }
 
@@ -200,6 +202,7 @@ static inline bool react_to_transactions(void) {
         return false;
     }
 
+    split_shared_memory_lock();
     split_transaction_desc_t* trans = &split_transaction_table[sstd_index];
 
     /* Send back the handshake which is XORed as a simple checksum,
@@ -254,7 +257,12 @@ bool soft_serial_transaction(int index) {
     /* Clear the receive queue, to start with a clean slate.
      * Parts of failed transactions or spurious bytes could still be in it. */
     usart_clear();
-    return initiate_transaction((uint8_t)index);
+
+    split_shared_memory_lock();
+    bool result = initiate_transaction((uint8_t)index);
+    split_shared_memory_unlock();
+
+    return result;
 }
 
 /**
diff --git a/platforms/chibios/drivers/spi_master.c b/platforms/chibios/drivers/spi_master.c
index 998bace550..ce69e7f0ac 100644
--- a/platforms/chibios/drivers/spi_master.c
+++ b/platforms/chibios/drivers/spi_master.c
@@ -54,7 +54,7 @@ bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
         return false;
     }
 
-#ifndef WB32F3G71xx
+#if !(defined(WB32F3G71xx) || defined(WB32FQ95xx))
     uint16_t roundedDivisor = 2;
     while (roundedDivisor < divisor) {
         roundedDivisor <<= 1;
@@ -138,7 +138,7 @@ bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
 
     spiConfig.cpr = (roundedDivisor - 1) >> 1;
 
-#elif defined(WB32F3G71xx)
+#elif defined(WB32F3G71xx) || defined(WB32FQ95xx)
     if (!lsbFirst) {
         osalDbgAssert(lsbFirst != FALSE, "unsupported lsbFirst");
     }
diff --git a/platforms/chibios/drivers/uart.c b/platforms/chibios/drivers/uart.c
index 4884d7024f..396803f33b 100644
--- a/platforms/chibios/drivers/uart.c
+++ b/platforms/chibios/drivers/uart.c
@@ -18,7 +18,7 @@
 
 #include "quantum.h"
 
-#if defined(WB32F3G71xx)
+#if defined(WB32F3G71xx) || defined(WB32FQ95xx)
 static SerialConfig serialConfig = {SERIAL_DEFAULT_BITRATE, SD1_WRDLEN, SD1_STPBIT, SD1_PARITY, SD1_ATFLCT};
 #else
 static SerialConfig serialConfig = {SERIAL_DEFAULT_BITRATE, SD1_CR1, SD1_CR2, SD1_CR3};
diff --git a/platforms/chibios/drivers/ws2812_spi.c b/platforms/chibios/drivers/ws2812_spi.c
index 76191db165..01d8148875 100644
--- a/platforms/chibios/drivers/ws2812_spi.c
+++ b/platforms/chibios/drivers/ws2812_spi.c
@@ -139,7 +139,33 @@ void ws2812_init(void) {
 #endif // WS2812_SPI_SCK_PIN
 
     // TODO: more dynamic baudrate
-    static const SPIConfig spicfg = {WS2812_SPI_BUFFER_MODE, NULL, PAL_PORT(RGB_DI_PIN), PAL_PAD(RGB_DI_PIN), WS2812_SPI_DIVISOR_CR1_BR_X};
+    static const SPIConfig spicfg = {
+#ifndef HAL_LLD_SELECT_SPI_V2
+// HAL_SPI_V1
+#    if SPI_SUPPORTS_CIRCULAR == TRUE
+        WS2812_SPI_BUFFER_MODE,
+#    endif
+        NULL, // end_cb
+        PAL_PORT(RGB_DI_PIN),
+        PAL_PAD(RGB_DI_PIN),
+        WS2812_SPI_DIVISOR_CR1_BR_X,
+        0
+#else
+    // HAL_SPI_V2
+#    if SPI_SUPPORTS_CIRCULAR == TRUE
+        WS2812_SPI_BUFFER_MODE,
+#    endif
+#    if SPI_SUPPORTS_SLAVE_MODE == TRUE
+        false,
+#    endif
+        NULL, // data_cb
+        NULL, // error_cb
+        PAL_PORT(RGB_DI_PIN),
+        PAL_PAD(RGB_DI_PIN),
+        WS2812_SPI_DIVISOR_CR1_BR_X,
+        0
+#endif
+    };
 
     spiAcquireBus(&WS2812_SPI);     /* Acquire ownership of the bus.    */
     spiStart(&WS2812_SPI, &spicfg); /* Setup transfer parameters.       */
diff --git a/platforms/chibios/eeprom_stm32_defs.h b/platforms/chibios/eeprom_stm32_defs.h
index a6ceb41355..57d0440330 100644
--- a/platforms/chibios/eeprom_stm32_defs.h
+++ b/platforms/chibios/eeprom_stm32_defs.h
@@ -25,7 +25,7 @@
 #        ifndef FEE_PAGE_COUNT
 #            define FEE_PAGE_COUNT 2 // How many pages are used
 #        endif
-#    elif defined(STM32F103xE) || defined(STM32F303xC) || defined(STM32F072xB) || defined(STM32F070xB)
+#    elif defined(STM32F103xE) || defined(STM32F303xC) || defined(STM32F303xE) || defined(STM32F072xB) || defined(STM32F070xB)
 #        ifndef FEE_PAGE_SIZE
 #            define FEE_PAGE_SIZE 0x800 // Page size = 2KByte
 #        endif
@@ -51,7 +51,7 @@
 #        define FEE_MCU_FLASH_SIZE 128 // Size in Kb
 #    elif defined(STM32F303xC) || defined(STM32F401xC)
 #        define FEE_MCU_FLASH_SIZE 256 // Size in Kb
-#    elif defined(STM32F103xE) || defined(STM32F401xE) || defined(STM32F411xE)
+#    elif defined(STM32F103xE) || defined(STM32F303xE) || defined(STM32F401xE) || defined(STM32F411xE)
 #        define FEE_MCU_FLASH_SIZE 512 // Size in Kb
 #    elif defined(STM32F405xG)
 #        define FEE_MCU_FLASH_SIZE 1024 // Size in Kb
diff --git a/platforms/chibios/flash.mk b/platforms/chibios/flash.mk
index 6ee53172d2..a91ef2cf35 100644
--- a/platforms/chibios/flash.mk
+++ b/platforms/chibios/flash.mk
@@ -40,6 +40,18 @@ endef
 dfu-util: $(BUILD_DIR)/$(TARGET).bin cpfirmware sizeafter
 	$(call EXEC_DFU_UTIL)
 
+define EXEC_UF2_UTIL_DEPLOY
+	if ! $(UF2CONV) --deploy $(BUILD_DIR)/$(TARGET).uf2 2>/dev/null; then \
+		printf "$(MSG_BOOTLOADER_NOT_FOUND_QUICK_RETRY)" ;\
+		sleep $(BOOTLOADER_RETRY_TIME) ;\
+		while ! $(UF2CONV) --deploy $(BUILD_DIR)/$(TARGET).uf2  2>/dev/null; do \
+			printf "." ;\
+			sleep $(BOOTLOADER_RETRY_TIME) ;\
+		done ;\
+		printf "\n" ;\
+	fi
+endef
+
 # TODO: Remove once ARM has a way to configure EECONFIG_HANDEDNESS
 #       within the emulated eeprom via dfu-util or another tool
 ifneq (,$(filter $(MAKECMDGOALS),dfu-util-split-left))
@@ -90,6 +102,8 @@ ifneq ($(strip $(PROGRAM_CMD)),)
 	$(UNSYNC_OUTPUT_CMD) && $(PROGRAM_CMD)
 else ifeq ($(strip $(BOOTLOADER)),kiibohd)
 	$(UNSYNC_OUTPUT_CMD) && $(call EXEC_DFU_UTIL)
+else ifeq ($(strip $(BOOTLOADER)),tinyuf2)
+	$(UNSYNC_OUTPUT_CMD) && $(call EXEC_UF2_UTIL_DEPLOY)
 else ifeq ($(strip $(MCU_FAMILY)),KINETIS)
 	$(UNSYNC_OUTPUT_CMD) && $(call EXEC_TEENSY)
 else ifeq ($(strip $(MCU_FAMILY)),MIMXRT1062)
diff --git a/platforms/chibios/gpio.h b/platforms/chibios/gpio.h
index eb44a18f9c..80551abac5 100644
--- a/platforms/chibios/gpio.h
+++ b/platforms/chibios/gpio.h
@@ -31,7 +31,14 @@ typedef ioline_t pin_t;
 
 #define writePinHigh(pin) palSetLine(pin)
 #define writePinLow(pin) palClearLine(pin)
-#define writePin(pin, level) ((level) ? (writePinHigh(pin)) : (writePinLow(pin)))
+#define writePin(pin, level)   \
+    do {                       \
+        if (level) {           \
+            writePinHigh(pin); \
+        } else {               \
+            writePinLow(pin);  \
+        }                      \
+    } while (0)
 
 #define readPin(pin) palReadLine(pin)
 
diff --git a/platforms/chibios/hardware_id.c b/platforms/chibios/hardware_id.c
new file mode 100644
index 0000000000..888a275465
--- /dev/null
+++ b/platforms/chibios/hardware_id.c
@@ -0,0 +1,15 @@
+// Copyright 2022 QMK
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <ch.h>
+#include "hardware_id.h"
+
+hardware_id_t get_hardware_id(void) {
+    hardware_id_t id = {0};
+#ifdef UID_BASE
+    id.data[0] = (uint32_t)(*((uint32_t *)UID_BASE));
+    id.data[1] = (uint32_t)(*((uint32_t *)(UID_BASE + 4)));
+    id.data[1] = (uint32_t)(*((uint32_t *)(UID_BASE + 8)));
+#endif
+    return id;
+}
diff --git a/platforms/chibios/pin_defs.h b/platforms/chibios/pin_defs.h
deleted file mode 100644
index c03f8de0c2..0000000000
--- a/platforms/chibios/pin_defs.h
+++ /dev/null
@@ -1,323 +0,0 @@
-/* Copyright 2021 QMK
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-#pragma once
-
-// Defines mapping for Proton C replacement
-#ifdef CONVERT_TO_PROTON_C
-// Left side (front)
-#    define D3 PAL_LINE(GPIOA, 9)
-#    define D2 PAL_LINE(GPIOA, 10)
-//      GND
-//      GND
-#    define D1 PAL_LINE(GPIOB, 7)
-#    define D0 PAL_LINE(GPIOB, 6)
-#    define D4 PAL_LINE(GPIOB, 5)
-#    define C6 PAL_LINE(GPIOB, 4)
-#    define D7 PAL_LINE(GPIOB, 3)
-#    define E6 PAL_LINE(GPIOB, 2)
-#    define B4 PAL_LINE(GPIOB, 1)
-#    define B5 PAL_LINE(GPIOB, 0)
-
-// Right side (front)
-//      RAW
-//      GND
-//      RESET
-//      VCC
-#    define F4 PAL_LINE(GPIOA, 2)
-#    define F5 PAL_LINE(GPIOA, 1)
-#    define F6 PAL_LINE(GPIOA, 0)
-#    define F7 PAL_LINE(GPIOB, 8)
-#    define B1 PAL_LINE(GPIOB, 13)
-#    define B3 PAL_LINE(GPIOB, 14)
-#    define B2 PAL_LINE(GPIOB, 15)
-#    define B6 PAL_LINE(GPIOB, 9)
-
-// LEDs (only D5/C13 uses an actual LED)
-#    ifdef CONVERT_TO_PROTON_C_RXLED
-#        define D5 PAL_LINE(GPIOC, 14)
-#        define B0 PAL_LINE(GPIOC, 13)
-#    else
-#        define D5 PAL_LINE(GPIOC, 13)
-#        define B0 PAL_LINE(GPIOC, 14)
-#    endif
-#else
-#    define A0 PAL_LINE(GPIOA, 0)
-#    define A1 PAL_LINE(GPIOA, 1)
-#    define A2 PAL_LINE(GPIOA, 2)
-#    define A3 PAL_LINE(GPIOA, 3)
-#    define A4 PAL_LINE(GPIOA, 4)
-#    define A5 PAL_LINE(GPIOA, 5)
-#    define A6 PAL_LINE(GPIOA, 6)
-#    define A7 PAL_LINE(GPIOA, 7)
-#    define A8 PAL_LINE(GPIOA, 8)
-#    define A9 PAL_LINE(GPIOA, 9)
-#    define A10 PAL_LINE(GPIOA, 10)
-#    define A11 PAL_LINE(GPIOA, 11)
-#    define A12 PAL_LINE(GPIOA, 12)
-#    define A13 PAL_LINE(GPIOA, 13)
-#    define A14 PAL_LINE(GPIOA, 14)
-#    define A15 PAL_LINE(GPIOA, 15)
-#    define A16 PAL_LINE(GPIOA, 16)
-#    define A17 PAL_LINE(GPIOA, 17)
-#    define A18 PAL_LINE(GPIOA, 18)
-#    define A19 PAL_LINE(GPIOA, 19)
-#    define A20 PAL_LINE(GPIOA, 20)
-#    define A21 PAL_LINE(GPIOA, 21)
-#    define A22 PAL_LINE(GPIOA, 22)
-#    define A23 PAL_LINE(GPIOA, 23)
-#    define A24 PAL_LINE(GPIOA, 24)
-#    define A25 PAL_LINE(GPIOA, 25)
-#    define A26 PAL_LINE(GPIOA, 26)
-#    define A27 PAL_LINE(GPIOA, 27)
-#    define A28 PAL_LINE(GPIOA, 28)
-#    define A29 PAL_LINE(GPIOA, 29)
-#    define A30 PAL_LINE(GPIOA, 30)
-#    define A31 PAL_LINE(GPIOA, 31)
-#    define A32 PAL_LINE(GPIOA, 32)
-#    define B0 PAL_LINE(GPIOB, 0)
-#    define B1 PAL_LINE(GPIOB, 1)
-#    define B2 PAL_LINE(GPIOB, 2)
-#    define B3 PAL_LINE(GPIOB, 3)
-#    define B4 PAL_LINE(GPIOB, 4)
-#    define B5 PAL_LINE(GPIOB, 5)
-#    define B6 PAL_LINE(GPIOB, 6)
-#    define B7 PAL_LINE(GPIOB, 7)
-#    define B8 PAL_LINE(GPIOB, 8)
-#    define B9 PAL_LINE(GPIOB, 9)
-#    define B10 PAL_LINE(GPIOB, 10)
-#    define B11 PAL_LINE(GPIOB, 11)
-#    define B12 PAL_LINE(GPIOB, 12)
-#    define B13 PAL_LINE(GPIOB, 13)
-#    define B14 PAL_LINE(GPIOB, 14)
-#    define B15 PAL_LINE(GPIOB, 15)
-#    define B16 PAL_LINE(GPIOB, 16)
-#    define B17 PAL_LINE(GPIOB, 17)
-#    define B18 PAL_LINE(GPIOB, 18)
-#    define B19 PAL_LINE(GPIOB, 19)
-#    define B20 PAL_LINE(GPIOB, 20)
-#    define B21 PAL_LINE(GPIOB, 21)
-#    define B22 PAL_LINE(GPIOB, 22)
-#    define B23 PAL_LINE(GPIOB, 23)
-#    define B24 PAL_LINE(GPIOB, 24)
-#    define B25 PAL_LINE(GPIOB, 25)
-#    define B26 PAL_LINE(GPIOB, 26)
-#    define B27 PAL_LINE(GPIOB, 27)
-#    define B28 PAL_LINE(GPIOB, 28)
-#    define B29 PAL_LINE(GPIOB, 29)
-#    define B30 PAL_LINE(GPIOB, 30)
-#    define B31 PAL_LINE(GPIOB, 31)
-#    define B32 PAL_LINE(GPIOB, 32)
-#    define C0 PAL_LINE(GPIOC, 0)
-#    define C1 PAL_LINE(GPIOC, 1)
-#    define C2 PAL_LINE(GPIOC, 2)
-#    define C3 PAL_LINE(GPIOC, 3)
-#    define C4 PAL_LINE(GPIOC, 4)
-#    define C5 PAL_LINE(GPIOC, 5)
-#    define C6 PAL_LINE(GPIOC, 6)
-#    define C7 PAL_LINE(GPIOC, 7)
-#    define C8 PAL_LINE(GPIOC, 8)
-#    define C9 PAL_LINE(GPIOC, 9)
-#    define C10 PAL_LINE(GPIOC, 10)
-#    define C11 PAL_LINE(GPIOC, 11)
-#    define C12 PAL_LINE(GPIOC, 12)
-#    define C13 PAL_LINE(GPIOC, 13)
-#    define C14 PAL_LINE(GPIOC, 14)
-#    define C15 PAL_LINE(GPIOC, 15)
-#    define C16 PAL_LINE(GPIOC, 16)
-#    define C17 PAL_LINE(GPIOC, 17)
-#    define C18 PAL_LINE(GPIOC, 18)
-#    define C19 PAL_LINE(GPIOC, 19)
-#    define C20 PAL_LINE(GPIOC, 20)
-#    define C21 PAL_LINE(GPIOC, 21)
-#    define C22 PAL_LINE(GPIOC, 22)
-#    define C23 PAL_LINE(GPIOC, 23)
-#    define C24 PAL_LINE(GPIOC, 24)
-#    define C25 PAL_LINE(GPIOC, 25)
-#    define C26 PAL_LINE(GPIOC, 26)
-#    define C27 PAL_LINE(GPIOC, 27)
-#    define C28 PAL_LINE(GPIOC, 28)
-#    define C29 PAL_LINE(GPIOC, 29)
-#    define C30 PAL_LINE(GPIOC, 30)
-#    define C31 PAL_LINE(GPIOC, 31)
-#    define C32 PAL_LINE(GPIOC, 32)
-#    define D0 PAL_LINE(GPIOD, 0)
-#    define D1 PAL_LINE(GPIOD, 1)
-#    define D2 PAL_LINE(GPIOD, 2)
-#    define D3 PAL_LINE(GPIOD, 3)
-#    define D4 PAL_LINE(GPIOD, 4)
-#    define D5 PAL_LINE(GPIOD, 5)
-#    define D6 PAL_LINE(GPIOD, 6)
-#    define D7 PAL_LINE(GPIOD, 7)
-#    define D8 PAL_LINE(GPIOD, 8)
-#    define D9 PAL_LINE(GPIOD, 9)
-#    define D10 PAL_LINE(GPIOD, 10)
-#    define D11 PAL_LINE(GPIOD, 11)
-#    define D12 PAL_LINE(GPIOD, 12)
-#    define D13 PAL_LINE(GPIOD, 13)
-#    define D14 PAL_LINE(GPIOD, 14)
-#    define D15 PAL_LINE(GPIOD, 15)
-#    define D16 PAL_LINE(GPIOD, 16)
-#    define D17 PAL_LINE(GPIOD, 17)
-#    define D18 PAL_LINE(GPIOD, 18)
-#    define D19 PAL_LINE(GPIOD, 19)
-#    define D20 PAL_LINE(GPIOD, 20)
-#    define D21 PAL_LINE(GPIOD, 21)
-#    define D22 PAL_LINE(GPIOD, 22)
-#    define D23 PAL_LINE(GPIOD, 23)
-#    define D24 PAL_LINE(GPIOD, 24)
-#    define D25 PAL_LINE(GPIOD, 25)
-#    define D26 PAL_LINE(GPIOD, 26)
-#    define D27 PAL_LINE(GPIOD, 27)
-#    define D28 PAL_LINE(GPIOD, 28)
-#    define D29 PAL_LINE(GPIOD, 29)
-#    define D30 PAL_LINE(GPIOD, 30)
-#    define D31 PAL_LINE(GPIOD, 31)
-#    define D32 PAL_LINE(GPIOD, 32)
-#    define E0 PAL_LINE(GPIOE, 0)
-#    define E1 PAL_LINE(GPIOE, 1)
-#    define E2 PAL_LINE(GPIOE, 2)
-#    define E3 PAL_LINE(GPIOE, 3)
-#    define E4 PAL_LINE(GPIOE, 4)
-#    define E5 PAL_LINE(GPIOE, 5)
-#    define E6 PAL_LINE(GPIOE, 6)
-#    define E7 PAL_LINE(GPIOE, 7)
-#    define E8 PAL_LINE(GPIOE, 8)
-#    define E9 PAL_LINE(GPIOE, 9)
-#    define E10 PAL_LINE(GPIOE, 10)
-#    define E11 PAL_LINE(GPIOE, 11)
-#    define E12 PAL_LINE(GPIOE, 12)
-#    define E13 PAL_LINE(GPIOE, 13)
-#    define E14 PAL_LINE(GPIOE, 14)
-#    define E15 PAL_LINE(GPIOE, 15)
-#    define E16 PAL_LINE(GPIOE, 16)
-#    define E17 PAL_LINE(GPIOE, 17)
-#    define E18 PAL_LINE(GPIOE, 18)
-#    define E19 PAL_LINE(GPIOE, 19)
-#    define E20 PAL_LINE(GPIOE, 20)
-#    define E21 PAL_LINE(GPIOE, 21)
-#    define E22 PAL_LINE(GPIOE, 22)
-#    define E23 PAL_LINE(GPIOE, 23)
-#    define E24 PAL_LINE(GPIOE, 24)
-#    define E25 PAL_LINE(GPIOE, 25)
-#    define E26 PAL_LINE(GPIOE, 26)
-#    define E27 PAL_LINE(GPIOE, 27)
-#    define E28 PAL_LINE(GPIOE, 28)
-#    define E29 PAL_LINE(GPIOE, 29)
-#    define E30 PAL_LINE(GPIOE, 30)
-#    define E31 PAL_LINE(GPIOE, 31)
-#    define E32 PAL_LINE(GPIOE, 32)
-#    define F0 PAL_LINE(GPIOF, 0)
-#    define F1 PAL_LINE(GPIOF, 1)
-#    define F2 PAL_LINE(GPIOF, 2)
-#    define F3 PAL_LINE(GPIOF, 3)
-#    define F4 PAL_LINE(GPIOF, 4)
-#    define F5 PAL_LINE(GPIOF, 5)
-#    define F6 PAL_LINE(GPIOF, 6)
-#    define F7 PAL_LINE(GPIOF, 7)
-#    define F8 PAL_LINE(GPIOF, 8)
-#    define F9 PAL_LINE(GPIOF, 9)
-#    define F10 PAL_LINE(GPIOF, 10)
-#    define F11 PAL_LINE(GPIOF, 11)
-#    define F12 PAL_LINE(GPIOF, 12)
-#    define F13 PAL_LINE(GPIOF, 13)
-#    define F14 PAL_LINE(GPIOF, 14)
-#    define F15 PAL_LINE(GPIOF, 15)
-#    define G0 PAL_LINE(GPIOG, 0)
-#    define G1 PAL_LINE(GPIOG, 1)
-#    define G2 PAL_LINE(GPIOG, 2)
-#    define G3 PAL_LINE(GPIOG, 3)
-#    define G4 PAL_LINE(GPIOG, 4)
-#    define G5 PAL_LINE(GPIOG, 5)
-#    define G6 PAL_LINE(GPIOG, 6)
-#    define G7 PAL_LINE(GPIOG, 7)
-#    define G8 PAL_LINE(GPIOG, 8)
-#    define G9 PAL_LINE(GPIOG, 9)
-#    define G10 PAL_LINE(GPIOG, 10)
-#    define G11 PAL_LINE(GPIOG, 11)
-#    define G12 PAL_LINE(GPIOG, 12)
-#    define G13 PAL_LINE(GPIOG, 13)
-#    define G14 PAL_LINE(GPIOG, 14)
-#    define G15 PAL_LINE(GPIOG, 15)
-#    define H0 PAL_LINE(GPIOH, 0)
-#    define H1 PAL_LINE(GPIOH, 1)
-#    define H2 PAL_LINE(GPIOH, 2)
-#    define H3 PAL_LINE(GPIOH, 3)
-#    define H4 PAL_LINE(GPIOH, 4)
-#    define H5 PAL_LINE(GPIOH, 5)
-#    define H6 PAL_LINE(GPIOH, 6)
-#    define H7 PAL_LINE(GPIOH, 7)
-#    define H8 PAL_LINE(GPIOH, 8)
-#    define H9 PAL_LINE(GPIOH, 9)
-#    define H10 PAL_LINE(GPIOH, 10)
-#    define H11 PAL_LINE(GPIOH, 11)
-#    define H12 PAL_LINE(GPIOH, 12)
-#    define H13 PAL_LINE(GPIOH, 13)
-#    define H14 PAL_LINE(GPIOH, 14)
-#    define H15 PAL_LINE(GPIOH, 15)
-#    define I0 PAL_LINE(GPIOI, 0)
-#    define I1 PAL_LINE(GPIOI, 1)
-#    define I2 PAL_LINE(GPIOI, 2)
-#    define I3 PAL_LINE(GPIOI, 3)
-#    define I4 PAL_LINE(GPIOI, 4)
-#    define I5 PAL_LINE(GPIOI, 5)
-#    define I6 PAL_LINE(GPIOI, 6)
-#    define I7 PAL_LINE(GPIOI, 7)
-#    define I8 PAL_LINE(GPIOI, 8)
-#    define I9 PAL_LINE(GPIOI, 9)
-#    define I10 PAL_LINE(GPIOI, 10)
-#    define I11 PAL_LINE(GPIOI, 11)
-#    define I12 PAL_LINE(GPIOI, 12)
-#    define I13 PAL_LINE(GPIOI, 13)
-#    define I14 PAL_LINE(GPIOI, 14)
-#    define I15 PAL_LINE(GPIOI, 15)
-#    define J0 PAL_LINE(GPIOJ, 0)
-#    define J1 PAL_LINE(GPIOJ, 1)
-#    define J2 PAL_LINE(GPIOJ, 2)
-#    define J3 PAL_LINE(GPIOJ, 3)
-#    define J4 PAL_LINE(GPIOJ, 4)
-#    define J5 PAL_LINE(GPIOJ, 5)
-#    define J6 PAL_LINE(GPIOJ, 6)
-#    define J7 PAL_LINE(GPIOJ, 7)
-#    define J8 PAL_LINE(GPIOJ, 8)
-#    define J9 PAL_LINE(GPIOJ, 9)
-#    define J10 PAL_LINE(GPIOJ, 10)
-#    define J11 PAL_LINE(GPIOJ, 11)
-#    define J12 PAL_LINE(GPIOJ, 12)
-#    define J13 PAL_LINE(GPIOJ, 13)
-#    define J14 PAL_LINE(GPIOJ, 14)
-#    define J15 PAL_LINE(GPIOJ, 15)
-// Keyboards can `#define KEYBOARD_REQUIRES_GPIOK` if they need to access GPIO-K pins. These conflict with a whole
-// bunch of layout definitions, so it's intentionally left out unless absolutely required -- in that case, the
-// keyboard designer should use a different symbol when defining their layout macros.
-#    ifdef KEYBOARD_REQUIRES_GPIOK
-#        define K0 PAL_LINE(GPIOK, 0)
-#        define K1 PAL_LINE(GPIOK, 1)
-#        define K2 PAL_LINE(GPIOK, 2)
-#        define K3 PAL_LINE(GPIOK, 3)
-#        define K4 PAL_LINE(GPIOK, 4)
-#        define K5 PAL_LINE(GPIOK, 5)
-#        define K6 PAL_LINE(GPIOK, 6)
-#        define K7 PAL_LINE(GPIOK, 7)
-#        define K8 PAL_LINE(GPIOK, 8)
-#        define K9 PAL_LINE(GPIOK, 9)
-#        define K10 PAL_LINE(GPIOK, 10)
-#        define K11 PAL_LINE(GPIOK, 11)
-#        define K12 PAL_LINE(GPIOK, 12)
-#        define K13 PAL_LINE(GPIOK, 13)
-#        define K14 PAL_LINE(GPIOK, 14)
-#        define K15 PAL_LINE(GPIOK, 15)
-#    endif
-#endif
diff --git a/platforms/chibios/platform.mk b/platforms/chibios/platform.mk
index 6fd1fd83f5..21751f23fd 100644
--- a/platforms/chibios/platform.mk
+++ b/platforms/chibios/platform.mk
@@ -39,7 +39,6 @@ ifeq ($(strip $(MCU)), risc-v)
     STARTUP_MK = $(CHIBIOS_CONTRIB)/os/common/startup/RISCV-ECLIC/compilers/GCC/mk/startup_$(MCU_STARTUP).mk
     PORT_V = $(CHIBIOS_CONTRIB)/os/common/ports/RISCV-ECLIC/compilers/GCC/mk/port.mk
     RULESPATH = $(CHIBIOS_CONTRIB)/os/common/startup/RISCV-ECLIC/compilers/GCC
-    PLATFORM_MK = $(CHIBIOS_CONTRIB)/os/hal/ports/GD/GD32VF103/platform.mk
 else
     # ARM Support
     CHIBIOS_PORT ?=
@@ -82,10 +81,15 @@ ifeq ("$(PLATFORM_NAME)","")
     PLATFORM_NAME = platform
 endif
 
+# If no MCU port name was specified, use the family instead
+ifeq ("$(MCU_PORT_NAME)","")
+    MCU_PORT_NAME = $(MCU_FAMILY)
+endif
+
 ifeq ("$(wildcard $(PLATFORM_MK))","")
-    PLATFORM_MK = $(CHIBIOS)/os/hal/ports/$(MCU_FAMILY)/$(MCU_SERIES)/$(PLATFORM_NAME).mk
+    PLATFORM_MK = $(CHIBIOS)/os/hal/ports/$(MCU_PORT_NAME)/$(MCU_SERIES)/$(PLATFORM_NAME).mk
     ifeq ("$(wildcard $(PLATFORM_MK))","")
-        PLATFORM_MK = $(CHIBIOS_CONTRIB)/os/hal/ports/$(MCU_FAMILY)/$(MCU_SERIES)/$(PLATFORM_NAME).mk
+        PLATFORM_MK = $(CHIBIOS_CONTRIB)/os/hal/ports/$(MCU_PORT_NAME)/$(MCU_SERIES)/$(PLATFORM_NAME).mk
     endif
 endif
 
@@ -261,7 +265,8 @@ PLATFORM_SRC = \
         $(STREAMSSRC) \
         $(CHIBIOS)/os/various/syscalls.c \
         $(PLATFORM_COMMON_DIR)/syscall-fallbacks.c \
-        $(PLATFORM_COMMON_DIR)/wait.c
+        $(PLATFORM_COMMON_DIR)/wait.c \
+        $(PLATFORM_COMMON_DIR)/synchronization_util.c
 
 # Ensure the ASM files are not subjected to LTO -- it'll strip out interrupt handlers otherwise.
 QUANTUM_LIB_SRC += $(STARTUPASM) $(PORTASM) $(OSALASM) $(PLATFORMASM)
@@ -416,6 +421,9 @@ LDFLAGS  += $(SHARED_LDFLAGS) $(SHARED_LDSYMBOLS) $(TOOLCHAIN_LDFLAGS) $(TOOLCHA
 # Tell QMK that we are hosting it on ChibiOS.
 OPT_DEFS += -DPROTOCOL_CHIBIOS
 
+# ChibiOS supports synchronization primitives like a Mutex
+OPT_DEFS += -DPLATFORM_SUPPORTS_SYNCHRONIZATION
+
 # Workaround to stop ChibiOS from complaining about new GCC -- it's been fixed for 7/8/9 already
 OPT_DEFS += -DPORT_IGNORE_GCC_VERSION_CHECK=1
 
diff --git a/platforms/chibios/synchronization_util.c b/platforms/chibios/synchronization_util.c
new file mode 100644
index 0000000000..bc4a4e621f
--- /dev/null
+++ b/platforms/chibios/synchronization_util.c
@@ -0,0 +1,26 @@
+// Copyright 2022 Stefan Kerkmann
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "synchronization_util.h"
+#include "ch.h"
+
+#if defined(SPLIT_KEYBOARD)
+static MUTEX_DECL(SPLIT_SHARED_MEMORY_MUTEX);
+
+/**
+ * @brief Acquire exclusive access to the split keyboard shared memory, by
+ * locking the mutex guarding it. If the mutex is already held, the calling
+ * thread will be suspended until the mutex currently owning thread releases the
+ * mutex again.
+ */
+void split_shared_memory_lock(void) {
+    chMtxLock(&SPLIT_SHARED_MEMORY_MUTEX);
+}
+
+/**
+ * @brief Release the split shared memory mutex that has been acquired before.
+ */
+void split_shared_memory_unlock(void) {
+    chMtxUnlock(&SPLIT_SHARED_MEMORY_MUTEX);
+}
+#endif
diff --git a/platforms/chibios/timer.c b/platforms/chibios/timer.c
index e3bdfdcc37..5e01ea6372 100644
--- a/platforms/chibios/timer.c
+++ b/platforms/chibios/timer.c
@@ -40,7 +40,7 @@ static virtual_timer_t update_timer;
 #    define UPDATE_INTERVAL (((sysinterval_t)1) << (CH_CFG_ST_RESOLUTION - 1))
 
 // VT callback function to keep the overflow bits of the system tick counter updated.
-static void update_fn(void *arg) {
+static void update_fn(struct ch_virtual_timer *timer, void *arg) {
     (void)arg;
     chSysLockFromISR();
     get_system_time_ticks();
diff --git a/platforms/chibios/wait.c b/platforms/chibios/wait.c
index 56fd6ffcec..88cb5e6d54 100644
--- a/platforms/chibios/wait.c
+++ b/platforms/chibios/wait.c
@@ -31,7 +31,7 @@ void wait_us(uint16_t duration) {
      * Only use this timer on the main thread;
      * other threads need to use their own timer.
      */
-    if (chThdGetSelfX() == &ch.mainthread && duration < (1ULL << (sizeof(gptcnt_t) * 8))) {
+    if (chThdGetSelfX() == &(currcore->mainthread) && duration < (1ULL << (sizeof(gptcnt_t) * 8))) {
         gptStart(&WAIT_US_TIMER, &gpt_cfg);
         gptPolledDelay(&WAIT_US_TIMER, duration);
     } else {
diff --git a/platforms/common.mk b/platforms/common.mk
index 2a1fc8d377..693bdc8cf0 100644
--- a/platforms/common.mk
+++ b/platforms/common.mk
@@ -2,6 +2,7 @@ PLATFORM_COMMON_DIR = $(PLATFORM_PATH)/$(PLATFORM_KEY)
 
 TMK_COMMON_SRC +=	\
 	$(PLATFORM_PATH)/suspend.c \
+	$(PLATFORM_COMMON_DIR)/hardware_id.c \
 	$(PLATFORM_COMMON_DIR)/platform.c \
 	$(PLATFORM_COMMON_DIR)/suspend.c \
 	$(PLATFORM_COMMON_DIR)/timer.c \
diff --git a/platforms/hardware_id.h b/platforms/hardware_id.h
new file mode 100644
index 0000000000..0c161863d6
--- /dev/null
+++ b/platforms/hardware_id.h
@@ -0,0 +1,18 @@
+// Copyright 2022 QMK
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#pragma once
+
+#include <stdint.h>
+
+/** \brief Storage for a hardware ID
+ *
+ * Ensure this is sized to cover all hardware scenarios
+ */
+typedef struct hardware_id_t {
+    uint32_t data[4];
+} hardware_id_t;
+
+/** \brief Query the devices "unique" ID
+ */
+hardware_id_t get_hardware_id(void);
diff --git a/platforms/pin_defs.h b/platforms/pin_defs.h
index ea730138f2..341fe89b6e 100644
--- a/platforms/pin_defs.h
+++ b/platforms/pin_defs.h
@@ -18,6 +18,6 @@
 // useful for direct pin mapping
 #define NO_PIN (pin_t)(~0)
 
-#if __has_include_next("pin_defs.h")
-#    include_next "pin_defs.h" /* Include the platforms pin_defs.h */
+#if __has_include("_pin_defs.h")
+#    include "_pin_defs.h" /* Include the platforms pin defs */
 #endif
diff --git a/platforms/synchronization_util.h b/platforms/synchronization_util.h
new file mode 100644
index 0000000000..3730f271db
--- /dev/null
+++ b/platforms/synchronization_util.h
@@ -0,0 +1,14 @@
+// Copyright 2022 Stefan Kerkmann
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#pragma once
+
+#if defined(PLATFORM_SUPPORTS_SYNCHRONIZATION)
+#    if defined(SPLIT_KEYBOARD)
+void split_shared_memory_lock(void);
+void split_shared_memory_unlock(void);
+#    endif
+#else
+inline void split_shared_memory_lock(void){};
+inline void split_shared_memory_unlock(void){};
+#endif
diff --git a/platforms/test/bootloaders/none.c b/platforms/test/bootloaders/none.c
index 5155d9ff04..e88a79ae05 100644
--- a/platforms/test/bootloaders/none.c
+++ b/platforms/test/bootloaders/none.c
@@ -17,3 +17,4 @@
 #include "bootloader.h"
 
 void bootloader_jump(void) {}
+void mcu_reset(void) {}
diff --git a/platforms/test/hardware_id.c b/platforms/test/hardware_id.c
new file mode 100644
index 0000000000..8b3b35a492
--- /dev/null
+++ b/platforms/test/hardware_id.c
@@ -0,0 +1,9 @@
+// Copyright 2022 QMK
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "hardware_id.h"
+
+hardware_id_t get_hardware_id(void) {
+    hardware_id_t id = {0};
+    return id;
+}