diff options
| author | JX <572673807@qq.com> | 2022-05-12 12:48:47 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-05-11 21:48:47 -0700 |
| commit | 4d1332b62c53282631aa8d24fee1105c6322352a (patch) | |
| tree | d8ab44cb46cee6f8a98b2a32a8db797dd57ef7f1 /keyboards/yandrstudio/zhou65/mcuconf.h | |
| parent | ffa1b37634418a4928e7d2b64cb08f31512dcedf (diff) | |
[Keyboard] Cleanup zhou65 and add nz64 keyboard (#17032)
Co-authored-by: Drashna Jaelre <drashna@live.com>
Diffstat (limited to 'keyboards/yandrstudio/zhou65/mcuconf.h')
| -rw-r--r-- | keyboards/yandrstudio/zhou65/mcuconf.h | 59 |
1 files changed, 5 insertions, 54 deletions
diff --git a/keyboards/yandrstudio/zhou65/mcuconf.h b/keyboards/yandrstudio/zhou65/mcuconf.h index 85376734f4..918717451c 100644 --- a/keyboards/yandrstudio/zhou65/mcuconf.h +++ b/keyboards/yandrstudio/zhou65/mcuconf.h @@ -1,4 +1,4 @@ -/* Copyright 2020 QMK +/* Copyright 2021 JasonRen(biu) * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,61 +18,12 @@ #include_next <mcuconf.h> -#undef STM32_NO_INIT -#undef STM32_HSI_ENABLED -#undef STM32_LSI_ENABLED -#undef STM32_HSE_ENABLED -#undef STM32_LSE_ENABLED -#undef STM32_CLOCK48_REQUIRED -#undef STM32_SW -#undef STM32_PLLSRC #undef STM32_PLLM_VALUE #undef STM32_PLLN_VALUE #undef STM32_PLLP_VALUE #undef STM32_PLLQ_VALUE -#undef STM32_HPRE -#undef STM32_PPRE1 -#undef STM32_PPRE2 -#undef STM32_RTCSEL -#undef STM32_RTCPRE_VALUE -#undef STM32_MCO1SEL -#undef STM32_MCO1PRE -#undef STM32_MCO2SEL -#undef STM32_MCO2PRE -#undef STM32_I2SSRC -#undef STM32_PLLI2SN_VALUE -#undef STM32_PLLI2SR_VALUE -#undef STM32_PVD_ENABLE -#undef STM32_PLS -#undef STM32_BKPRAM_ENABLE -#define STM32_NO_INIT FALSE -#define STM32_HSI_ENABLED TRUE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED FALSE -#define STM32_CLOCK48_REQUIRED TRUE -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLM_VALUE 8 -#define STM32_PLLN_VALUE 192 -#define STM32_PLLP_VALUE 4 -#define STM32_PLLQ_VALUE 4 -// AHB prescaler value. -#define STM32_HPRE STM32_HPRE_DIV1 -//APB1 prescaler value. -#define STM32_PPRE1 STM32_PPRE1_DIV4 -//APB2 prescaler value. -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_RTCSEL STM32_RTCSEL_LSI -#define STM32_RTCPRE_VALUE 8 -#define STM32_MCO1SEL STM32_MCO1SEL_HSI -#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 -#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK -#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 -#define STM32_I2SSRC STM32_I2SSRC_CKIN -#define STM32_PLLI2SN_VALUE 192 -#define STM32_PLLI2SR_VALUE 5 -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_BKPRAM_ENABLE FALSE +#define STM32_PLLM_VALUE (STM32_HSECLK/1000000) +#define STM32_PLLN_VALUE 192 +#define STM32_PLLP_VALUE 4 +#define STM32_PLLQ_VALUE 4 |