1 files changed, 51 insertions, 0 deletions
diff --git a/blink-t84/blink.c b/blink-t84/blink.c
new file mode 100644
index 0000000..08921c2
--- /dev/null
+++ b/blink-t84/blink.c
@@ -0,0 +1,51 @@
+#include <stdlib.h>
+#include <avr/power.h>
+#include <avr/io.h>
+#include <util/delay.h>
+
+void set_frequency(int frequency) {
+  int i = F_CPU / (2*8);
+  OCR0A = i/frequency;
+}
+
+int main(void) {
+  // Base clock: 8MHz.
+  clock_prescale_set(clock_div_8);
+
+  DDRA |= (1 << DDA4);
+  DDRA |= (1 << DDA7);  // OCR1A
+  DDRA |= (1 << DDA6);  // OCR0B
+  DDRB |= (1 << DDB2);  // OCR0A
+
+  // PORTB |= _BV(DDB2);
+
+  // PORTA |= (1 << DDA7);
+  // PORTA |= (1 << DDA6);
+
+  TCCR0A |= (1 << COM0A1) | (1 << COM0B1);  // set non-inverting mode
+  // TCCR0A |= (1 << WGM11) | (1 << WGM10);  // set 10bit phase corrected PWM Mode
+  TCCR0A |= (1 << WGM10);  // 8 bit PWM
+  TCCR0B |= (1 << CS01);  // prescaler
+
+  TCCR1A |= (1 << COM0A1);  // set non-inverting mode
+  // TCCR0A |= (1 << WGM11) | (1 << WGM10);  // set 10bit phase corrected PWM Mode
+  TCCR1A |= (1 << WGM10);  // 8 bit PWM
+  TCCR1B |= (1 << CS01);  // prescaler
+
+  uint32_t tick = 0;
+  while (1) {
+    tick += 1;
+    OCR0A = abs((tick % 511) - 255) * 0.2;  // green
+    OCR0B = abs(((tick + 127) % 511) - 255) * 0.2;  // yellow
+    OCR1A = abs(((tick + 255) % 511) - 255) * 0.1;  // blue
+    _delay_ms(10);
+
+    // set_frequency(tick % 50);
+    // _delay_ms(200);
+    // PORTA |= _BV(DDA4);
+    // _delay_ms(500);
+    // PORTA &= ~_BV(DDA4);
+    // _delay_ms(500);
+  }
+  return 0;
+}