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/*
** ###################################################################
** Version: rev. 1.0, 2014-05-14
** Build: b140515
**
** Abstract:
** Chip specific module features.
**
** Copyright: 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2014-05-14)
** Customer release.
**
** ###################################################################
*/
#if !defined(__FSL_FTM_FEATURES_H__)
#define __FSL_FTM_FEATURES_H__
#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \
defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || \
defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10)
/* @brief Bus clock is the source clock for the module. */
#define FSL_FEATURE_FTM_BUS_CLOCK (1)
/* @brief Number of channels. */
#define FSL_FEATURE_FTM_CHANNEL_COUNT (6)
#define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \
((x) == 0 ? (6) : \
((x) == 1 ? (2) : \
((x) == 2 ? (2) : (-1))))
/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
#define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1)
#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \
defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \
defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \
defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \
defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \
defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5)
/* @brief Bus clock is the source clock for the module. */
#define FSL_FEATURE_FTM_BUS_CLOCK (1)
/* @brief Number of channels. */
#define FSL_FEATURE_FTM_CHANNEL_COUNT (8)
#define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \
((x) == 0 ? (8) : \
((x) == 1 ? (2) : (-1)))
/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
#define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
#elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \
defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \
defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12)
/* @brief Bus clock is the source clock for the module. */
#define FSL_FEATURE_FTM_BUS_CLOCK (1)
/* @brief Number of channels. */
#define FSL_FEATURE_FTM_CHANNEL_COUNT (8)
#define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \
((x) == 0 ? (8) : \
((x) == 1 ? (2) : \
((x) == 2 ? (2) : (-1))))
/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
#define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1)
#elif defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MKV31F512VLH12) || \
defined(CPU_MKV31F512VLL12)
/* @brief Bus clock is the source clock for the module. */
#define FSL_FEATURE_FTM_BUS_CLOCK (1)
/* @brief Number of channels. */
#define FSL_FEATURE_FTM_CHANNEL_COUNT (8)
#define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \
((x) == 0 ? (8) : \
((x) == 1 ? (2) : \
((x) == 2 ? (2) : \
((x) == 3 ? (8) : (-1)))))
/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
#define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1)
#elif defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || \
defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || \
defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \
defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || \
defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || \
defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || \
defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \
defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
/* @brief Bus clock is the source clock for the module. */
#define FSL_FEATURE_FTM_BUS_CLOCK (1)
/* @brief Number of channels. */
#define FSL_FEATURE_FTM_CHANNEL_COUNT (8)
#define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \
((x) == 0 ? (8) : \
((x) == 1 ? (2) : \
((x) == 2 ? (2) : \
((x) == 3 ? (8) : (-1)))))
/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
#define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
#elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV45F128VLH15) || \
defined(CPU_MKV45F256VLH15) || defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F256VLH15)
/* @brief Bus clock is the source clock for the module. */
#define FSL_FEATURE_FTM_BUS_CLOCK (1)
/* @brief Number of channels. */
#define FSL_FEATURE_FTM_CHANNEL_COUNT (8)
#define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \
((x) == 0 ? (8) : \
((x) == 1 ? (2) : (-1)))
/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
#define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1)
#elif defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLL15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLL15) || \
defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLL15)
/* @brief Bus clock is the source clock for the module. */
#define FSL_FEATURE_FTM_BUS_CLOCK (1)
/* @brief Number of channels. */
#define FSL_FEATURE_FTM_CHANNEL_COUNT (8)
#define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \
((x) == 0 ? (8) : \
((x) == 1 ? (2) : \
((x) == 2 ? (8) : (-1))))
/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
#define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1)
#else
#error "No valid CPU defined!"
#endif
#endif /* __FSL_FTM_FEATURES_H__ */
/*******************************************************************************
* EOF
******************************************************************************/
|
