1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
|
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : scif_iobitmask.h
* $Rev: 1115 $
* $Date:: 2014-07-09 15:35:02 +0900#$
* Description : SCIF register define header
*******************************************************************************/
#ifndef SCIF_IOBITMASK_H
#define SCIF_IOBITMASK_H
/* ==== Mask values for IO registers ==== */
/* ---- SCIF0 ---- */
#define SCIF0_SCSMR_CKS (0x0003u)
#define SCIF0_SCSMR_STOP (0x0008u)
#define SCIF0_SCSMR_OE (0x0010u)
#define SCIF0_SCSMR_PE (0x0020u)
#define SCIF0_SCSMR_CHR (0x0040u)
#define SCIF0_SCSMR_CA (0x0080u)
#define SCIF0_SCBRR_D (0xFFu)
#define SCIF0_SCSCR_CKE (0x0003u)
#define SCIF0_SCSCR_REIE (0x0008u)
#define SCIF0_SCSCR_RE (0x0010u)
#define SCIF0_SCSCR_TE (0x0020u)
#define SCIF0_SCSCR_RIE (0x0040u)
#define SCIF0_SCSCR_TIE (0x0080u)
#define SCIF0_SCFTDR_D (0xFFu)
#define SCIF0_SCFSR_DR (0x0001u)
#define SCIF0_SCFSR_RDF (0x0002u)
#define SCIF0_SCFSR_PER (0x0004u)
#define SCIF0_SCFSR_FER (0x0008u)
#define SCIF0_SCFSR_BRK (0x0010u)
#define SCIF0_SCFSR_TDFE (0x0020u)
#define SCIF0_SCFSR_TEND (0x0040u)
#define SCIF0_SCFSR_ER (0x0080u)
#define SCIF0_SCFSR_FERN (0x0F00u)
#define SCIF0_SCFSR_PERN (0xF000u)
#define SCIF0_SCFRDR_D (0xFFu)
#define SCIF0_SCFCR_LOOP (0x0001u)
#define SCIF0_SCFCR_RFRST (0x0002u)
#define SCIF0_SCFCR_TFRST (0x0004u)
#define SCIF0_SCFCR_MCE (0x0008u)
#define SCIF0_SCFCR_TTRG (0x0030u)
#define SCIF0_SCFCR_RTRG (0x00C0u)
#define SCIF0_SCFCR_RSTRG (0x0700u)
#define SCIF0_SCFDR_R (0x001Fu)
#define SCIF0_SCFDR_T (0x1F00u)
#define SCIF0_SCSPTR_SPB2DT (0x0001u)
#define SCIF0_SCSPTR_SPB2IO (0x0002u)
#define SCIF0_SCSPTR_SCKDT (0x0004u)
#define SCIF0_SCSPTR_SCKIO (0x0008u)
#define SCIF0_SCSPTR_CTSDT (0x0010u)
#define SCIF0_SCSPTR_CTSIO (0x0020u)
#define SCIF0_SCSPTR_RTSDT (0x0040u)
#define SCIF0_SCSPTR_RTSIO (0x0080u)
#define SCIF0_SCLSR_ORER (0x0001u)
#define SCIF0_SCEMR_ABCS (0x0001u)
#define SCIF0_SCEMR_BGDM (0x0080u)
/* ---- SCIF1 ---- */
#define SCIF1_SCSMR_CKS (0x0003u)
#define SCIF1_SCSMR_STOP (0x0008u)
#define SCIF1_SCSMR_OE (0x0010u)
#define SCIF1_SCSMR_PE (0x0020u)
#define SCIF1_SCSMR_CHR (0x0040u)
#define SCIF1_SCSMR_CA (0x0080u)
#define SCIF1_SCBRR_D (0xFFu)
#define SCIF1_SCSCR_CKE (0x0003u)
#define SCIF1_SCSCR_REIE (0x0008u)
#define SCIF1_SCSCR_RE (0x0010u)
#define SCIF1_SCSCR_TE (0x0020u)
#define SCIF1_SCSCR_RIE (0x0040u)
#define SCIF1_SCSCR_TIE (0x0080u)
#define SCIF1_SCFTDR_D (0xFFu)
#define SCIF1_SCFSR_DR (0x0001u)
#define SCIF1_SCFSR_RDF (0x0002u)
#define SCIF1_SCFSR_PER (0x0004u)
#define SCIF1_SCFSR_FER (0x0008u)
#define SCIF1_SCFSR_BRK (0x0010u)
#define SCIF1_SCFSR_TDFE (0x0020u)
#define SCIF1_SCFSR_TEND (0x0040u)
#define SCIF1_SCFSR_ER (0x0080u)
#define SCIF1_SCFSR_FERN (0x0F00u)
#define SCIF1_SCFSR_PERN (0xF000u)
#define SCIF1_SCFRDR_D (0xFFu)
#define SCIF1_SCFCR_LOOP (0x0001u)
#define SCIF1_SCFCR_RFRST (0x0002u)
#define SCIF1_SCFCR_TFRST (0x0004u)
#define SCIF1_SCFCR_MCE (0x0008u)
#define SCIF1_SCFCR_TTRG (0x0030u)
#define SCIF1_SCFCR_RTRG (0x00C0u)
#define SCIF1_SCFCR_RSTRG (0x0700u)
#define SCIF1_SCFDR_R (0x001Fu)
#define SCIF1_SCFDR_T (0x1F00u)
#define SCIF1_SCSPTR_SPB2DT (0x0001u)
#define SCIF1_SCSPTR_SPB2IO (0x0002u)
#define SCIF1_SCSPTR_SCKDT (0x0004u)
#define SCIF1_SCSPTR_SCKIO (0x0008u)
#define SCIF1_SCSPTR_CTSDT (0x0010u)
#define SCIF1_SCSPTR_CTSIO (0x0020u)
#define SCIF1_SCSPTR_RTSDT (0x0040u)
#define SCIF1_SCSPTR_RTSIO (0x0080u)
#define SCIF1_SCLSR_ORER (0x0001u)
#define SCIF1_SCEMR_ABCS (0x0001u)
#define SCIF1_SCEMR_BGDM (0x0080u)
/* ---- SCIF2 ---- */
#define SCIF2_SCSMR_CKS (0x0003u)
#define SCIF2_SCSMR_STOP (0x0008u)
#define SCIF2_SCSMR_OE (0x0010u)
#define SCIF2_SCSMR_PE (0x0020u)
#define SCIF2_SCSMR_CHR (0x0040u)
#define SCIF2_SCSMR_CA (0x0080u)
#define SCIF2_SCBRR_D (0xFFu)
#define SCIF2_SCSCR_CKE (0x0003u)
#define SCIF2_SCSCR_REIE (0x0008u)
#define SCIF2_SCSCR_RE (0x0010u)
#define SCIF2_SCSCR_TE (0x0020u)
#define SCIF2_SCSCR_RIE (0x0040u)
#define SCIF2_SCSCR_TIE (0x0080u)
#define SCIF2_SCFTDR_D (0xFFu)
#define SCIF2_SCFSR_DR (0x0001u)
#define SCIF2_SCFSR_RDF (0x0002u)
#define SCIF2_SCFSR_PER (0x0004u)
#define SCIF2_SCFSR_FER (0x0008u)
#define SCIF2_SCFSR_BRK (0x0010u)
#define SCIF2_SCFSR_TDFE (0x0020u)
#define SCIF2_SCFSR_TEND (0x0040u)
#define SCIF2_SCFSR_ER (0x0080u)
#define SCIF2_SCFSR_FERN (0x0F00u)
#define SCIF2_SCFSR_PERN (0xF000u)
#define SCIF2_SCFRDR_D (0xFFu)
#define SCIF2_SCFCR_LOOP (0x0001u)
#define SCIF2_SCFCR_RFRST (0x0002u)
#define SCIF2_SCFCR_TFRST (0x0004u)
#define SCIF2_SCFCR_MCE (0x0008u)
#define SCIF2_SCFCR_TTRG (0x0030u)
#define SCIF2_SCFCR_RTRG (0x00C0u)
#define SCIF2_SCFCR_RSTRG (0x0700u)
#define SCIF2_SCFDR_R (0x001Fu)
#define SCIF2_SCFDR_T (0x1F00u)
#define SCIF2_SCSPTR_SPB2DT (0x0001u)
#define SCIF2_SCSPTR_SPB2IO (0x0002u)
#define SCIF2_SCSPTR_SCKDT (0x0004u)
#define SCIF2_SCSPTR_SCKIO (0x0008u)
#define SCIF2_SCSPTR_CTSDT (0x0010u)
#define SCIF2_SCSPTR_CTSIO (0x0020u)
#define SCIF2_SCSPTR_RTSDT (0x0040u)
#define SCIF2_SCSPTR_RTSIO (0x0080u)
#define SCIF2_SCLSR_ORER (0x0001u)
#define SCIF2_SCEMR_ABCS (0x0001u)
#define SCIF2_SCEMR_BGDM (0x0080u)
/* ---- SCIF3 ---- */
#define SCIF3_SCSMR_CKS (0x0003u)
#define SCIF3_SCSMR_STOP (0x0008u)
#define SCIF3_SCSMR_OE (0x0010u)
#define SCIF3_SCSMR_PE (0x0020u)
#define SCIF3_SCSMR_CHR (0x0040u)
#define SCIF3_SCSMR_CA (0x0080u)
#define SCIF3_SCBRR_D (0xFFu)
#define SCIF3_SCSCR_CKE (0x0003u)
#define SCIF3_SCSCR_REIE (0x0008u)
#define SCIF3_SCSCR_RE (0x0010u)
#define SCIF3_SCSCR_TE (0x0020u)
#define SCIF3_SCSCR_RIE (0x0040u)
#define SCIF3_SCSCR_TIE (0x0080u)
#define SCIF3_SCFTDR_D (0xFFu)
#define SCIF3_SCFSR_DR (0x0001u)
#define SCIF3_SCFSR_RDF (0x0002u)
#define SCIF3_SCFSR_PER (0x0004u)
#define SCIF3_SCFSR_FER (0x0008u)
#define SCIF3_SCFSR_BRK (0x0010u)
#define SCIF3_SCFSR_TDFE (0x0020u)
#define SCIF3_SCFSR_TEND (0x0040u)
#define SCIF3_SCFSR_ER (0x0080u)
#define SCIF3_SCFSR_FERN (0x0F00u)
#define SCIF3_SCFSR_PERN (0xF000u)
#define SCIF3_SCFRDR_D (0xFFu)
#define SCIF3_SCFCR_LOOP (0x0001u)
#define SCIF3_SCFCR_RFRST (0x0002u)
#define SCIF3_SCFCR_TFRST (0x0004u)
#define SCIF3_SCFCR_MCE (0x0008u)
#define SCIF3_SCFCR_TTRG (0x0030u)
#define SCIF3_SCFCR_RTRG (0x00C0u)
#define SCIF3_SCFCR_RSTRG (0x0700u)
#define SCIF3_SCFDR_R (0x001Fu)
#define SCIF3_SCFDR_T (0x1F00u)
#define SCIF3_SCSPTR_SPB2DT (0x0001u)
#define SCIF3_SCSPTR_SPB2IO (0x0002u)
#define SCIF3_SCSPTR_SCKDT (0x0004u)
#define SCIF3_SCSPTR_SCKIO (0x0008u)
#define SCIF3_SCSPTR_CTSDT (0x0010u)
#define SCIF3_SCSPTR_CTSIO (0x0020u)
#define SCIF3_SCSPTR_RTSDT (0x0040u)
#define SCIF3_SCSPTR_RTSIO (0x0080u)
#define SCIF3_SCLSR_ORER (0x0001u)
#define SCIF3_SCEMR_ABCS (0x0001u)
#define SCIF3_SCEMR_BGDM (0x0080u)
/* ---- SCIF4 ---- */
#define SCIF4_SCSMR_CKS (0x0003u)
#define SCIF4_SCSMR_STOP (0x0008u)
#define SCIF4_SCSMR_OE (0x0010u)
#define SCIF4_SCSMR_PE (0x0020u)
#define SCIF4_SCSMR_CHR (0x0040u)
#define SCIF4_SCSMR_CA (0x0080u)
#define SCIF4_SCBRR_D (0xFFu)
#define SCIF4_SCSCR_CKE (0x0003u)
#define SCIF4_SCSCR_REIE (0x0008u)
#define SCIF4_SCSCR_RE (0x0010u)
#define SCIF4_SCSCR_TE (0x0020u)
#define SCIF4_SCSCR_RIE (0x0040u)
#define SCIF4_SCSCR_TIE (0x0080u)
#define SCIF4_SCFTDR_D (0xFFu)
#define SCIF4_SCFSR_DR (0x0001u)
#define SCIF4_SCFSR_RDF (0x0002u)
#define SCIF4_SCFSR_PER (0x0004u)
#define SCIF4_SCFSR_FER (0x0008u)
#define SCIF4_SCFSR_BRK (0x0010u)
#define SCIF4_SCFSR_TDFE (0x0020u)
#define SCIF4_SCFSR_TEND (0x0040u)
#define SCIF4_SCFSR_ER (0x0080u)
#define SCIF4_SCFSR_FERN (0x0F00u)
#define SCIF4_SCFSR_PERN (0xF000u)
#define SCIF4_SCFRDR_D (0xFFu)
#define SCIF4_SCFCR_LOOP (0x0001u)
#define SCIF4_SCFCR_RFRST (0x0002u)
#define SCIF4_SCFCR_TFRST (0x0004u)
#define SCIF4_SCFCR_MCE (0x0008u)
#define SCIF4_SCFCR_TTRG (0x0030u)
#define SCIF4_SCFCR_RTRG (0x00C0u)
#define SCIF4_SCFCR_RSTRG (0x0700u)
#define SCIF4_SCFDR_R (0x001Fu)
#define SCIF4_SCFDR_T (0x1F00u)
#define SCIF4_SCSPTR_SPB2DT (0x0001u)
#define SCIF4_SCSPTR_SPB2IO (0x0002u)
#define SCIF4_SCSPTR_SCKDT (0x0004u)
#define SCIF4_SCSPTR_SCKIO (0x0008u)
#define SCIF4_SCSPTR_CTSDT (0x0010u)
#define SCIF4_SCSPTR_CTSIO (0x0020u)
#define SCIF4_SCSPTR_RTSDT (0x0040u)
#define SCIF4_SCSPTR_RTSIO (0x0080u)
#define SCIF4_SCLSR_ORER (0x0001u)
#define SCIF4_SCEMR_ABCS (0x0001u)
#define SCIF4_SCEMR_BGDM (0x0080u)
/* ---- SCIF5 ---- */
#define SCIF5_SCSMR_CKS (0x0003u)
#define SCIF5_SCSMR_STOP (0x0008u)
#define SCIF5_SCSMR_OE (0x0010u)
#define SCIF5_SCSMR_PE (0x0020u)
#define SCIF5_SCSMR_CHR (0x0040u)
#define SCIF5_SCSMR_CA (0x0080u)
#define SCIF5_SCBRR_D (0xFFu)
#define SCIF5_SCSCR_CKE (0x0003u)
#define SCIF5_SCSCR_REIE (0x0008u)
#define SCIF5_SCSCR_RE (0x0010u)
#define SCIF5_SCSCR_TE (0x0020u)
#define SCIF5_SCSCR_RIE (0x0040u)
#define SCIF5_SCSCR_TIE (0x0080u)
#define SCIF5_SCFTDR_D (0xFFu)
#define SCIF5_SCFSR_DR (0x0001u)
#define SCIF5_SCFSR_RDF (0x0002u)
#define SCIF5_SCFSR_PER (0x0004u)
#define SCIF5_SCFSR_FER (0x0008u)
#define SCIF5_SCFSR_BRK (0x0010u)
#define SCIF5_SCFSR_TDFE (0x0020u)
#define SCIF5_SCFSR_TEND (0x0040u)
#define SCIF5_SCFSR_ER (0x0080u)
#define SCIF5_SCFSR_FERN (0x0F00u)
#define SCIF5_SCFSR_PERN (0xF000u)
#define SCIF5_SCFRDR_D (0xFFu)
#define SCIF5_SCFCR_LOOP (0x0001u)
#define SCIF5_SCFCR_RFRST (0x0002u)
#define SCIF5_SCFCR_TFRST (0x0004u)
#define SCIF5_SCFCR_MCE (0x0008u)
#define SCIF5_SCFCR_TTRG (0x0030u)
#define SCIF5_SCFCR_RTRG (0x00C0u)
#define SCIF5_SCFCR_RSTRG (0x0700u)
#define SCIF5_SCFDR_R (0x001Fu)
#define SCIF5_SCFDR_T (0x1F00u)
#define SCIF5_SCSPTR_SPB2DT (0x0001u)
#define SCIF5_SCSPTR_SPB2IO (0x0002u)
#define SCIF5_SCSPTR_SCKDT (0x0004u)
#define SCIF5_SCSPTR_SCKIO (0x0008u)
#define SCIF5_SCSPTR_CTSDT (0x0010u)
#define SCIF5_SCSPTR_CTSIO (0x0020u)
#define SCIF5_SCSPTR_RTSDT (0x0040u)
#define SCIF5_SCSPTR_RTSIO (0x0080u)
#define SCIF5_SCLSR_ORER (0x0001u)
#define SCIF5_SCEMR_ABCS (0x0001u)
#define SCIF5_SCEMR_BGDM (0x0080u)
/* ---- SCIF6 ---- */
#define SCIF6_SCSMR_CKS (0x0003u)
#define SCIF6_SCSMR_STOP (0x0008u)
#define SCIF6_SCSMR_OE (0x0010u)
#define SCIF6_SCSMR_PE (0x0020u)
#define SCIF6_SCSMR_CHR (0x0040u)
#define SCIF6_SCSMR_CA (0x0080u)
#define SCIF6_SCBRR_D (0xFFu)
#define SCIF6_SCSCR_CKE (0x0003u)
#define SCIF6_SCSCR_REIE (0x0008u)
#define SCIF6_SCSCR_RE (0x0010u)
#define SCIF6_SCSCR_TE (0x0020u)
#define SCIF6_SCSCR_RIE (0x0040u)
#define SCIF6_SCSCR_TIE (0x0080u)
#define SCIF6_SCFTDR_D (0xFFu)
#define SCIF6_SCFSR_DR (0x0001u)
#define SCIF6_SCFSR_RDF (0x0002u)
#define SCIF6_SCFSR_PER (0x0004u)
#define SCIF6_SCFSR_FER (0x0008u)
#define SCIF6_SCFSR_BRK (0x0010u)
#define SCIF6_SCFSR_TDFE (0x0020u)
#define SCIF6_SCFSR_TEND (0x0040u)
#define SCIF6_SCFSR_ER (0x0080u)
#define SCIF6_SCFSR_FERN (0x0F00u)
#define SCIF6_SCFSR_PERN (0xF000u)
#define SCIF6_SCFRDR_D (0xFFu)
#define SCIF6_SCFCR_LOOP (0x0001u)
#define SCIF6_SCFCR_RFRST (0x0002u)
#define SCIF6_SCFCR_TFRST (0x0004u)
#define SCIF6_SCFCR_MCE (0x0008u)
#define SCIF6_SCFCR_TTRG (0x0030u)
#define SCIF6_SCFCR_RTRG (0x00C0u)
#define SCIF6_SCFCR_RSTRG (0x0700u)
#define SCIF6_SCFDR_R (0x001Fu)
#define SCIF6_SCFDR_T (0x1F00u)
#define SCIF6_SCSPTR_SPB2DT (0x0001u)
#define SCIF6_SCSPTR_SPB2IO (0x0002u)
#define SCIF6_SCSPTR_SCKDT (0x0004u)
#define SCIF6_SCSPTR_SCKIO (0x0008u)
#define SCIF6_SCSPTR_CTSDT (0x0010u)
#define SCIF6_SCSPTR_CTSIO (0x0020u)
#define SCIF6_SCSPTR_RTSDT (0x0040u)
#define SCIF6_SCSPTR_RTSIO (0x0080u)
#define SCIF6_SCLSR_ORER (0x0001u)
#define SCIF6_SCEMR_ABCS (0x0001u)
#define SCIF6_SCEMR_BGDM (0x0080u)
/* ---- SCIF7 ---- */
#define SCIF7_SCSMR_CKS (0x0003u)
#define SCIF7_SCSMR_STOP (0x0008u)
#define SCIF7_SCSMR_OE (0x0010u)
#define SCIF7_SCSMR_PE (0x0020u)
#define SCIF7_SCSMR_CHR (0x0040u)
#define SCIF7_SCSMR_CA (0x0080u)
#define SCIF7_SCBRR_D (0xFFu)
#define SCIF7_SCSCR_CKE (0x0003u)
#define SCIF7_SCSCR_REIE (0x0008u)
#define SCIF7_SCSCR_RE (0x0010u)
#define SCIF7_SCSCR_TE (0x0020u)
#define SCIF7_SCSCR_RIE (0x0040u)
#define SCIF7_SCSCR_TIE (0x0080u)
#define SCIF7_SCFTDR_D (0xFFu)
#define SCIF7_SCFSR_DR (0x0001u)
#define SCIF7_SCFSR_RDF (0x0002u)
#define SCIF7_SCFSR_PER (0x0004u)
#define SCIF7_SCFSR_FER (0x0008u)
#define SCIF7_SCFSR_BRK (0x0010u)
#define SCIF7_SCFSR_TDFE (0x0020u)
#define SCIF7_SCFSR_TEND (0x0040u)
#define SCIF7_SCFSR_ER (0x0080u)
#define SCIF7_SCFSR_FERN (0x0F00u)
#define SCIF7_SCFSR_PERN (0xF000u)
#define SCIF7_SCFRDR_D (0xFFu)
#define SCIF7_SCFCR_LOOP (0x0001u)
#define SCIF7_SCFCR_RFRST (0x0002u)
#define SCIF7_SCFCR_TFRST (0x0004u)
#define SCIF7_SCFCR_MCE (0x0008u)
#define SCIF7_SCFCR_TTRG (0x0030u)
#define SCIF7_SCFCR_RTRG (0x00C0u)
#define SCIF7_SCFCR_RSTRG (0x0700u)
#define SCIF7_SCFDR_R (0x001Fu)
#define SCIF7_SCFDR_T (0x1F00u)
#define SCIF7_SCSPTR_SPB2DT (0x0001u)
#define SCIF7_SCSPTR_SPB2IO (0x0002u)
#define SCIF7_SCSPTR_SCKDT (0x0004u)
#define SCIF7_SCSPTR_SCKIO (0x0008u)
#define SCIF7_SCSPTR_CTSDT (0x0010u)
#define SCIF7_SCSPTR_CTSIO (0x0020u)
#define SCIF7_SCSPTR_RTSDT (0x0040u)
#define SCIF7_SCSPTR_RTSIO (0x0080u)
#define SCIF7_SCLSR_ORER (0x0001u)
#define SCIF7_SCEMR_ABCS (0x0001u)
#define SCIF7_SCEMR_BGDM (0x0080u)
/* ---- SCIFn ---- */
#define SCIFn_SCSMR_CKS (0x0003u)
#define SCIFn_SCSMR_STOP (0x0008u)
#define SCIFn_SCSMR_OE (0x0010u)
#define SCIFn_SCSMR_PE (0x0020u)
#define SCIFn_SCSMR_CHR (0x0040u)
#define SCIFn_SCSMR_CA (0x0080u)
#define SCIFn_SCBRR_D (0xFFu)
#define SCIFn_SCSCR_CKE (0x0003u)
#define SCIFn_SCSCR_REIE (0x0008u)
#define SCIFn_SCSCR_RE (0x0010u)
#define SCIFn_SCSCR_TE (0x0020u)
#define SCIFn_SCSCR_RIE (0x0040u)
#define SCIFn_SCSCR_TIE (0x0080u)
#define SCIFn_SCFTDR_D (0xFFu)
#define SCIFn_SCFSR_DR (0x0001u)
#define SCIFn_SCFSR_RDF (0x0002u)
#define SCIFn_SCFSR_PER (0x0004u)
#define SCIFn_SCFSR_FER (0x0008u)
#define SCIFn_SCFSR_BRK (0x0010u)
#define SCIFn_SCFSR_TDFE (0x0020u)
#define SCIFn_SCFSR_TEND (0x0040u)
#define SCIFn_SCFSR_ER (0x0080u)
#define SCIFn_SCFSR_FERN (0x0F00u)
#define SCIFn_SCFSR_PERN (0xF000u)
#define SCIFn_SCFRDR_D (0xFFu)
#define SCIFn_SCFCR_LOOP (0x0001u)
#define SCIFn_SCFCR_RFRST (0x0002u)
#define SCIFn_SCFCR_TFRST (0x0004u)
#define SCIFn_SCFCR_MCE (0x0008u)
#define SCIFn_SCFCR_TTRG (0x0030u)
#define SCIFn_SCFCR_RTRG (0x00C0u)
#define SCIFn_SCFCR_RSTRG (0x0700u)
#define SCIFn_SCFDR_R (0x001Fu)
#define SCIFn_SCFDR_T (0x1F00u)
#define SCIFn_SCSPTR_SPB2DT (0x0001u)
#define SCIFn_SCSPTR_SPB2IO (0x0002u)
#define SCIFn_SCSPTR_SCKDT (0x0004u)
#define SCIFn_SCSPTR_SCKIO (0x0008u)
#define SCIFn_SCSPTR_CTSDT (0x0010u)
#define SCIFn_SCSPTR_CTSIO (0x0020u)
#define SCIFn_SCSPTR_RTSDT (0x0040u)
#define SCIFn_SCSPTR_RTSIO (0x0080u)
#define SCIFn_SCLSR_ORER (0x0001u)
#define SCIFn_SCEMR_ABCS (0x0001u)
#define SCIFn_SCEMR_BGDM (0x0080u)
/* ==== Shift values for IO registers ==== */
/* ---- SCIF0 ---- */
#define SCIF0_SCSMR_CKS_SHIFT (0u)
#define SCIF0_SCSMR_STOP_SHIFT (3u)
#define SCIF0_SCSMR_OE_SHIFT (4u)
#define SCIF0_SCSMR_PE_SHIFT (5u)
#define SCIF0_SCSMR_CHR_SHIFT (6u)
#define SCIF0_SCSMR_CA_SHIFT (7u)
#define SCIF0_SCBRR_D_SHIFT (0u)
#define SCIF0_SCSCR_CKE_SHIFT (0u)
#define SCIF0_SCSCR_REIE_SHIFT (3u)
#define SCIF0_SCSCR_RE_SHIFT (4u)
#define SCIF0_SCSCR_TE_SHIFT (5u)
#define SCIF0_SCSCR_RIE_SHIFT (6u)
#define SCIF0_SCSCR_TIE_SHIFT (7u)
#define SCIF0_SCFTDR_D_SHIFT (0u)
#define SCIF0_SCFSR_DR_SHIFT (0u)
#define SCIF0_SCFSR_RDF_SHIFT (1u)
#define SCIF0_SCFSR_PER_SHIFT (2u)
#define SCIF0_SCFSR_FER_SHIFT (3u)
#define SCIF0_SCFSR_BRK_SHIFT (4u)
#define SCIF0_SCFSR_TDFE_SHIFT (5u)
#define SCIF0_SCFSR_TEND_SHIFT (6u)
#define SCIF0_SCFSR_ER_SHIFT (7u)
#define SCIF0_SCFSR_FERN_SHIFT (8u)
#define SCIF0_SCFSR_PERN_SHIFT (12u)
#define SCIF0_SCFRDR_D_SHIFT (0u)
#define SCIF0_SCFCR_LOOP_SHIFT (0u)
#define SCIF0_SCFCR_RFRST_SHIFT (1u)
#define SCIF0_SCFCR_TFRST_SHIFT (2u)
#define SCIF0_SCFCR_MCE_SHIFT (3u)
#define SCIF0_SCFCR_TTRG_SHIFT (4u)
#define SCIF0_SCFCR_RTRG_SHIFT (6u)
#define SCIF0_SCFCR_RSTRG_SHIFT (8u)
#define SCIF0_SCFDR_R_SHIFT (0u)
#define SCIF0_SCFDR_T_SHIFT (8u)
#define SCIF0_SCSPTR_SPB2DT_SHIFT (0u)
#define SCIF0_SCSPTR_SPB2IO_SHIFT (1u)
#define SCIF0_SCSPTR_SCKDT_SHIFT (2u)
#define SCIF0_SCSPTR_SCKIO_SHIFT (3u)
#define SCIF0_SCSPTR_CTSDT_SHIFT (4u)
#define SCIF0_SCSPTR_CTSIO_SHIFT (5u)
#define SCIF0_SCSPTR_RTSDT_SHIFT (6u)
#define SCIF0_SCSPTR_RTSIO_SHIFT (7u)
#define SCIF0_SCLSR_ORER_SHIFT (0u)
#define SCIF0_SCEMR_ABCS_SHIFT (0u)
#define SCIF0_SCEMR_BGDM_SHIFT (7u)
/* ---- SCIF1 ---- */
#define SCIF1_SCSMR_CKS_SHIFT (0u)
#define SCIF1_SCSMR_STOP_SHIFT (3u)
#define SCIF1_SCSMR_OE_SHIFT (4u)
#define SCIF1_SCSMR_PE_SHIFT (5u)
#define SCIF1_SCSMR_CHR_SHIFT (6u)
#define SCIF1_SCSMR_CA_SHIFT (7u)
#define SCIF1_SCBRR_D_SHIFT (0u)
#define SCIF1_SCSCR_CKE_SHIFT (0u)
#define SCIF1_SCSCR_REIE_SHIFT (3u)
#define SCIF1_SCSCR_RE_SHIFT (4u)
#define SCIF1_SCSCR_TE_SHIFT (5u)
#define SCIF1_SCSCR_RIE_SHIFT (6u)
#define SCIF1_SCSCR_TIE_SHIFT (7u)
#define SCIF1_SCFTDR_D_SHIFT (0u)
#define SCIF1_SCFSR_DR_SHIFT (0u)
#define SCIF1_SCFSR_RDF_SHIFT (1u)
#define SCIF1_SCFSR_PER_SHIFT (2u)
#define SCIF1_SCFSR_FER_SHIFT (3u)
#define SCIF1_SCFSR_BRK_SHIFT (4u)
#define SCIF1_SCFSR_TDFE_SHIFT (5u)
#define SCIF1_SCFSR_TEND_SHIFT (6u)
#define SCIF1_SCFSR_ER_SHIFT (7u)
#define SCIF1_SCFSR_FERN_SHIFT (8u)
#define SCIF1_SCFSR_PERN_SHIFT (12u)
#define SCIF1_SCFRDR_D_SHIFT (0u)
#define SCIF1_SCFCR_LOOP_SHIFT (0u)
#define SCIF1_SCFCR_RFRST_SHIFT (1u)
#define SCIF1_SCFCR_TFRST_SHIFT (2u)
#define SCIF1_SCFCR_MCE_SHIFT (3u)
#define SCIF1_SCFCR_TTRG_SHIFT (4u)
#define SCIF1_SCFCR_RTRG_SHIFT (6u)
#define SCIF1_SCFCR_RSTRG_SHIFT (8u)
#define SCIF1_SCFDR_R_SHIFT (0u)
#define SCIF1_SCFDR_T_SHIFT (8u)
#define SCIF1_SCSPTR_SPB2DT_SHIFT (0u)
#define SCIF1_SCSPTR_SPB2IO_SHIFT (1u)
#define SCIF1_SCSPTR_SCKDT_SHIFT (2u)
#define SCIF1_SCSPTR_SCKIO_SHIFT (3u)
#define SCIF1_SCSPTR_CTSDT_SHIFT (4u)
#define SCIF1_SCSPTR_CTSIO_SHIFT (5u)
#define SCIF1_SCSPTR_RTSDT_SHIFT (6u)
#define SCIF1_SCSPTR_RTSIO_SHIFT (7u)
#define SCIF1_SCLSR_ORER_SHIFT (0u)
#define SCIF1_SCEMR_ABCS_SHIFT (0u)
#define SCIF1_SCEMR_BGDM_SHIFT (7u)
/* ---- SCIF2 ---- */
#define SCIF2_SCSMR_CKS_SHIFT (0u)
#define SCIF2_SCSMR_STOP_SHIFT (3u)
#define SCIF2_SCSMR_OE_SHIFT (4u)
#define SCIF2_SCSMR_PE_SHIFT (5u)
#define SCIF2_SCSMR_CHR_SHIFT (6u)
#define SCIF2_SCSMR_CA_SHIFT (7u)
#define SCIF2_SCBRR_D_SHIFT (0u)
#define SCIF2_SCSCR_CKE_SHIFT (0u)
#define SCIF2_SCSCR_REIE_SHIFT (3u)
#define SCIF2_SCSCR_RE_SHIFT (4u)
#define SCIF2_SCSCR_TE_SHIFT (5u)
#define SCIF2_SCSCR_RIE_SHIFT (6u)
#define SCIF2_SCSCR_TIE_SHIFT (7u)
#define SCIF2_SCFTDR_D_SHIFT (0u)
#define SCIF2_SCFSR_DR_SHIFT (0u)
#define SCIF2_SCFSR_RDF_SHIFT (1u)
#define SCIF2_SCFSR_PER_SHIFT (2u)
#define SCIF2_SCFSR_FER_SHIFT (3u)
#define SCIF2_SCFSR_BRK_SHIFT (4u)
#define SCIF2_SCFSR_TDFE_SHIFT (5u)
#define SCIF2_SCFSR_TEND_SHIFT (6u)
#define SCIF2_SCFSR_ER_SHIFT (7u)
#define SCIF2_SCFSR_FERN_SHIFT (8u)
#define SCIF2_SCFSR_PERN_SHIFT (12u)
#define SCIF2_SCFRDR_D_SHIFT (0u)
#define SCIF2_SCFCR_LOOP_SHIFT (0u)
#define SCIF2_SCFCR_RFRST_SHIFT (1u)
#define SCIF2_SCFCR_TFRST_SHIFT (2u)
#define SCIF2_SCFCR_MCE_SHIFT (3u)
#define SCIF2_SCFCR_TTRG_SHIFT (4u)
#define SCIF2_SCFCR_RTRG_SHIFT (6u)
#define SCIF2_SCFCR_RSTRG_SHIFT (8u)
#define SCIF2_SCFDR_R_SHIFT (0u)
#define SCIF2_SCFDR_T_SHIFT (8u)
#define SCIF2_SCSPTR_SPB2DT_SHIFT (0u)
#define SCIF2_SCSPTR_SPB2IO_SHIFT (1u)
#define SCIF2_SCSPTR_SCKDT_SHIFT (2u)
#define SCIF2_SCSPTR_SCKIO_SHIFT (3u)
#define SCIF2_SCSPTR_CTSDT_SHIFT (4u)
#define SCIF2_SCSPTR_CTSIO_SHIFT (5u)
#define SCIF2_SCSPTR_RTSDT_SHIFT (6u)
#define SCIF2_SCSPTR_RTSIO_SHIFT (7u)
#define SCIF2_SCLSR_ORER_SHIFT (0u)
#define SCIF2_SCEMR_ABCS_SHIFT (0u)
#define SCIF2_SCEMR_BGDM_SHIFT (7u)
/* ---- SCIF3 ---- */
#define SCIF3_SCSMR_CKS_SHIFT (0u)
#define SCIF3_SCSMR_STOP_SHIFT (3u)
#define SCIF3_SCSMR_OE_SHIFT (4u)
#define SCIF3_SCSMR_PE_SHIFT (5u)
#define SCIF3_SCSMR_CHR_SHIFT (6u)
#define SCIF3_SCSMR_CA_SHIFT (7u)
#define SCIF3_SCBRR_D_SHIFT (0u)
#define SCIF3_SCSCR_CKE_SHIFT (0u)
#define SCIF3_SCSCR_REIE_SHIFT (3u)
#define SCIF3_SCSCR_RE_SHIFT (4u)
#define SCIF3_SCSCR_TE_SHIFT (5u)
#define SCIF3_SCSCR_RIE_SHIFT (6u)
#define SCIF3_SCSCR_TIE_SHIFT (7u)
#define SCIF3_SCFTDR_D_SHIFT (0u)
#define SCIF3_SCFSR_DR_SHIFT (0u)
#define SCIF3_SCFSR_RDF_SHIFT (1u)
#define SCIF3_SCFSR_PER_SHIFT (2u)
#define SCIF3_SCFSR_FER_SHIFT (3u)
#define SCIF3_SCFSR_BRK_SHIFT (4u)
#define SCIF3_SCFSR_TDFE_SHIFT (5u)
#define SCIF3_SCFSR_TEND_SHIFT (6u)
#define SCIF3_SCFSR_ER_SHIFT (7u)
#define SCIF3_SCFSR_FERN_SHIFT (8u)
#define SCIF3_SCFSR_PERN_SHIFT (12u)
#define SCIF3_SCFRDR_D_SHIFT (0u)
#define SCIF3_SCFCR_LOOP_SHIFT (0u)
#define SCIF3_SCFCR_RFRST_SHIFT (1u)
#define SCIF3_SCFCR_TFRST_SHIFT (2u)
#define SCIF3_SCFCR_MCE_SHIFT (3u)
#define SCIF3_SCFCR_TTRG_SHIFT (4u)
#define SCIF3_SCFCR_RTRG_SHIFT (6u)
#define SCIF3_SCFCR_RSTRG_SHIFT (8u)
#define SCIF3_SCFDR_R_SHIFT (0u)
#define SCIF3_SCFDR_T_SHIFT (8u)
#define SCIF3_SCSPTR_SPB2DT_SHIFT (0u)
#define SCIF3_SCSPTR_SPB2IO_SHIFT (1u)
#define SCIF3_SCSPTR_SCKDT_SHIFT (2u)
#define SCIF3_SCSPTR_SCKIO_SHIFT (3u)
#define SCIF3_SCSPTR_CTSDT_SHIFT (4u)
#define SCIF3_SCSPTR_CTSIO_SHIFT (5u)
#define SCIF3_SCSPTR_RTSDT_SHIFT (6u)
#define SCIF3_SCSPTR_RTSIO_SHIFT (7u)
#define SCIF3_SCLSR_ORER_SHIFT (0u)
#define SCIF3_SCEMR_ABCS_SHIFT (0u)
#define SCIF3_SCEMR_BGDM_SHIFT (7u)
/* ---- SCIF4 ---- */
#define SCIF4_SCSMR_CKS_SHIFT (0u)
#define SCIF4_SCSMR_STOP_SHIFT (3u)
#define SCIF4_SCSMR_OE_SHIFT (4u)
#define SCIF4_SCSMR_PE_SHIFT (5u)
#define SCIF4_SCSMR_CHR_SHIFT (6u)
#define SCIF4_SCSMR_CA_SHIFT (7u)
#define SCIF4_SCBRR_D_SHIFT (0u)
#define SCIF4_SCSCR_CKE_SHIFT (0u)
#define SCIF4_SCSCR_REIE_SHIFT (3u)
#define SCIF4_SCSCR_RE_SHIFT (4u)
#define SCIF4_SCSCR_TE_SHIFT (5u)
#define SCIF4_SCSCR_RIE_SHIFT (6u)
#define SCIF4_SCSCR_TIE_SHIFT (7u)
#define SCIF4_SCFTDR_D_SHIFT (0u)
#define SCIF4_SCFSR_DR_SHIFT (0u)
#define SCIF4_SCFSR_RDF_SHIFT (1u)
#define SCIF4_SCFSR_PER_SHIFT (2u)
#define SCIF4_SCFSR_FER_SHIFT (3u)
#define SCIF4_SCFSR_BRK_SHIFT (4u)
#define SCIF4_SCFSR_TDFE_SHIFT (5u)
#define SCIF4_SCFSR_TEND_SHIFT (6u)
#define SCIF4_SCFSR_ER_SHIFT (7u)
#define SCIF4_SCFSR_FERN_SHIFT (8u)
#define SCIF4_SCFSR_PERN_SHIFT (12u)
#define SCIF4_SCFRDR_D_SHIFT (0u)
#define SCIF4_SCFCR_LOOP_SHIFT (0u)
#define SCIF4_SCFCR_RFRST_SHIFT (1u)
#define SCIF4_SCFCR_TFRST_SHIFT (2u)
#define SCIF4_SCFCR_MCE_SHIFT (3u)
#define SCIF4_SCFCR_TTRG_SHIFT (4u)
#define SCIF4_SCFCR_RTRG_SHIFT (6u)
#define SCIF4_SCFCR_RSTRG_SHIFT (8u)
#define SCIF4_SCFDR_R_SHIFT (0u)
#define SCIF4_SCFDR_T_SHIFT (8u)
#define SCIF4_SCSPTR_SPB2DT_SHIFT (0u)
#define SCIF4_SCSPTR_SPB2IO_SHIFT (1u)
#define SCIF4_SCSPTR_SCKDT_SHIFT (2u)
#define SCIF4_SCSPTR_SCKIO_SHIFT (3u)
#define SCIF4_SCSPTR_CTSDT_SHIFT (4u)
#define SCIF4_SCSPTR_CTSIO_SHIFT (5u)
#define SCIF4_SCSPTR_RTSDT_SHIFT (6u)
#define SCIF4_SCSPTR_RTSIO_SHIFT (7u)
#define SCIF4_SCLSR_ORER_SHIFT (0u)
#define SCIF4_SCEMR_ABCS_SHIFT (0u)
#define SCIF4_SCEMR_BGDM_SHIFT (7u)
/* ---- SCIF5 ---- */
#define SCIF5_SCSMR_CKS_SHIFT (0u)
#define SCIF5_SCSMR_STOP_SHIFT (3u)
#define SCIF5_SCSMR_OE_SHIFT (4u)
#define SCIF5_SCSMR_PE_SHIFT (5u)
#define SCIF5_SCSMR_CHR_SHIFT (6u)
#define SCIF5_SCSMR_CA_SHIFT (7u)
#define SCIF5_SCBRR_D_SHIFT (0u)
#define SCIF5_SCSCR_CKE_SHIFT (0u)
#define SCIF5_SCSCR_REIE_SHIFT (3u)
#define SCIF5_SCSCR_RE_SHIFT (4u)
#define SCIF5_SCSCR_TE_SHIFT (5u)
#define SCIF5_SCSCR_RIE_SHIFT (6u)
#define SCIF5_SCSCR_TIE_SHIFT (7u)
#define SCIF5_SCFTDR_D_SHIFT (0u)
#define SCIF5_SCFSR_DR_SHIFT (0u)
#define SCIF5_SCFSR_RDF_SHIFT (1u)
#define SCIF5_SCFSR_PER_SHIFT (2u)
#define SCIF5_SCFSR_FER_SHIFT (3u)
#define SCIF5_SCFSR_BRK_SHIFT (4u)
#define SCIF5_SCFSR_TDFE_SHIFT (5u)
#define SCIF5_SCFSR_TEND_SHIFT (6u)
#define SCIF5_SCFSR_ER_SHIFT (7u)
#define SCIF5_SCFSR_FERN_SHIFT (8u)
#define SCIF5_SCFSR_PERN_SHIFT (12u)
#define SCIF5_SCFRDR_D_SHIFT (0u)
#define SCIF5_SCFCR_LOOP_SHIFT (0u)
#define SCIF5_SCFCR_RFRST_SHIFT (1u)
#define SCIF5_SCFCR_TFRST_SHIFT (2u)
#define SCIF5_SCFCR_MCE_SHIFT (3u)
#define SCIF5_SCFCR_TTRG_SHIFT (4u)
#define SCIF5_SCFCR_RTRG_SHIFT (6u)
#define SCIF5_SCFCR_RSTRG_SHIFT (8u)
#define SCIF5_SCFDR_R_SHIFT (0u)
#define SCIF5_SCFDR_T_SHIFT (8u)
#define SCIF5_SCSPTR_SPB2DT_SHIFT (0u)
#define SCIF5_SCSPTR_SPB2IO_SHIFT (1u)
#define SCIF5_SCSPTR_SCKDT_SHIFT (2u)
#define SCIF5_SCSPTR_SCKIO_SHIFT (3u)
#define SCIF5_SCSPTR_CTSDT_SHIFT (4u)
#define SCIF5_SCSPTR_CTSIO_SHIFT (5u)
#define SCIF5_SCSPTR_RTSDT_SHIFT (6u)
#define SCIF5_SCSPTR_RTSIO_SHIFT (7u)
#define SCIF5_SCLSR_ORER_SHIFT (0u)
#define SCIF5_SCEMR_ABCS_SHIFT (0u)
#define SCIF5_SCEMR_BGDM_SHIFT (7u)
/* ---- SCIF6 ---- */
#define SCIF6_SCSMR_CKS_SHIFT (0u)
#define SCIF6_SCSMR_STOP_SHIFT (3u)
#define SCIF6_SCSMR_OE_SHIFT (4u)
#define SCIF6_SCSMR_PE_SHIFT (5u)
#define SCIF6_SCSMR_CHR_SHIFT (6u)
#define SCIF6_SCSMR_CA_SHIFT (7u)
#define SCIF6_SCBRR_D_SHIFT (0u)
#define SCIF6_SCSCR_CKE_SHIFT (0u)
#define SCIF6_SCSCR_REIE_SHIFT (3u)
#define SCIF6_SCSCR_RE_SHIFT (4u)
#define SCIF6_SCSCR_TE_SHIFT (5u)
#define SCIF6_SCSCR_RIE_SHIFT (6u)
#define SCIF6_SCSCR_TIE_SHIFT (7u)
#define SCIF6_SCFTDR_D_SHIFT (0u)
#define SCIF6_SCFSR_DR_SHIFT (0u)
#define SCIF6_SCFSR_RDF_SHIFT (1u)
#define SCIF6_SCFSR_PER_SHIFT (2u)
#define SCIF6_SCFSR_FER_SHIFT (3u)
#define SCIF6_SCFSR_BRK_SHIFT (4u)
#define SCIF6_SCFSR_TDFE_SHIFT (5u)
#define SCIF6_SCFSR_TEND_SHIFT (6u)
#define SCIF6_SCFSR_ER_SHIFT (7u)
#define SCIF6_SCFSR_FERN_SHIFT (8u)
#define SCIF6_SCFSR_PERN_SHIFT (12u)
#define SCIF6_SCFRDR_D_SHIFT (0u)
#define SCIF6_SCFCR_LOOP_SHIFT (0u)
#define SCIF6_SCFCR_RFRST_SHIFT (1u)
#define SCIF6_SCFCR_TFRST_SHIFT (2u)
#define SCIF6_SCFCR_MCE_SHIFT (3u)
#define SCIF6_SCFCR_TTRG_SHIFT (4u)
#define SCIF6_SCFCR_RTRG_SHIFT (6u)
#define SCIF6_SCFCR_RSTRG_SHIFT (8u)
#define SCIF6_SCFDR_R_SHIFT (0u)
#define SCIF6_SCFDR_T_SHIFT (8u)
#define SCIF6_SCSPTR_SPB2DT_SHIFT (0u)
#define SCIF6_SCSPTR_SPB2IO_SHIFT (1u)
#define SCIF6_SCSPTR_SCKDT_SHIFT (2u)
#define SCIF6_SCSPTR_SCKIO_SHIFT (3u)
#define SCIF6_SCSPTR_CTSDT_SHIFT (4u)
#define SCIF6_SCSPTR_CTSIO_SHIFT (5u)
#define SCIF6_SCSPTR_RTSDT_SHIFT (6u)
#define SCIF6_SCSPTR_RTSIO_SHIFT (7u)
#define SCIF6_SCLSR_ORER_SHIFT (0u)
#define SCIF6_SCEMR_ABCS_SHIFT (0u)
#define SCIF6_SCEMR_BGDM_SHIFT (7u)
/* ---- SCIF7 ---- */
#define SCIF7_SCSMR_CKS_SHIFT (0u)
#define SCIF7_SCSMR_STOP_SHIFT (3u)
#define SCIF7_SCSMR_OE_SHIFT (4u)
#define SCIF7_SCSMR_PE_SHIFT (5u)
#define SCIF7_SCSMR_CHR_SHIFT (6u)
#define SCIF7_SCSMR_CA_SHIFT (7u)
#define SCIF7_SCBRR_D_SHIFT (0u)
#define SCIF7_SCSCR_CKE_SHIFT (0u)
#define SCIF7_SCSCR_REIE_SHIFT (3u)
#define SCIF7_SCSCR_RE_SHIFT (4u)
#define SCIF7_SCSCR_TE_SHIFT (5u)
#define SCIF7_SCSCR_RIE_SHIFT (6u)
#define SCIF7_SCSCR_TIE_SHIFT (7u)
#define SCIF7_SCFTDR_D_SHIFT (0u)
#define SCIF7_SCFSR_DR_SHIFT (0u)
#define SCIF7_SCFSR_RDF_SHIFT (1u)
#define SCIF7_SCFSR_PER_SHIFT (2u)
#define SCIF7_SCFSR_FER_SHIFT (3u)
#define SCIF7_SCFSR_BRK_SHIFT (4u)
#define SCIF7_SCFSR_TDFE_SHIFT (5u)
#define SCIF7_SCFSR_TEND_SHIFT (6u)
#define SCIF7_SCFSR_ER_SHIFT (7u)
#define SCIF7_SCFSR_FERN_SHIFT (8u)
#define SCIF7_SCFSR_PERN_SHIFT (12u)
#define SCIF7_SCFRDR_D_SHIFT (0u)
#define SCIF7_SCFCR_LOOP_SHIFT (0u)
#define SCIF7_SCFCR_RFRST_SHIFT (1u)
#define SCIF7_SCFCR_TFRST_SHIFT (2u)
#define SCIF7_SCFCR_MCE_SHIFT (3u)
#define SCIF7_SCFCR_TTRG_SHIFT (4u)
#define SCIF7_SCFCR_RTRG_SHIFT (6u)
#define SCIF7_SCFCR_RSTRG_SHIFT (8u)
#define SCIF7_SCFDR_R_SHIFT (0u)
#define SCIF7_SCFDR_T_SHIFT (8u)
#define SCIF7_SCSPTR_SPB2DT_SHIFT (0u)
#define SCIF7_SCSPTR_SPB2IO_SHIFT (1u)
#define SCIF7_SCSPTR_SCKDT_SHIFT (2u)
#define SCIF7_SCSPTR_SCKIO_SHIFT (3u)
#define SCIF7_SCSPTR_CTSDT_SHIFT (4u)
#define SCIF7_SCSPTR_CTSIO_SHIFT (5u)
#define SCIF7_SCSPTR_RTSDT_SHIFT (6u)
#define SCIF7_SCSPTR_RTSIO_SHIFT (7u)
#define SCIF7_SCLSR_ORER_SHIFT (0u)
#define SCIF7_SCEMR_ABCS_SHIFT (0u)
#define SCIF7_SCEMR_BGDM_SHIFT (7u)
/* ---- SCIFn ---- */
#define SCIFn_SCSMR_CKS_SHIFT (0u)
#define SCIFn_SCSMR_STOP_SHIFT (3u)
#define SCIFn_SCSMR_OE_SHIFT (4u)
#define SCIFn_SCSMR_PE_SHIFT (5u)
#define SCIFn_SCSMR_CHR_SHIFT (6u)
#define SCIFn_SCSMR_CA_SHIFT (7u)
#define SCIFn_SCBRR_D_SHIFT (0u)
#define SCIFn_SCSCR_CKE_SHIFT (0u)
#define SCIFn_SCSCR_REIE_SHIFT (3u)
#define SCIFn_SCSCR_RE_SHIFT (4u)
#define SCIFn_SCSCR_TE_SHIFT (5u)
#define SCIFn_SCSCR_RIE_SHIFT (6u)
#define SCIFn_SCSCR_TIE_SHIFT (7u)
#define SCIFn_SCFTDR_D_SHIFT (0u)
#define SCIFn_SCFSR_DR_SHIFT (0u)
#define SCIFn_SCFSR_RDF_SHIFT (1u)
#define SCIFn_SCFSR_PER_SHIFT (2u)
#define SCIFn_SCFSR_FER_SHIFT (3u)
#define SCIFn_SCFSR_BRK_SHIFT (4u)
#define SCIFn_SCFSR_TDFE_SHIFT (5u)
#define SCIFn_SCFSR_TEND_SHIFT (6u)
#define SCIFn_SCFSR_ER_SHIFT (7u)
#define SCIFn_SCFSR_FERN_SHIFT (8u)
#define SCIFn_SCFSR_PERN_SHIFT (12u)
#define SCIFn_SCFRDR_D_SHIFT (0u)
#define SCIFn_SCFCR_LOOP_SHIFT (0u)
#define SCIFn_SCFCR_RFRST_SHIFT (1u)
#define SCIFn_SCFCR_TFRST_SHIFT (2u)
#define SCIFn_SCFCR_MCE_SHIFT (3u)
#define SCIFn_SCFCR_TTRG_SHIFT (4u)
#define SCIFn_SCFCR_RTRG_SHIFT (6u)
#define SCIFn_SCFCR_RSTRG_SHIFT (8u)
#define SCIFn_SCFDR_R_SHIFT (0u)
#define SCIFn_SCFDR_T_SHIFT (8u)
#define SCIFn_SCSPTR_SPB2DT_SHIFT (0u)
#define SCIFn_SCSPTR_SPB2IO_SHIFT (1u)
#define SCIFn_SCSPTR_SCKDT_SHIFT (2u)
#define SCIFn_SCSPTR_SCKIO_SHIFT (3u)
#define SCIFn_SCSPTR_CTSDT_SHIFT (4u)
#define SCIFn_SCSPTR_CTSIO_SHIFT (5u)
#define SCIFn_SCSPTR_RTSDT_SHIFT (6u)
#define SCIFn_SCSPTR_RTSIO_SHIFT (7u)
#define SCIFn_SCLSR_ORER_SHIFT (0u)
#define SCIFn_SCEMR_ABCS_SHIFT (0u)
#define SCIFn_SCEMR_BGDM_SHIFT (7u)
#endif /* SCIF_IOBITMASK_H */
/* End of File */
|
