1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
|
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : usb0_host_dmacdrv.c
* $Rev: 1116 $
* $Date:: 2014-07-09 16:29:19 +0900#$
* Device(s) : RZ/A1H
* Tool-Chain :
* OS : None
* H/W Platform :
* Description : RZ/A1H R7S72100 USB Sample Program
* Operation :
* Limitations :
*******************************************************************************/
/*******************************************************************************
Includes <System Includes> , "Project Includes"
*******************************************************************************/
#include "r_typedefs.h"
#include "iodefine.h"
#include "rza_io_regrw.h"
#include "usb0_host_dmacdrv.h"
/*******************************************************************************
Typedef definitions
*******************************************************************************/
/*******************************************************************************
Macro definitions
*******************************************************************************/
#define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */
/* ==== Request setting information for on-chip peripheral module ==== */
typedef enum dmac_peri_req_reg_type
{
DMAC_REQ_MID,
DMAC_REQ_RID,
DMAC_REQ_AM,
DMAC_REQ_LVL,
DMAC_REQ_REQD
} dmac_peri_req_reg_type_t;
/*******************************************************************************
Imported global variables and functions (from other files)
*******************************************************************************/
/*******************************************************************************
Exported global variables and functions (to be accessed by other files)
*******************************************************************************/
/*******************************************************************************
Private global variables and functions
*******************************************************************************/
/* ==== Prototype declaration ==== */
/* ==== Global variable ==== */
/* On-chip peripheral module request setting table */
static const uint8_t usb0_host_dmac_peri_req_init_table[8][5] =
{
/* MID,RID, AM,LVL,REQD */
{ 32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */
{ 32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */
{ 33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */
{ 33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */
{ 34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */
{ 34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */
{ 35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */
{ 35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */
};
/*******************************************************************************
* Function Name: usb0_host_DMAC1_PeriReqInit
* Description : Sets the register mode for DMA mode and the on-chip peripheral
* : module request for transfer request for DMAC channel 1.
* : Executes DMAC initial setting using the DMA information
* : specified by the argument *trans_info and the enabled/disabled
* : continuous transfer specified by the argument continuation.
* : Registers DMAC channel 1 interrupt handler function and sets
* : the interrupt priority level. Then enables transfer completion
* : interrupt.
* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
* : : register
* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
* : uint32_t continuation : Set continuous transfer to be valid
* : : after DMA transfer has been completed
* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
* : DMAC_SAMPLE_SINGLE : Do not execute continuous
* : : transfer
* : uint32_t request_factor : Factor for on-chip peripheral module
* : : request
* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
* : :
* : uint32_t req_direction : Setting value of CHCFG_n register
* : : REQD bit
* Return Value : none
*******************************************************************************/
void usb0_host_DMAC1_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
uint32_t request_factor, uint32_t req_direction)
{
/* ==== Register mode ==== */
if (DMAC_MODE_REGISTER == dmamode)
{
/* ==== Next0 register set ==== */
DMAC1.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
DMAC1.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
DMAC1.N0TB_n = trans_info->count; /* Total transfer byte count */
/* DAD : Transfer destination address counting direction */
/* SAD : Transfer source address counting direction */
/* DDS : Transfer destination transfer size */
/* SDS : Transfer source transfer size */
RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
trans_info->daddr_dir,
DMAC1_CHCFG_n_DAD_SHIFT,
DMAC1_CHCFG_n_DAD);
RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
trans_info->saddr_dir,
DMAC1_CHCFG_n_SAD_SHIFT,
DMAC1_CHCFG_n_SAD);
RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
trans_info->dst_size,
DMAC1_CHCFG_n_DDS_SHIFT,
DMAC1_CHCFG_n_DDS);
RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
trans_info->src_size,
DMAC1_CHCFG_n_SDS_SHIFT,
DMAC1_CHCFG_n_SDS);
/* DMS : Register mode */
/* RSEL : Select Next0 register set */
/* SBE : No discharge of buffer data when aborted */
/* DEM : No DMA interrupt mask */
RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
0,
DMAC1_CHCFG_n_DMS_SHIFT,
DMAC1_CHCFG_n_DMS);
RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
0,
DMAC1_CHCFG_n_RSEL_SHIFT,
DMAC1_CHCFG_n_RSEL);
RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
0,
DMAC1_CHCFG_n_SBE_SHIFT,
DMAC1_CHCFG_n_SBE);
RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
0,
DMAC1_CHCFG_n_DEM_SHIFT,
DMAC1_CHCFG_n_DEM);
/* ---- Continuous transfer ---- */
if (DMAC_SAMPLE_CONTINUATION == continuation)
{
/* REN : Execute continuous transfer */
/* RSW : Change register set when DMA transfer is completed. */
RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
1,
DMAC1_CHCFG_n_REN_SHIFT,
DMAC1_CHCFG_n_REN);
RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
1,
DMAC1_CHCFG_n_RSW_SHIFT,
DMAC1_CHCFG_n_RSW);
}
/* ---- Single transfer ---- */
else
{
/* REN : Do not execute continuous transfer */
/* RSW : Do not change register set when DMA transfer is completed. */
RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
0,
DMAC1_CHCFG_n_REN_SHIFT,
DMAC1_CHCFG_n_REN);
RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
0,
DMAC1_CHCFG_n_RSW_SHIFT,
DMAC1_CHCFG_n_RSW);
}
/* TM : Single transfer */
/* SEL : Channel setting */
/* HIEN, LOEN : On-chip peripheral module request */
RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
0,
DMAC1_CHCFG_n_TM_SHIFT,
DMAC1_CHCFG_n_TM);
RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
1,
DMAC1_CHCFG_n_SEL_SHIFT,
DMAC1_CHCFG_n_SEL);
RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
1,
DMAC1_CHCFG_n_HIEN_SHIFT,
DMAC1_CHCFG_n_HIEN);
RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
0,
DMAC1_CHCFG_n_LOEN_SHIFT,
DMAC1_CHCFG_n_LOEN);
/* ---- Set factor by specified on-chip peripheral module request ---- */
RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
DMAC1_CHCFG_n_AM_SHIFT,
DMAC1_CHCFG_n_AM);
RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
DMAC1_CHCFG_n_LVL_SHIFT,
DMAC1_CHCFG_n_LVL);
if (usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
{
RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
DMAC1_CHCFG_n_REQD_SHIFT,
DMAC1_CHCFG_n_REQD);
}
else
{
RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
req_direction,
DMAC1_CHCFG_n_REQD_SHIFT,
DMAC1_CHCFG_n_REQD);
}
RZA_IO_RegWrite_32(&DMAC01.DMARS,
usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
DMAC01_DMARS_CH1_RID_SHIFT,
DMAC01_DMARS_CH1_RID);
RZA_IO_RegWrite_32(&DMAC01.DMARS,
usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
DMAC01_DMARS_CH1_MID_SHIFT,
DMAC01_DMARS_CH1_MID);
/* PR : Round robin mode */
RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
1,
DMAC07_DCTRL_0_7_PR_SHIFT,
DMAC07_DCTRL_0_7_PR);
}
}
/*******************************************************************************
* Function Name: usb0_host_DMAC1_Open
* Description : Enables DMAC channel 1 transfer.
* Arguments : uint32_t req : DMAC request mode
* Return Value : 0 : Succeeded in enabling DMA transfer
* : -1 : Failed to enable DMA transfer (due to DMA operation)
*******************************************************************************/
int32_t usb0_host_DMAC1_Open (uint32_t req)
{
int32_t ret;
volatile uint8_t dummy;
/* Transferable? */
if ((0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
DMAC1_CHSTAT_n_EN_SHIFT,
DMAC1_CHSTAT_n_EN)) &&
(0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
DMAC1_CHSTAT_n_TACT_SHIFT,
DMAC1_CHSTAT_n_TACT)))
{
/* Clear Channel Status Register */
RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
1,
DMAC1_CHCTRL_n_SWRST_SHIFT,
DMAC1_CHCTRL_n_SWRST);
dummy = RZA_IO_RegRead_32(&DMAC1.CHCTRL_n,
DMAC1_CHCTRL_n_SWRST_SHIFT,
DMAC1_CHCTRL_n_SWRST);
/* Enable DMA transfer */
RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
1,
DMAC1_CHCTRL_n_SETEN_SHIFT,
DMAC1_CHCTRL_n_SETEN);
/* ---- Request by software ---- */
if (DMAC_REQ_MODE_SOFT == req)
{
/* DMA transfer Request by software */
RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
1,
DMAC1_CHCTRL_n_STG_SHIFT,
DMAC1_CHCTRL_n_STG);
}
ret = 0;
}
else
{
ret = -1;
}
return ret;
}
/*******************************************************************************
* Function Name: usb0_host_DMAC1_Close
* Description : Aborts DMAC channel 1 transfer. Returns the remaining transfer
* : byte count at the time of DMA transfer abort to the argument
* : *remain.
* Arguments : uint32_t * remain : Remaining transfer byte count when
* : : DMA transfer is aborted
* Return Value : none
*******************************************************************************/
void usb0_host_DMAC1_Close (uint32_t * remain)
{
/* ==== Abort transfer ==== */
RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
1,
DMAC1_CHCTRL_n_CLREN_SHIFT,
DMAC1_CHCTRL_n_CLREN);
while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
DMAC1_CHSTAT_n_TACT_SHIFT,
DMAC1_CHSTAT_n_TACT))
{
/* Loop until transfer is aborted */
}
while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
DMAC1_CHSTAT_n_EN_SHIFT,
DMAC1_CHSTAT_n_EN))
{
/* Loop until 0 is set in EN before checking the remaining transfer byte count */
}
/* ==== Obtain remaining transfer byte count ==== */
*remain = DMAC1.CRTB_n;
}
/*******************************************************************************
* Function Name: usb0_host_DMAC1_Load_Set
* Description : Sets the transfer source address, transfer destination
* : address, and total transfer byte count respectively
* : specified by the argument src_addr, dst_addr, and count to
* : DMAC channel 1 as DMA transfer information.
* : Sets the register set selected by the CHCFG_n register
* : RSEL bit from the Next0 or Next1 register set.
* : This function should be called when DMA transfer of DMAC
* : channel 1 is aboted.
* Arguments : uint32_t src_addr : Transfer source address
* : uint32_t dst_addr : Transfer destination address
* : uint32_t count : Total transfer byte count
* Return Value : none
*******************************************************************************/
void usb0_host_DMAC1_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
{
uint8_t reg_set;
/* Obtain register set in use */
reg_set = RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
DMAC1_CHSTAT_n_SR_SHIFT,
DMAC1_CHSTAT_n_SR);
/* ==== Load ==== */
if (0 == reg_set)
{
/* ---- Next0 Register Set ---- */
DMAC1.N0SA_n = src_addr; /* Start address of transfer source */
DMAC1.N0DA_n = dst_addr; /* Start address of transfer destination */
DMAC1.N0TB_n = count; /* Total transfer byte count */
}
else
{
/* ---- Next1 Register Set ---- */
DMAC1.N1SA_n = src_addr; /* Start address of transfer source */
DMAC1.N1DA_n = dst_addr; /* Start address of transfer destination */
DMAC1.N1TB_n = count; /* Total transfer byte count */
}
}
/*******************************************************************************
* Function Name: usb0_host_DMAC2_PeriReqInit
* Description : Sets the register mode for DMA mode and the on-chip peripheral
* : module request for transfer request for DMAC channel 2.
* : Executes DMAC initial setting using the DMA information
* : specified by the argument *trans_info and the enabled/disabled
* : continuous transfer specified by the argument continuation.
* : Registers DMAC channel 2 interrupt handler function and sets
* : the interrupt priority level. Then enables transfer completion
* : interrupt.
* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
* : : register
* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
* : uint32_t continuation : Set continuous transfer to be valid
* : : after DMA transfer has been completed
* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
* : DMAC_SAMPLE_SINGLE : Do not execute continuous
* : : transfer
* : uint32_t request_factor : Factor for on-chip peripheral module
* : : request
* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
* : :
* : uint32_t req_direction : Setting value of CHCFG_n register
* : : REQD bit
* Return Value : none
*******************************************************************************/
void usb0_host_DMAC2_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
uint32_t request_factor, uint32_t req_direction)
{
/* ==== Register mode ==== */
if (DMAC_MODE_REGISTER == dmamode)
{
/* ==== Next0 register set ==== */
DMAC2.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
DMAC2.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
DMAC2.N0TB_n = trans_info->count; /* Total transfer byte count */
/* DAD : Transfer destination address counting direction */
/* SAD : Transfer source address counting direction */
/* DDS : Transfer destination transfer size */
/* SDS : Transfer source transfer size */
RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
trans_info->daddr_dir,
DMAC2_CHCFG_n_DAD_SHIFT,
DMAC2_CHCFG_n_DAD);
RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
trans_info->saddr_dir,
DMAC2_CHCFG_n_SAD_SHIFT,
DMAC2_CHCFG_n_SAD);
RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
trans_info->dst_size,
DMAC2_CHCFG_n_DDS_SHIFT,
DMAC2_CHCFG_n_DDS);
RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
trans_info->src_size,
DMAC2_CHCFG_n_SDS_SHIFT,
DMAC2_CHCFG_n_SDS);
/* DMS : Register mode */
/* RSEL : Select Next0 register set */
/* SBE : No discharge of buffer data when aborted */
/* DEM : No DMA interrupt mask */
RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
0,
DMAC2_CHCFG_n_DMS_SHIFT,
DMAC2_CHCFG_n_DMS);
RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
0,
DMAC2_CHCFG_n_RSEL_SHIFT,
DMAC2_CHCFG_n_RSEL);
RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
0,
DMAC2_CHCFG_n_SBE_SHIFT,
DMAC2_CHCFG_n_SBE);
RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
0,
DMAC2_CHCFG_n_DEM_SHIFT,
DMAC2_CHCFG_n_DEM);
/* ---- Continuous transfer ---- */
if (DMAC_SAMPLE_CONTINUATION == continuation)
{
/* REN : Execute continuous transfer */
/* RSW : Change register set when DMA transfer is completed. */
RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
1,
DMAC2_CHCFG_n_REN_SHIFT,
DMAC2_CHCFG_n_REN);
RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
1,
DMAC2_CHCFG_n_RSW_SHIFT,
DMAC2_CHCFG_n_RSW);
}
/* ---- Single transfer ---- */
else
{
/* REN : Do not execute continuous transfer */
/* RSW : Do not change register set when DMA transfer is completed. */
RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
0,
DMAC2_CHCFG_n_REN_SHIFT,
DMAC2_CHCFG_n_REN);
RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
0,
DMAC2_CHCFG_n_RSW_SHIFT,
DMAC2_CHCFG_n_RSW);
}
/* TM : Single transfer */
/* SEL : Channel setting */
/* HIEN, LOEN : On-chip peripheral module request */
RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
0,
DMAC2_CHCFG_n_TM_SHIFT,
DMAC2_CHCFG_n_TM);
RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
2,
DMAC2_CHCFG_n_SEL_SHIFT,
DMAC2_CHCFG_n_SEL);
RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
1,
DMAC2_CHCFG_n_HIEN_SHIFT,
DMAC2_CHCFG_n_HIEN);
RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
0,
DMAC2_CHCFG_n_LOEN_SHIFT,
DMAC2_CHCFG_n_LOEN);
/* ---- Set factor by specified on-chip peripheral module request ---- */
RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
DMAC2_CHCFG_n_AM_SHIFT,
DMAC2_CHCFG_n_AM);
RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
DMAC2_CHCFG_n_LVL_SHIFT,
DMAC2_CHCFG_n_LVL);
if (usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
{
RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
DMAC2_CHCFG_n_REQD_SHIFT,
DMAC2_CHCFG_n_REQD);
}
else
{
RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
req_direction,
DMAC2_CHCFG_n_REQD_SHIFT,
DMAC2_CHCFG_n_REQD);
}
RZA_IO_RegWrite_32(&DMAC23.DMARS,
usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
DMAC23_DMARS_CH2_RID_SHIFT,
DMAC23_DMARS_CH2_RID);
RZA_IO_RegWrite_32(&DMAC23.DMARS,
usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
DMAC23_DMARS_CH2_MID_SHIFT,
DMAC23_DMARS_CH2_MID);
/* PR : Round robin mode */
RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
1,
DMAC07_DCTRL_0_7_PR_SHIFT,
DMAC07_DCTRL_0_7_PR);
}
}
/*******************************************************************************
* Function Name: usb0_host_DMAC2_Open
* Description : Enables DMAC channel 2 transfer.
* Arguments : uint32_t req : DMAC request mode
* Return Value : 0 : Succeeded in enabling DMA transfer
* : -1 : Failed to enable DMA transfer (due to DMA operation)
*******************************************************************************/
int32_t usb0_host_DMAC2_Open (uint32_t req)
{
int32_t ret;
volatile uint8_t dummy;
/* Transferable? */
if ((0 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
DMAC2_CHSTAT_n_EN_SHIFT,
DMAC2_CHSTAT_n_EN)) &&
(0 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
DMAC2_CHSTAT_n_TACT_SHIFT,
DMAC2_CHSTAT_n_TACT)))
{
/* Clear Channel Status Register */
RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
1,
DMAC2_CHCTRL_n_SWRST_SHIFT,
DMAC2_CHCTRL_n_SWRST);
dummy = RZA_IO_RegRead_32(&DMAC2.CHCTRL_n,
DMAC2_CHCTRL_n_SWRST_SHIFT,
DMAC2_CHCTRL_n_SWRST);
/* Enable DMA transfer */
RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
1,
DMAC2_CHCTRL_n_SETEN_SHIFT,
DMAC2_CHCTRL_n_SETEN);
/* ---- Request by software ---- */
if (DMAC_REQ_MODE_SOFT == req)
{
/* DMA transfer Request by software */
RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
1,
DMAC2_CHCTRL_n_STG_SHIFT,
DMAC2_CHCTRL_n_STG);
}
ret = 0;
}
else
{
ret = -1;
}
return ret;
}
/*******************************************************************************
* Function Name: usb0_host_DMAC2_Close
* Description : Aborts DMAC channel 2 transfer. Returns the remaining transfer
* : byte count at the time of DMA transfer abort to the argument
* : *remain.
* Arguments : uint32_t * remain : Remaining transfer byte count when
* : : DMA transfer is aborted
* Return Value : none
*******************************************************************************/
void usb0_host_DMAC2_Close (uint32_t * remain)
{
/* ==== Abort transfer ==== */
RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
1,
DMAC2_CHCTRL_n_CLREN_SHIFT,
DMAC2_CHCTRL_n_CLREN);
while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
DMAC2_CHSTAT_n_TACT_SHIFT,
DMAC2_CHSTAT_n_TACT))
{
/* Loop until transfer is aborted */
}
while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
DMAC2_CHSTAT_n_EN_SHIFT,
DMAC2_CHSTAT_n_EN))
{
/* Loop until 0 is set in EN before checking the remaining transfer byte count */
}
/* ==== Obtain remaining transfer byte count ==== */
*remain = DMAC2.CRTB_n;
}
/*******************************************************************************
* Function Name: usb0_host_DMAC2_Load_Set
* Description : Sets the transfer source address, transfer destination
* : address, and total transfer byte count respectively
* : specified by the argument src_addr, dst_addr, and count to
* : DMAC channel 2 as DMA transfer information.
* : Sets the register set selected by the CHCFG_n register
* : RSEL bit from the Next0 or Next1 register set.
* : This function should be called when DMA transfer of DMAC
* : channel 2 is aboted.
* Arguments : uint32_t src_addr : Transfer source address
* : uint32_t dst_addr : Transfer destination address
* : uint32_t count : Total transfer byte count
* Return Value : none
*******************************************************************************/
void usb0_host_DMAC2_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
{
uint8_t reg_set;
/* Obtain register set in use */
reg_set = RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
DMAC2_CHSTAT_n_SR_SHIFT,
DMAC2_CHSTAT_n_SR);
/* ==== Load ==== */
if (0 == reg_set)
{
/* ---- Next0 Register Set ---- */
DMAC2.N0SA_n = src_addr; /* Start address of transfer source */
DMAC2.N0DA_n = dst_addr; /* Start address of transfer destination */
DMAC2.N0TB_n = count; /* Total transfer byte count */
}
else
{
/* ---- Next1 Register Set ---- */
DMAC2.N1SA_n = src_addr; /* Start address of transfer source */
DMAC2.N1DA_n = dst_addr; /* Start address of transfer destination */
DMAC2.N1TB_n = count; /* Total transfer byte count */
}
}
/* End of File */
|
