From 2728603fe6d73e805a539d337fd01051c46ca806 Mon Sep 17 00:00:00 2001 From: Joel Challis Date: Fri, 19 Nov 2021 18:41:02 +0000 Subject: Move tmk_core/common/ (#13918) --- platforms/chibios/_timer.h | 19 + platforms/chibios/_wait.c | 89 ++++ platforms/chibios/_wait.h | 60 +++ platforms/chibios/atomic_util.h | 37 ++ platforms/chibios/bootloader.c | 145 ++++++ platforms/chibios/chibios_config.h | 78 ++++ platforms/chibios/eeprom_stm32.c | 687 +++++++++++++++++++++++++++ platforms/chibios/eeprom_stm32.h | 33 ++ platforms/chibios/eeprom_stm32_defs.h | 74 +++ platforms/chibios/eeprom_teensy.c | 795 ++++++++++++++++++++++++++++++++ platforms/chibios/flash_stm32.c | 208 +++++++++ platforms/chibios/flash_stm32.h | 44 ++ platforms/chibios/gd32v_compatibility.h | 120 +++++ platforms/chibios/gpio.h | 50 ++ platforms/chibios/pin_defs.h | 323 +++++++++++++ platforms/chibios/platform.c | 22 + platforms/chibios/platform.mk | 436 ++++++++++++++++++ platforms/chibios/platform_deps.h | 19 + platforms/chibios/sleep_led.c | 192 ++++++++ platforms/chibios/suspend.c | 92 ++++ platforms/chibios/syscall-fallbacks.c | 110 +++++ platforms/chibios/timer.c | 47 ++ platforms/chibios/wait.c | 41 ++ 23 files changed, 3721 insertions(+) create mode 100644 platforms/chibios/_timer.h create mode 100644 platforms/chibios/_wait.c create mode 100644 platforms/chibios/_wait.h create mode 100644 platforms/chibios/atomic_util.h create mode 100644 platforms/chibios/bootloader.c create mode 100644 platforms/chibios/chibios_config.h create mode 100644 platforms/chibios/eeprom_stm32.c create mode 100644 platforms/chibios/eeprom_stm32.h create mode 100644 platforms/chibios/eeprom_stm32_defs.h create mode 100644 platforms/chibios/eeprom_teensy.c create mode 100644 platforms/chibios/flash_stm32.c create mode 100644 platforms/chibios/flash_stm32.h create mode 100644 platforms/chibios/gd32v_compatibility.h create mode 100644 platforms/chibios/gpio.h create mode 100644 platforms/chibios/pin_defs.h create mode 100644 platforms/chibios/platform.c create mode 100644 platforms/chibios/platform.mk create mode 100644 platforms/chibios/platform_deps.h create mode 100644 platforms/chibios/sleep_led.c create mode 100644 platforms/chibios/suspend.c create mode 100644 platforms/chibios/syscall-fallbacks.c create mode 100644 platforms/chibios/timer.c create mode 100644 platforms/chibios/wait.c (limited to 'platforms/chibios') diff --git a/platforms/chibios/_timer.h b/platforms/chibios/_timer.h new file mode 100644 index 0000000000..77402b612a --- /dev/null +++ b/platforms/chibios/_timer.h @@ -0,0 +1,19 @@ +/* Copyright 2021 Simon Arlott + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#pragma once + +// The platform is 32-bit, so prefer 32-bit timers to avoid overflow +#define FAST_TIMER_T_SIZE 32 diff --git a/platforms/chibios/_wait.c b/platforms/chibios/_wait.c new file mode 100644 index 0000000000..1fbea2dd5e --- /dev/null +++ b/platforms/chibios/_wait.c @@ -0,0 +1,89 @@ +/* Copyright 2021 QMK + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __OPTIMIZE__ +# pragma message "Compiler optimizations disabled; wait_cpuclock() won't work as designed" +#endif + +#define CLOCK_DELAY_NOP8 "nop\n\t nop\n\t nop\n\t nop\n\t nop\n\t nop\n\t nop\n\t nop\n\t" + +__attribute__((always_inline)) static inline void wait_cpuclock(unsigned int n) { /* n: 1..135 */ + /* The argument n must be a constant expression. + * That way, compiler optimization will remove unnecessary code. */ + if (n < 1) { + return; + } + if (n > 8) { + unsigned int n8 = n / 8; + n = n - n8 * 8; + switch (n8) { + case 16: + asm volatile(CLOCK_DELAY_NOP8::: "memory"); + case 15: + asm volatile(CLOCK_DELAY_NOP8::: "memory"); + case 14: + asm volatile(CLOCK_DELAY_NOP8::: "memory"); + case 13: + asm volatile(CLOCK_DELAY_NOP8::: "memory"); + case 12: + asm volatile(CLOCK_DELAY_NOP8::: "memory"); + case 11: + asm volatile(CLOCK_DELAY_NOP8::: "memory"); + case 10: + asm volatile(CLOCK_DELAY_NOP8::: "memory"); + case 9: + asm volatile(CLOCK_DELAY_NOP8::: "memory"); + case 8: + asm volatile(CLOCK_DELAY_NOP8::: "memory"); + case 7: + asm volatile(CLOCK_DELAY_NOP8::: "memory"); + case 6: + asm volatile(CLOCK_DELAY_NOP8::: "memory"); + case 5: + asm volatile(CLOCK_DELAY_NOP8::: "memory"); + case 4: + asm volatile(CLOCK_DELAY_NOP8::: "memory"); + case 3: + asm volatile(CLOCK_DELAY_NOP8::: "memory"); + case 2: + asm volatile(CLOCK_DELAY_NOP8::: "memory"); + case 1: + asm volatile(CLOCK_DELAY_NOP8::: "memory"); + case 0: + break; + } + } + switch (n) { + case 8: + asm volatile("nop" ::: "memory"); + case 7: + asm volatile("nop" ::: "memory"); + case 6: + asm volatile("nop" ::: "memory"); + case 5: + asm volatile("nop" ::: "memory"); + case 4: + asm volatile("nop" ::: "memory"); + case 3: + asm volatile("nop" ::: "memory"); + case 2: + asm volatile("nop" ::: "memory"); + case 1: + asm volatile("nop" ::: "memory"); + case 0: + break; + } +} diff --git a/platforms/chibios/_wait.h b/platforms/chibios/_wait.h new file mode 100644 index 0000000000..2f36c64a2e --- /dev/null +++ b/platforms/chibios/_wait.h @@ -0,0 +1,60 @@ +/* Copyright 2021 QMK + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#pragma once + +#include +#include + +/* chThdSleepX of zero maps to infinite - so we map to a tiny delay to still yield */ +#define wait_ms(ms) \ + do { \ + if (ms != 0) { \ + chThdSleepMilliseconds(ms); \ + } else { \ + chThdSleepMicroseconds(1); \ + } \ + } while (0) + +#ifdef WAIT_US_TIMER +void wait_us(uint16_t duration); +#else +# define wait_us(us) \ + do { \ + if (us != 0) { \ + chThdSleepMicroseconds(us); \ + } else { \ + chThdSleepMicroseconds(1); \ + } \ + } while (0) +#endif + +#include "_wait.c" + +/* For GPIOs on ARM-based MCUs, the input pins are sampled by the clock of the bus + * to which the GPIO is connected. + * The connected buses differ depending on the various series of MCUs. + * And since the instruction execution clock of the CPU and the bus clock of GPIO are different, + * there is a delay of several clocks to read the change of the input signal. + * + * Define this delay with the GPIO_INPUT_PIN_DELAY macro. + * If the GPIO_INPUT_PIN_DELAY macro is not defined, the following default values will be used. + * (A fairly large value of 0.25 microseconds is set.) + */ +#ifndef GPIO_INPUT_PIN_DELAY +# define GPIO_INPUT_PIN_DELAY (CPU_CLOCK / 1000000L / 4) +#endif + +#define waitInputPinDelay() wait_cpuclock(GPIO_INPUT_PIN_DELAY) diff --git a/platforms/chibios/atomic_util.h b/platforms/chibios/atomic_util.h new file mode 100644 index 0000000000..8975045153 --- /dev/null +++ b/platforms/chibios/atomic_util.h @@ -0,0 +1,37 @@ +/* Copyright 2021 QMK + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#pragma once + +#include + +static __inline__ uint8_t __interrupt_disable__(void) { + chSysLock(); + + return 1; +} + +static __inline__ void __interrupt_enable__(const uint8_t *__s) { + chSysUnlock(); + + __asm__ volatile("" ::: "memory"); + (void)__s; +} + +#define ATOMIC_BLOCK(type) for (type, __ToDo = __interrupt_disable__(); __ToDo; __ToDo = 0) +#define ATOMIC_FORCEON uint8_t sreg_save __attribute__((__cleanup__(__interrupt_enable__))) = 0 + +#define ATOMIC_BLOCK_RESTORESTATE _Static_assert(0, "ATOMIC_BLOCK_RESTORESTATE not implemented") +#define ATOMIC_BLOCK_FORCEON ATOMIC_BLOCK(ATOMIC_FORCEON) diff --git a/platforms/chibios/bootloader.c b/platforms/chibios/bootloader.c new file mode 100644 index 0000000000..5cadadeeeb --- /dev/null +++ b/platforms/chibios/bootloader.c @@ -0,0 +1,145 @@ +#include "bootloader.h" + +#include +#include +#include "wait.h" + +/* This code should be checked whether it runs correctly on platforms */ +#define SYMVAL(sym) (uint32_t)(((uint8_t *)&(sym)) - ((uint8_t *)0)) +#define BOOTLOADER_MAGIC 0xDEADBEEF +#define MAGIC_ADDR (unsigned long *)(SYMVAL(__ram0_end__) - 4) + +#ifndef STM32_BOOTLOADER_DUAL_BANK +# define STM32_BOOTLOADER_DUAL_BANK FALSE +#endif + +#ifdef BOOTLOADER_TINYUF2 + +# define DBL_TAP_MAGIC 0xf01669ef // From tinyuf2's board_api.h + +// defined by linker script +extern uint32_t _board_dfu_dbl_tap[]; +# define DBL_TAP_REG _board_dfu_dbl_tap[0] + +void bootloader_jump(void) { + DBL_TAP_REG = DBL_TAP_MAGIC; + NVIC_SystemReset(); +} + +void enter_bootloader_mode_if_requested(void) { /* not needed, no two-stage reset */ +} + +#elif STM32_BOOTLOADER_DUAL_BANK + +// Need pin definitions +# include "config_common.h" + +# ifndef STM32_BOOTLOADER_DUAL_BANK_GPIO +# error "No STM32_BOOTLOADER_DUAL_BANK_GPIO defined, don't know which pin to toggle" +# endif + +# ifndef STM32_BOOTLOADER_DUAL_BANK_POLARITY +# define STM32_BOOTLOADER_DUAL_BANK_POLARITY 0 +# endif + +# ifndef STM32_BOOTLOADER_DUAL_BANK_DELAY +# define STM32_BOOTLOADER_DUAL_BANK_DELAY 100000 +# endif + +extern uint32_t __ram0_end__; + +__attribute__((weak)) void bootloader_jump(void) { + // For STM32 MCUs with dual-bank flash, and we're incapable of jumping to the bootloader. The first valid flash + // bank is executed unconditionally after a reset, so it doesn't enter DFU unless BOOT0 is high. Instead, we do + // it with hardware...in this case, we pull a GPIO high/low depending on the configuration, connects 3.3V to + // BOOT0's RC charging circuit, lets it charge the capacitor, and issue a system reset. See the QMK discord + // #hardware channel pins for an example circuit. + palSetPadMode(PAL_PORT(STM32_BOOTLOADER_DUAL_BANK_GPIO), PAL_PAD(STM32_BOOTLOADER_DUAL_BANK_GPIO), PAL_MODE_OUTPUT_PUSHPULL); +# if STM32_BOOTLOADER_DUAL_BANK_POLARITY + palSetPad(PAL_PORT(STM32_BOOTLOADER_DUAL_BANK_GPIO), PAL_PAD(STM32_BOOTLOADER_DUAL_BANK_GPIO)); +# else + palClearPad(PAL_PORT(STM32_BOOTLOADER_DUAL_BANK_GPIO), PAL_PAD(STM32_BOOTLOADER_DUAL_BANK_GPIO)); +# endif + + // Wait for a while for the capacitor to charge + wait_ms(100); + + // Issue a system reset to get the ROM bootloader to execute, with BOOT0 high + NVIC_SystemReset(); +} + +void enter_bootloader_mode_if_requested(void) {} // not needed at all, but if anybody attempts to invoke it.... + +#elif defined(STM32_BOOTLOADER_ADDRESS) // STM32_BOOTLOADER_DUAL_BANK + +extern uint32_t __ram0_end__; + +__attribute__((weak)) void bootloader_jump(void) { + *MAGIC_ADDR = BOOTLOADER_MAGIC; // set magic flag => reset handler will jump into boot loader + NVIC_SystemReset(); +} + +void enter_bootloader_mode_if_requested(void) { + unsigned long *check = MAGIC_ADDR; + if (*check == BOOTLOADER_MAGIC) { + *check = 0; + __set_CONTROL(0); + __set_MSP(*(__IO uint32_t *)STM32_BOOTLOADER_ADDRESS); + __enable_irq(); + + typedef void (*BootJump_t)(void); + BootJump_t boot_jump = *(BootJump_t *)(STM32_BOOTLOADER_ADDRESS + 4); + boot_jump(); + while (1) + ; + } +} + +#elif defined(GD32VF103) + +# define DBGMCU_KEY_UNLOCK 0x4B5A6978 +# define DBGMCU_CMD_RESET 0x1 + +__IO uint32_t *DBGMCU_KEY = (uint32_t *)DBGMCU_BASE + 0x0CU; +__IO uint32_t *DBGMCU_CMD = (uint32_t *)DBGMCU_BASE + 0x08U; + +__attribute__((weak)) void bootloader_jump(void) { + /* The MTIMER unit of the GD32VF103 doesn't have the MSFRST + * register to generate a software reset request. + * BUT instead two undocumented registers in the debug peripheral + * that allow issueing a software reset. WHO would need the MSFRST + * register anyway? Source: + * https://github.com/esmil/gd32vf103inator/blob/master/include/gd32vf103/dbg.h */ + *DBGMCU_KEY = DBGMCU_KEY_UNLOCK; + *DBGMCU_CMD = DBGMCU_CMD_RESET; +} + +void enter_bootloader_mode_if_requested(void) { /* Jumping to bootloader is not possible from user code. */ +} + +#elif defined(KL2x) || defined(K20x) || defined(MK66F18) || defined(MIMXRT1062) // STM32_BOOTLOADER_DUAL_BANK // STM32_BOOTLOADER_ADDRESS +/* Kinetis */ + +# if defined(BOOTLOADER_KIIBOHD) +/* Kiibohd Bootloader (MCHCK and Infinity KB) */ +# define SCB_AIRCR_VECTKEY_WRITEMAGIC 0x05FA0000 +const uint8_t sys_reset_to_loader_magic[] = "\xff\x00\x7fRESET TO LOADER\x7f\x00\xff"; +__attribute__((weak)) void bootloader_jump(void) { + void *volatile vbat = (void *)VBAT; + __builtin_memcpy(vbat, (const void *)sys_reset_to_loader_magic, sizeof(sys_reset_to_loader_magic)); + // request reset + SCB->AIRCR = SCB_AIRCR_VECTKEY_WRITEMAGIC | SCB_AIRCR_SYSRESETREQ_Msk; +} + +# else /* defined(BOOTLOADER_KIIBOHD) */ +/* Default for Kinetis - expecting an ARM Teensy */ +# include "wait.h" +__attribute__((weak)) void bootloader_jump(void) { + wait_ms(100); + __BKPT(0); +} +# endif /* defined(BOOTLOADER_KIIBOHD) */ + +#else /* neither STM32 nor KINETIS */ +__attribute__((weak)) void bootloader_jump(void) {} +#endif diff --git a/platforms/chibios/chibios_config.h b/platforms/chibios/chibios_config.h new file mode 100644 index 0000000000..ad2f808a95 --- /dev/null +++ b/platforms/chibios/chibios_config.h @@ -0,0 +1,78 @@ +/* Copyright 2019 + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#pragma once + +#ifndef USB_VBUS_PIN +# define SPLIT_USB_DETECT // Force this on when dedicated pin is not used +#endif + +// STM32 compatibility +#if defined(MCU_STM32) +# define CPU_CLOCK STM32_SYSCLK + +# if defined(STM32F1XX) +# define USE_GPIOV1 +# define PAL_MODE_ALTERNATE_OPENDRAIN PAL_MODE_STM32_ALTERNATE_OPENDRAIN +# define PAL_MODE_ALTERNATE_PUSHPULL PAL_MODE_STM32_ALTERNATE_PUSHPULL +# else +# define PAL_OUTPUT_TYPE_OPENDRAIN PAL_STM32_OTYPE_OPENDRAIN +# define PAL_OUTPUT_TYPE_PUSHPULL PAL_STM32_OTYPE_PUSHPULL +# define PAL_OUTPUT_SPEED_HIGHEST PAL_STM32_OSPEED_HIGHEST +# define PAL_PUPDR_FLOATING PAL_STM32_PUPDR_FLOATING +# endif + +# if defined(STM32F1XX) || defined(STM32F2XX) || defined(STM32F4XX) || defined(STM32L1XX) +# define USE_I2CV1 +# endif +#endif + +// GD32 compatibility +#if defined(MCU_GD32V) +# define CPU_CLOCK GD32_SYSCLK + +# if defined(GD32VF103) +# define USE_GPIOV1 +# define USE_I2CV1 +# define PAL_MODE_ALTERNATE_OPENDRAIN PAL_MODE_GD32_ALTERNATE_OPENDRAIN +# define PAL_MODE_ALTERNATE_PUSHPULL PAL_MODE_GD32_ALTERNATE_PUSHPULL +# endif +#endif + +#if defined(GD32VF103) +/* This chip has the same API as STM32F103, but uses different names for literally the same thing. + * As of 4.7.2021 QMK is tailored to use STM32 defines/names, for compatibility sake + * we just redefine the GD32 names. */ +# include "gd32v_compatibility.h" +#endif + +// teensy compatibility +#if defined(MCU_KINETIS) +# define CPU_CLOCK KINETIS_SYSCLK_FREQUENCY + +# if defined(K20x) || defined(KL2x) +# define USE_I2CV1 +# define USE_I2CV1_CONTRIB // for some reason a bunch of ChibiOS-Contrib boards only have clock_speed +# define USE_GPIOV1 +# endif +#endif + +#if defined(HT32) +# define CPU_CLOCK HT32_CK_SYS_FREQUENCY +# define PAL_MODE_ALTERNATE PAL_HT32_MODE_AF +# define PAL_OUTPUT_TYPE_OPENDRAIN (PAL_HT32_MODE_OD | PAL_HT32_MODE_DIR) +# define PAL_OUTPUT_TYPE_PUSHPULL PAL_HT32_MODE_DIR +# define PAL_OUTPUT_SPEED_HIGHEST 0 +#endif diff --git a/platforms/chibios/eeprom_stm32.c b/platforms/chibios/eeprom_stm32.c new file mode 100644 index 0000000000..acc6a48516 --- /dev/null +++ b/platforms/chibios/eeprom_stm32.c @@ -0,0 +1,687 @@ +/* + * This software is experimental and a work in progress. + * Under no circumstances should these files be used in relation to any critical system(s). + * Use of these files is at your own risk. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR + * PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This files are free to use from http://engsta.com/stm32-flash-memory-eeprom-emulator/ by + * Artur F. + * + * Modifications for QMK and STM32F303 by Yiancar + * Modifications to add flash wear leveling by Ilya Zhuravlev + * Modifications to increase flash density by Don Kjer + */ + +#include +#include +#include "util.h" +#include "debug.h" +#include "eeprom_stm32.h" +#include "flash_stm32.h" + +/* + * We emulate eeprom by writing a snapshot compacted view of eeprom contents, + * followed by a write log of any change since that snapshot: + * + * === SIMULATED EEPROM CONTENTS === + * + * ┌─ Compacted ┬ Write Log ─┐ + * │............│[BYTE][BYTE]│ + * │FFFF....FFFF│[WRD0][WRD1]│ + * │FFFFFFFFFFFF│[WORD][NEXT]│ + * │....FFFFFFFF│[BYTE][WRD0]│ + * ├────────────┼────────────┤ + * └──PAGE_BASE │ │ + * PAGE_LAST─┴─WRITE_BASE │ + * WRITE_LAST ┘ + * + * Compacted contents are the 1's complement of the actual EEPROM contents. + * e.g. An 'FFFF' represents a '0000' value. + * + * The size of the 'compacted' area is equal to the size of the 'emulated' eeprom. + * The size of the compacted-area and write log are configurable, and the combined + * size of Compacted + WriteLog is a multiple FEE_PAGE_SIZE, which is MCU dependent. + * Simulated Eeprom contents are located at the end of available flash space. + * + * The following configuration defines can be set: + * + * FEE_PAGE_COUNT # Total number of pages to use for eeprom simulation (Compact + Write log) + * FEE_DENSITY_BYTES # Size of simulated eeprom. (Defaults to half the space allocated by FEE_PAGE_COUNT) + * NOTE: The current implementation does not include page swapping, + * and FEE_DENSITY_BYTES will consume that amount of RAM as a cached view of actual EEPROM contents. + * + * The maximum size of FEE_DENSITY_BYTES is currently 16384. The write log size equals + * FEE_PAGE_COUNT * FEE_PAGE_SIZE - FEE_DENSITY_BYTES. + * The larger the write log, the less frequently the compacted area needs to be rewritten. + * + * + * *** General Algorithm *** + * + * During initialization: + * The contents of the Compacted-flash area are loaded and the 1's complement value + * is cached into memory (e.g. 0xFFFF in Flash represents 0x0000 in cache). + * Write log entries are processed until a 0xFFFF is reached. + * Each log entry updates a byte or word in the cache. + * + * During reads: + * EEPROM contents are given back directly from the cache in memory. + * + * During writes: + * The contents of the cache is updated first. + * If the Compacted-flash area corresponding to the write address is unprogrammed, the 1's complement of the value is written directly into Compacted-flash + * Otherwise: + * If the write log is full, erase both the Compacted-flash area and the Write log, then write cached contents to the Compacted-flash area. + * Otherwise a Write log entry is constructed and appended to the next free position in the Write log. + * + * + * *** Write Log Structure *** + * + * Write log entries allow for optimized byte writes to addresses below 128. Writing 0 or 1 words are also optimized when word-aligned. + * + * === WRITE LOG ENTRY FORMATS === + * + * ╔═══ Byte-Entry ══╗ + * ║0XXXXXXX║YYYYYYYY║ + * ║ └──┬──┘║└──┬───┘║ + * ║ Address║ Value ║ + * ╚════════╩════════╝ + * 0 <= Address < 0x80 (128) + * + * ╔ Word-Encoded 0 ╗ + * ║100XXXXXXXXXXXXX║ + * ║ │└─────┬─────┘║ + * ║ │Address >> 1 ║ + * ║ └── Value: 0 ║ + * ╚════════════════╝ + * 0 <= Address <= 0x3FFE (16382) + * + * ╔ Word-Encoded 1 ╗ + * ║101XXXXXXXXXXXXX║ + * ║ │└─────┬─────┘║ + * ║ │Address >> 1 ║ + * ║ └── Value: 1 ║ + * ╚════════════════╝ + * 0 <= Address <= 0x3FFE (16382) + * + * ╔═══ Reserved ═══╗ + * ║110XXXXXXXXXXXXX║ + * ╚════════════════╝ + * + * ╔═══════════ Word-Next ═══════════╗ + * ║111XXXXXXXXXXXXX║YYYYYYYYYYYYYYYY║ + * ║ └─────┬─────┘║└───────┬──────┘║ + * ║(Address-128)>>1║ ~Value ║ + * ╚════════════════╩════════════════╝ + * ( 0 <= Address < 0x0080 (128): Reserved) + * 0x80 <= Address <= 0x3FFE (16382) + * + * Write Log entry ranges: + * 0x0000 ... 0x7FFF - Byte-Entry; address is (Entry & 0x7F00) >> 4; value is (Entry & 0xFF) + * 0x8000 ... 0x9FFF - Word-Encoded 0; address is (Entry & 0x1FFF) << 1; value is 0 + * 0xA000 ... 0xBFFF - Word-Encoded 1; address is (Entry & 0x1FFF) << 1; value is 1 + * 0xC000 ... 0xDFFF - Reserved + * 0xE000 ... 0xFFBF - Word-Next; address is (Entry & 0x1FFF) << 1 + 0x80; value is ~(Next_Entry) + * 0xFFC0 ... 0xFFFE - Reserved + * 0xFFFF - Unprogrammed + * + */ + +#include "eeprom_stm32_defs.h" +#if !defined(FEE_PAGE_SIZE) || !defined(FEE_PAGE_COUNT) || !defined(FEE_MCU_FLASH_SIZE) || !defined(FEE_PAGE_BASE_ADDRESS) +# error "not implemented." +#endif + +/* These bits are used for optimizing encoding of bytes, 0 and 1 */ +#define FEE_WORD_ENCODING 0x8000 +#define FEE_VALUE_NEXT 0x6000 +#define FEE_VALUE_RESERVED 0x4000 +#define FEE_VALUE_ENCODED 0x2000 +#define FEE_BYTE_RANGE 0x80 + +/* Addressable range 16KByte: 0 <-> (0x1FFF << 1) */ +#define FEE_ADDRESS_MAX_SIZE 0x4000 + +/* Flash word value after erase */ +#define FEE_EMPTY_WORD ((uint16_t)0xFFFF) + +/* Size of combined compacted eeprom and write log pages */ +#define FEE_DENSITY_MAX_SIZE (FEE_PAGE_COUNT * FEE_PAGE_SIZE) + +#ifndef FEE_MCU_FLASH_SIZE_IGNORE_CHECK /* *TODO: Get rid of this check */ +# if FEE_DENSITY_MAX_SIZE > (FEE_MCU_FLASH_SIZE * 1024) +# pragma message STR(FEE_DENSITY_MAX_SIZE) " > " STR(FEE_MCU_FLASH_SIZE * 1024) +# error emulated eeprom: FEE_DENSITY_MAX_SIZE is greater than available flash size +# endif +#endif + +/* Size of emulated eeprom */ +#ifdef FEE_DENSITY_BYTES +# if (FEE_DENSITY_BYTES > FEE_DENSITY_MAX_SIZE) +# pragma message STR(FEE_DENSITY_BYTES) " > " STR(FEE_DENSITY_MAX_SIZE) +# error emulated eeprom: FEE_DENSITY_BYTES exceeds FEE_DENSITY_MAX_SIZE +# endif +# if (FEE_DENSITY_BYTES == FEE_DENSITY_MAX_SIZE) +# pragma message STR(FEE_DENSITY_BYTES) " == " STR(FEE_DENSITY_MAX_SIZE) +# warning emulated eeprom: FEE_DENSITY_BYTES leaves no room for a write log. This will greatly increase the flash wear rate! +# endif +# if FEE_DENSITY_BYTES > FEE_ADDRESS_MAX_SIZE +# pragma message STR(FEE_DENSITY_BYTES) " > " STR(FEE_ADDRESS_MAX_SIZE) +# error emulated eeprom: FEE_DENSITY_BYTES is greater than FEE_ADDRESS_MAX_SIZE allows +# endif +# if ((FEE_DENSITY_BYTES) % 2) == 1 +# error emulated eeprom: FEE_DENSITY_BYTES must be even +# endif +#else +/* Default to half of allocated space used for emulated eeprom, half for write log */ +# define FEE_DENSITY_BYTES (FEE_PAGE_COUNT * FEE_PAGE_SIZE / 2) +#endif + +/* Size of write log */ +#ifdef FEE_WRITE_LOG_BYTES +# if ((FEE_DENSITY_BYTES + FEE_WRITE_LOG_BYTES) > FEE_DENSITY_MAX_SIZE) +# pragma message STR(FEE_DENSITY_BYTES) " + " STR(FEE_WRITE_LOG_BYTES) " > " STR(FEE_DENSITY_MAX_SIZE) +# error emulated eeprom: FEE_WRITE_LOG_BYTES exceeds remaining FEE_DENSITY_MAX_SIZE +# endif +# if ((FEE_WRITE_LOG_BYTES) % 2) == 1 +# error emulated eeprom: FEE_WRITE_LOG_BYTES must be even +# endif +#else +/* Default to use all remaining space */ +# define FEE_WRITE_LOG_BYTES (FEE_PAGE_COUNT * FEE_PAGE_SIZE - FEE_DENSITY_BYTES) +#endif + +/* Start of the emulated eeprom compacted flash area */ +#define FEE_COMPACTED_BASE_ADDRESS FEE_PAGE_BASE_ADDRESS +/* End of the emulated eeprom compacted flash area */ +#define FEE_COMPACTED_LAST_ADDRESS (FEE_COMPACTED_BASE_ADDRESS + FEE_DENSITY_BYTES) +/* Start of the emulated eeprom write log */ +#define FEE_WRITE_LOG_BASE_ADDRESS FEE_COMPACTED_LAST_ADDRESS +/* End of the emulated eeprom write log */ +#define FEE_WRITE_LOG_LAST_ADDRESS (FEE_WRITE_LOG_BASE_ADDRESS + FEE_WRITE_LOG_BYTES) + +#if defined(DYNAMIC_KEYMAP_EEPROM_MAX_ADDR) && (DYNAMIC_KEYMAP_EEPROM_MAX_ADDR >= FEE_DENSITY_BYTES) +# error emulated eeprom: DYNAMIC_KEYMAP_EEPROM_MAX_ADDR is greater than the FEE_DENSITY_BYTES available +#endif + +/* In-memory contents of emulated eeprom for faster access */ +/* *TODO: Implement page swapping */ +static uint16_t WordBuf[FEE_DENSITY_BYTES / 2]; +static uint8_t *DataBuf = (uint8_t *)WordBuf; + +/* Pointer to the first available slot within the write log */ +static uint16_t *empty_slot; + +// #define DEBUG_EEPROM_OUTPUT + +/* + * Debug print utils + */ + +#if defined(DEBUG_EEPROM_OUTPUT) + +# define debug_eeprom debug_enable +# define eeprom_println(s) println(s) +# define eeprom_printf(fmt, ...) xprintf(fmt, ##__VA_ARGS__); + +#else /* NO_DEBUG */ + +# define debug_eeprom false +# define eeprom_println(s) +# define eeprom_printf(fmt, ...) + +#endif /* NO_DEBUG */ + +void print_eeprom(void) { +#ifndef NO_DEBUG + int empty_rows = 0; + for (uint16_t i = 0; i < FEE_DENSITY_BYTES; i++) { + if (i % 16 == 0) { + if (i >= FEE_DENSITY_BYTES - 16) { + /* Make sure we display the last row */ + empty_rows = 0; + } + /* Check if this row is uninitialized */ + ++empty_rows; + for (uint16_t j = 0; j < 16; j++) { + if (DataBuf[i + j]) { + empty_rows = 0; + break; + } + } + if (empty_rows > 1) { + /* Repeat empty row */ + if (empty_rows == 2) { + /* Only display the first repeat empty row */ + println("*"); + } + i += 15; + continue; + } + xprintf("%04x", i); + } + if (i % 8 == 0) print(" "); + + xprintf(" %02x", DataBuf[i]); + if ((i + 1) % 16 == 0) { + println(""); + } + } +#endif +} + +uint16_t EEPROM_Init(void) { + /* Load emulated eeprom contents from compacted flash into memory */ + uint16_t *src = (uint16_t *)FEE_COMPACTED_BASE_ADDRESS; + uint16_t *dest = (uint16_t *)DataBuf; + for (; src < (uint16_t *)FEE_COMPACTED_LAST_ADDRESS; ++src, ++dest) { + *dest = ~*src; + } + + if (debug_eeprom) { + println("EEPROM_Init Compacted Pages:"); + print_eeprom(); + println("EEPROM_Init Write Log:"); + } + + /* Replay write log */ + uint16_t *log_addr; + for (log_addr = (uint16_t *)FEE_WRITE_LOG_BASE_ADDRESS; log_addr < (uint16_t *)FEE_WRITE_LOG_LAST_ADDRESS; ++log_addr) { + uint16_t address = *log_addr; + if (address == FEE_EMPTY_WORD) { + break; + } + /* Check for lowest 128-bytes optimization */ + if (!(address & FEE_WORD_ENCODING)) { + uint8_t bvalue = (uint8_t)address; + address >>= 8; + DataBuf[address] = bvalue; + eeprom_printf("DataBuf[0x%02x] = 0x%02x;\n", address, bvalue); + } else { + uint16_t wvalue; + /* Check if value is in next word */ + if ((address & FEE_VALUE_NEXT) == FEE_VALUE_NEXT) { + /* Read value from next word */ + if (++log_addr >= (uint16_t *)FEE_WRITE_LOG_LAST_ADDRESS) { + break; + } + wvalue = ~*log_addr; + if (!wvalue) { + eeprom_printf("Incomplete write at log_addr: 0x%04x;\n", (uint32_t)log_addr); + /* Possibly incomplete write. Ignore and continue */ + continue; + } + address &= 0x1FFF; + address <<= 1; + /* Writes to addresses less than 128 are byte log entries */ + address += FEE_BYTE_RANGE; + } else { + /* Reserved for future use */ + if (address & FEE_VALUE_RESERVED) { + eeprom_printf("Reserved encoded value at log_addr: 0x%04x;\n", (uint32_t)log_addr); + continue; + } + /* Optimization for 0 or 1 values. */ + wvalue = (address & FEE_VALUE_ENCODED) >> 13; + address &= 0x1FFF; + address <<= 1; + } + if (address < FEE_DENSITY_BYTES) { + eeprom_printf("DataBuf[0x%04x] = 0x%04x;\n", address, wvalue); + *(uint16_t *)(&DataBuf[address]) = wvalue; + } else { + eeprom_printf("DataBuf[0x%04x] cannot be set to 0x%04x [BAD ADDRESS]\n", address, wvalue); + } + } + } + + empty_slot = log_addr; + + if (debug_eeprom) { + println("EEPROM_Init Final DataBuf:"); + print_eeprom(); + } + + return FEE_DENSITY_BYTES; +} + +/* Clear flash contents (doesn't touch in-memory DataBuf) */ +static void eeprom_clear(void) { + FLASH_Unlock(); + + for (uint16_t page_num = 0; page_num < FEE_PAGE_COUNT; ++page_num) { + eeprom_printf("FLASH_ErasePage(0x%04x)\n", (uint32_t)(FEE_PAGE_BASE_ADDRESS + (page_num * FEE_PAGE_SIZE))); + FLASH_ErasePage(FEE_PAGE_BASE_ADDRESS + (page_num * FEE_PAGE_SIZE)); + } + + FLASH_Lock(); + + empty_slot = (uint16_t *)FEE_WRITE_LOG_BASE_ADDRESS; + eeprom_printf("eeprom_clear empty_slot: 0x%08x\n", (uint32_t)empty_slot); +} + +/* Erase emulated eeprom */ +void EEPROM_Erase(void) { + eeprom_println("EEPROM_Erase"); + /* Erase compacted pages and write log */ + eeprom_clear(); + /* re-initialize to reset DataBuf */ + EEPROM_Init(); +} + +/* Compact write log */ +static uint8_t eeprom_compact(void) { + /* Erase compacted pages and write log */ + eeprom_clear(); + + FLASH_Unlock(); + + FLASH_Status final_status = FLASH_COMPLETE; + + /* Write emulated eeprom contents from memory to compacted flash */ + uint16_t *src = (uint16_t *)DataBuf; + uintptr_t dest = FEE_COMPACTED_BASE_ADDRESS; + uint16_t value; + for (; dest < FEE_COMPACTED_LAST_ADDRESS; ++src, dest += 2) { + value = *src; + if (value) { + eeprom_printf("FLASH_ProgramHalfWord(0x%04x, 0x%04x)\n", (uint32_t)dest, ~value); + FLASH_Status status = FLASH_ProgramHalfWord(dest, ~value); + if (status != FLASH_COMPLETE) final_status = status; + } + } + + FLASH_Lock(); + + if (debug_eeprom) { + println("eeprom_compacted:"); + print_eeprom(); + } + + return final_status; +} + +static uint8_t eeprom_write_direct_entry(uint16_t Address) { + /* Check if we can just write this directly to the compacted flash area */ + uintptr_t directAddress = FEE_COMPACTED_BASE_ADDRESS + (Address & 0xFFFE); + if (*(uint16_t *)directAddress == FEE_EMPTY_WORD) { + /* Write the value directly to the compacted area without a log entry */ + uint16_t value = ~*(uint16_t *)(&DataBuf[Address & 0xFFFE]); + /* Early exit if a write isn't needed */ + if (value == FEE_EMPTY_WORD) return FLASH_COMPLETE; + + FLASH_Unlock(); + + eeprom_printf("FLASH_ProgramHalfWord(0x%08x, 0x%04x) [DIRECT]\n", (uint32_t)directAddress, value); + FLASH_Status status = FLASH_ProgramHalfWord(directAddress, value); + + FLASH_Lock(); + return status; + } + return 0; +} + +static uint8_t eeprom_write_log_word_entry(uint16_t Address) { + FLASH_Status final_status = FLASH_COMPLETE; + + uint16_t value = *(uint16_t *)(&DataBuf[Address]); + eeprom_printf("eeprom_write_log_word_entry(0x%04x): 0x%04x\n", Address, value); + + /* MSB signifies the lowest 128-byte optimization is not in effect */ + uint16_t encoding = FEE_WORD_ENCODING; + uint8_t entry_size; + if (value <= 1) { + encoding |= value << 13; + entry_size = 2; + } else { + encoding |= FEE_VALUE_NEXT; + entry_size = 4; + /* Writes to addresses less than 128 are byte log entries */ + Address -= FEE_BYTE_RANGE; + } + + /* if we can't find an empty spot, we must compact emulated eeprom */ + if (empty_slot > (uint16_t *)(FEE_WRITE_LOG_LAST_ADDRESS - entry_size)) { + /* compact the write log into the compacted flash area */ + return eeprom_compact(); + } + + /* Word log writes should be word-aligned. Take back a bit */ + Address >>= 1; + Address |= encoding; + + /* ok we found a place let's write our data */ + FLASH_Unlock(); + + /* address */ + eeprom_printf("FLASH_ProgramHalfWord(0x%08x, 0x%04x)\n", (uint32_t)empty_slot, Address); + final_status = FLASH_ProgramHalfWord((uintptr_t)empty_slot++, Address); + + /* value */ + if (encoding == (FEE_WORD_ENCODING | FEE_VALUE_NEXT)) { + eeprom_printf("FLASH_ProgramHalfWord(0x%08x, 0x%04x)\n", (uint32_t)empty_slot, ~value); + FLASH_Status status = FLASH_ProgramHalfWord((uintptr_t)empty_slot++, ~value); + if (status != FLASH_COMPLETE) final_status = status; + } + + FLASH_Lock(); + + return final_status; +} + +static uint8_t eeprom_write_log_byte_entry(uint16_t Address) { + eeprom_printf("eeprom_write_log_byte_entry(0x%04x): 0x%02x\n", Address, DataBuf[Address]); + + /* if couldn't find an empty spot, we must compact emulated eeprom */ + if (empty_slot >= (uint16_t *)FEE_WRITE_LOG_LAST_ADDRESS) { + /* compact the write log into the compacted flash area */ + return eeprom_compact(); + } + + /* ok we found a place let's write our data */ + FLASH_Unlock(); + + /* Pack address and value into the same word */ + uint16_t value = (Address << 8) | DataBuf[Address]; + + /* write to flash */ + eeprom_printf("FLASH_ProgramHalfWord(0x%08x, 0x%04x)\n", (uint32_t)empty_slot, value); + FLASH_Status status = FLASH_ProgramHalfWord((uintptr_t)empty_slot++, value); + + FLASH_Lock(); + + return status; +} + +uint8_t EEPROM_WriteDataByte(uint16_t Address, uint8_t DataByte) { + /* if the address is out-of-bounds, do nothing */ + if (Address >= FEE_DENSITY_BYTES) { + eeprom_printf("EEPROM_WriteDataByte(0x%04x, 0x%02x) [BAD ADDRESS]\n", Address, DataByte); + return FLASH_BAD_ADDRESS; + } + + /* if the value is the same, don't bother writing it */ + if (DataBuf[Address] == DataByte) { + eeprom_printf("EEPROM_WriteDataByte(0x%04x, 0x%02x) [SKIP SAME]\n", Address, DataByte); + return 0; + } + + /* keep DataBuf cache in sync */ + DataBuf[Address] = DataByte; + eeprom_printf("EEPROM_WriteDataByte DataBuf[0x%04x] = 0x%02x\n", Address, DataBuf[Address]); + + /* perform the write into flash memory */ + /* First, attempt to write directly into the compacted flash area */ + FLASH_Status status = eeprom_write_direct_entry(Address); + if (!status) { + /* Otherwise append to the write log */ + if (Address < FEE_BYTE_RANGE) { + status = eeprom_write_log_byte_entry(Address); + } else { + status = eeprom_write_log_word_entry(Address & 0xFFFE); + } + } + if (status != 0 && status != FLASH_COMPLETE) { + eeprom_printf("EEPROM_WriteDataByte [STATUS == %d]\n", status); + } + return status; +} + +uint8_t EEPROM_WriteDataWord(uint16_t Address, uint16_t DataWord) { + /* if the address is out-of-bounds, do nothing */ + if (Address >= FEE_DENSITY_BYTES) { + eeprom_printf("EEPROM_WriteDataWord(0x%04x, 0x%04x) [BAD ADDRESS]\n", Address, DataWord); + return FLASH_BAD_ADDRESS; + } + + /* Check for word alignment */ + FLASH_Status final_status = FLASH_COMPLETE; + if (Address % 2) { + final_status = EEPROM_WriteDataByte(Address, DataWord); + FLASH_Status status = EEPROM_WriteDataByte(Address + 1, DataWord >> 8); + if (status != FLASH_COMPLETE) final_status = status; + if (final_status != 0 && final_status != FLASH_COMPLETE) { + eeprom_printf("EEPROM_WriteDataWord [STATUS == %d]\n", final_status); + } + return final_status; + } + + /* if the value is the same, don't bother writing it */ + uint16_t oldValue = *(uint16_t *)(&DataBuf[Address]); + if (oldValue == DataWord) { + eeprom_printf("EEPROM_WriteDataWord(0x%04x, 0x%04x) [SKIP SAME]\n", Address, DataWord); + return 0; + } + + /* keep DataBuf cache in sync */ + *(uint16_t *)(&DataBuf[Address]) = DataWord; + eeprom_printf("EEPROM_WriteDataWord DataBuf[0x%04x] = 0x%04x\n", Address, *(uint16_t *)(&DataBuf[Address])); + + /* perform the write into flash memory */ + /* First, attempt to write directly into the compacted flash area */ + final_status = eeprom_write_direct_entry(Address); + if (!final_status) { + /* Otherwise append to the write log */ + /* Check if we need to fall back to byte write */ + if (Address < FEE_BYTE_RANGE) { + final_status = FLASH_COMPLETE; + /* Only write a byte if it has changed */ + if ((uint8_t)oldValue != (uint8_t)DataWord) { + final_status = eeprom_write_log_byte_entry(Address); + } + FLASH_Status status = FLASH_COMPLETE; + /* Only write a byte if it has changed */ + if ((oldValue >> 8) != (DataWord >> 8)) { + status = eeprom_write_log_byte_entry(Address + 1); + } + if (status != FLASH_COMPLETE) final_status = status; + } else { + final_status = eeprom_write_log_word_entry(Address); + } + } + if (final_status != 0 && final_status != FLASH_COMPLETE) { + eeprom_printf("EEPROM_WriteDataWord [STATUS == %d]\n", final_status); + } + return final_status; +} + +uint8_t EEPROM_ReadDataByte(uint16_t Address) { + uint8_t DataByte = 0xFF; + + if (Address < FEE_DENSITY_BYTES) { + DataByte = DataBuf[Address]; + } + + eeprom_printf("EEPROM_ReadDataByte(0x%04x): 0x%02x\n", Address, DataByte); + + return DataByte; +} + +uint16_t EEPROM_ReadDataWord(uint16_t Address) { + uint16_t DataWord = 0xFFFF; + + if (Address < FEE_DENSITY_BYTES - 1) { + /* Check word alignment */ + if (Address % 2) { + DataWord = DataBuf[Address] | (DataBuf[Address + 1] << 8); + } else { + DataWord = *(uint16_t *)(&DataBuf[Address]); + } + } + + eeprom_printf("EEPROM_ReadDataWord(0x%04x): 0x%04x\n", Address, DataWord); + + return DataWord; +} + +/***************************************************************************** + * Bind to eeprom_driver.c + *******************************************************************************/ +void eeprom_driver_init(void) { EEPROM_Init(); } + +void eeprom_driver_erase(void) { EEPROM_Erase(); } + +void eeprom_read_block(void *buf, const void *addr, size_t len) { + const uint8_t *src = (const uint8_t *)addr; + uint8_t * dest = (uint8_t *)buf; + + /* Check word alignment */ + if (len && (uintptr_t)src % 2) { + /* Read the unaligned first byte */ + *dest++ = EEPROM_ReadDataByte((const uintptr_t)src++); + --len; + } + + uint16_t value; + bool aligned = ((uintptr_t)dest % 2 == 0); + while (len > 1) { + value = EEPROM_ReadDataWord((const uintptr_t)((uint16_t *)src)); + if (aligned) { + *(uint16_t *)dest = value; + dest += 2; + } else { + *dest++ = value; + *dest++ = value >> 8; + } + src += 2; + len -= 2; + } + if (len) { + *dest = EEPROM_ReadDataByte((const uintptr_t)src); + } +} + +void eeprom_write_block(const void *buf, void *addr, size_t len) { + uint8_t * dest = (uint8_t *)addr; + const uint8_t *src = (const uint8_t *)buf; + + /* Check word alignment */ + if (len && (uintptr_t)dest % 2) { + /* Write the unaligned first byte */ + EEPROM_WriteDataByte((uintptr_t)dest++, *src++); + --len; + } + + uint16_t value; + bool aligned = ((uintptr_t)src % 2 == 0); + while (len > 1) { + if (aligned) { + value = *(uint16_t *)src; + } else { + value = *(uint8_t *)src | (*(uint8_t *)(src + 1) << 8); + } + EEPROM_WriteDataWord((uintptr_t)((uint16_t *)dest), value); + dest += 2; + src += 2; + len -= 2; + } + + if (len) { + EEPROM_WriteDataByte((uintptr_t)dest, *src); + } +} diff --git a/platforms/chibios/eeprom_stm32.h b/platforms/chibios/eeprom_stm32.h new file mode 100644 index 0000000000..8fcfb556b8 --- /dev/null +++ b/platforms/chibios/eeprom_stm32.h @@ -0,0 +1,33 @@ +/* + * This software is experimental and a work in progress. + * Under no circumstances should these files be used in relation to any critical system(s). + * Use of these files is at your own risk. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR + * PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This files are free to use from http://engsta.com/stm32-flash-memory-eeprom-emulator/ by + * Artur F. + * + * Modifications for QMK and STM32F303 by Yiancar + * + * This library assumes 8-bit data locations. To add a new MCU, please provide the flash + * page size and the total flash size in Kb. The number of available pages must be a multiple + * of 2. Only half of the pages account for the total EEPROM size. + * This library also assumes that the pages are not used by the firmware. + */ + +#pragma once + +uint16_t EEPROM_Init(void); +void EEPROM_Erase(void); +uint8_t EEPROM_WriteDataByte(uint16_t Address, uint8_t DataByte); +uint8_t EEPROM_WriteDataWord(uint16_t Address, uint16_t DataWord); +uint8_t EEPROM_ReadDataByte(uint16_t Address); +uint16_t EEPROM_ReadDataWord(uint16_t Address); + +void print_eeprom(void); diff --git a/platforms/chibios/eeprom_stm32_defs.h b/platforms/chibios/eeprom_stm32_defs.h new file mode 100644 index 0000000000..66904f247f --- /dev/null +++ b/platforms/chibios/eeprom_stm32_defs.h @@ -0,0 +1,74 @@ +/* Copyright 2021 QMK + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#pragma once + +#include + +#if !defined(FEE_PAGE_SIZE) || !defined(FEE_PAGE_COUNT) +# if defined(STM32F103xB) || defined(STM32F042x6) || defined(GD32VF103C8) || defined(GD32VF103CB) +# ifndef FEE_PAGE_SIZE +# define FEE_PAGE_SIZE 0x400 // Page size = 1KByte +# endif +# ifndef FEE_PAGE_COUNT +# define FEE_PAGE_COUNT 2 // How many pages are used +# endif +# elif defined(STM32F103xE) || defined(STM32F303xC) || defined(STM32F072xB) || defined(STM32F070xB) +# ifndef FEE_PAGE_SIZE +# define FEE_PAGE_SIZE 0x800 // Page size = 2KByte +# endif +# ifndef FEE_PAGE_COUNT +# define FEE_PAGE_COUNT 4 // How many pages are used +# endif +# elif defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xG) || defined(STM32F411xE) +# ifndef FEE_PAGE_SIZE +# define FEE_PAGE_SIZE 0x4000 // Page size = 16KByte +# endif +# ifndef FEE_PAGE_COUNT +# define FEE_PAGE_COUNT 1 // How many pages are used +# endif +# endif +#endif + +#if !defined(FEE_MCU_FLASH_SIZE) +# if defined(STM32F042x6) +# define FEE_MCU_FLASH_SIZE 32 // Size in Kb +# elif defined(GD32VF103C8) +# define FEE_MCU_FLASH_SIZE 64 // Size in Kb +# elif defined(STM32F103xB) || defined(STM32F072xB) || defined(STM32F070xB) || defined(GD32VF103CB) +# define FEE_MCU_FLASH_SIZE 128 // Size in Kb +# elif defined(STM32F303xC) || defined(STM32F401xC) +# define FEE_MCU_FLASH_SIZE 256 // Size in Kb +# elif defined(STM32F103xE) || defined(STM32F401xE) || defined(STM32F411xE) +# define FEE_MCU_FLASH_SIZE 512 // Size in Kb +# elif defined(STM32F405xG) +# define FEE_MCU_FLASH_SIZE 1024 // Size in Kb +# endif +#endif + +/* Start of the emulated eeprom */ +#if !defined(FEE_PAGE_BASE_ADDRESS) +# if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xG) || defined(STM32F411xE) +# ifndef FEE_PAGE_BASE_ADDRESS +# define FEE_PAGE_BASE_ADDRESS 0x08004000 // bodge to force 2nd 16k page +# endif +# else +# ifndef FEE_FLASH_BASE +# define FEE_FLASH_BASE 0x8000000 +# endif +/* Default to end of flash */ +# define FEE_PAGE_BASE_ADDRESS ((uintptr_t)(FEE_FLASH_BASE) + FEE_MCU_FLASH_SIZE * 1024 - (FEE_PAGE_COUNT * FEE_PAGE_SIZE)) +# endif +#endif diff --git a/platforms/chibios/eeprom_teensy.c b/platforms/chibios/eeprom_teensy.c new file mode 100644 index 0000000000..97da6f9e14 --- /dev/null +++ b/platforms/chibios/eeprom_teensy.c @@ -0,0 +1,795 @@ +#include +#include + +#include "eeconfig.h" + +/*************************************/ +/* Hardware backend */ +/* */ +/* Code from PJRC/Teensyduino */ +/*************************************/ + +/* Teensyduino Core Library + * http://www.pjrc.com/teensy/ + * Copyright (c) 2013 PJRC.COM, LLC. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * 1. The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * 2. If the Software is incorporated into a build system that allows + * selection among a list of target devices, then similar target + * devices manufactured by PJRC.COM must be included in the list of + * target devices and selectable in the same manner. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#define SMC_PMSTAT_RUN ((uint8_t)0x01) +#define SMC_PMSTAT_HSRUN ((uint8_t)0x80) + +#define F_CPU KINETIS_SYSCLK_FREQUENCY + +static inline int kinetis_hsrun_disable(void) { +#if defined(MK66F18) + if (SMC->PMSTAT == SMC_PMSTAT_HSRUN) { +// First, reduce the CPU clock speed, but do not change +// the peripheral speed (F_BUS). Serial1 & Serial2 baud +// rates will be impacted, but most other peripherals +// will continue functioning at the same speed. +# if F_CPU == 256000000 && F_BUS == 64000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 3, 1, 7); // TODO: TEST +# elif F_CPU == 256000000 && F_BUS == 128000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 1, 1, 7); // TODO: TEST +# elif F_CPU == 240000000 && F_BUS == 60000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 3, 1, 7); // ok +# elif F_CPU == 240000000 && F_BUS == 80000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(2, 2, 2, 8); // ok +# elif F_CPU == 240000000 && F_BUS == 120000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 1, 1, 7); // ok +# elif F_CPU == 216000000 && F_BUS == 54000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 3, 1, 7); // ok +# elif F_CPU == 216000000 && F_BUS == 72000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(2, 2, 2, 8); // ok +# elif F_CPU == 216000000 && F_BUS == 108000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 1, 1, 7); // ok +# elif F_CPU == 192000000 && F_BUS == 48000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 3, 1, 7); // ok +# elif F_CPU == 192000000 && F_BUS == 64000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(2, 2, 2, 8); // ok +# elif F_CPU == 192000000 && F_BUS == 96000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 1, 1, 7); // ok +# elif F_CPU == 180000000 && F_BUS == 60000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(2, 2, 2, 8); // ok +# elif F_CPU == 180000000 && F_BUS == 90000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 1, 1, 7); // ok +# elif F_CPU == 168000000 && F_BUS == 56000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(2, 2, 2, 5); // ok +# elif F_CPU == 144000000 && F_BUS == 48000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(2, 2, 2, 5); // ok +# elif F_CPU == 144000000 && F_BUS == 72000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 1, 1, 5); // ok +# elif F_CPU == 120000000 && F_BUS == 60000000 + SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1 - 1) | SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2 - 1) | +# if defined(MK66F18) + SIM_CLKDIV1_OUTDIV3(KINETIS_CLKDIV1_OUTDIV3 - 1) | +# endif + SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4 - 1); +# else + return 0; +# endif + // Then turn off HSRUN mode + SMC->PMCTRL = SMC_PMCTRL_RUNM_SET(0); + while (SMC->PMSTAT == SMC_PMSTAT_HSRUN) + ; // wait + return 1; + } +#endif + return 0; +} + +static inline int kinetis_hsrun_enable(void) { +#if defined(MK66F18) + if (SMC->PMSTAT == SMC_PMSTAT_RUN) { + // Turn HSRUN mode on + SMC->PMCTRL = SMC_PMCTRL_RUNM_SET(3); + while (SMC->PMSTAT != SMC_PMSTAT_HSRUN) { + ; + } // wait +// Then configure clock for full speed +# if F_CPU == 256000000 && F_BUS == 64000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 3, 0, 7); +# elif F_CPU == 256000000 && F_BUS == 128000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 1, 0, 7); +# elif F_CPU == 240000000 && F_BUS == 60000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 3, 0, 7); +# elif F_CPU == 240000000 && F_BUS == 80000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 2, 0, 7); +# elif F_CPU == 240000000 && F_BUS == 120000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 1, 0, 7); +# elif F_CPU == 216000000 && F_BUS == 54000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 3, 0, 7); +# elif F_CPU == 216000000 && F_BUS == 72000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 2, 0, 7); +# elif F_CPU == 216000000 && F_BUS == 108000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 1, 0, 7); +# elif F_CPU == 192000000 && F_BUS == 48000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 3, 0, 6); +# elif F_CPU == 192000000 && F_BUS == 64000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 2, 0, 6); +# elif F_CPU == 192000000 && F_BUS == 96000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 1, 0, 6); +# elif F_CPU == 180000000 && F_BUS == 60000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 2, 0, 6); +# elif F_CPU == 180000000 && F_BUS == 90000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 1, 0, 6); +# elif F_CPU == 168000000 && F_BUS == 56000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 2, 0, 5); +# elif F_CPU == 144000000 && F_BUS == 48000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 2, 0, 4); +# elif F_CPU == 144000000 && F_BUS == 72000000 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 1, 0, 4); +# elif F_CPU == 120000000 && F_BUS == 60000000 + SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1 - 1) | SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2 - 1) | +# if defined(MK66F18) + SIM_CLKDIV1_OUTDIV3(KINETIS_CLKDIV1_OUTDIV3 - 1) | +# endif + SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4 - 1); +# else + return 0; +# endif + return 1; + } +#endif + return 0; +} + +#if defined(K20x) || defined(MK66F18) /* chip selection */ +/* Teensy 3.0, 3.1, 3.2; mchck; infinity keyboard */ + +// The EEPROM is really RAM with a hardware-based backup system to +// flash memory. Selecting a smaller size EEPROM allows more wear +// leveling, for higher write endurance. If you edit this file, +// set this to the smallest size your application can use. Also, +// due to Freescale's implementation, writing 16 or 32 bit words +// (aligned to 2 or 4 byte boundaries) has twice the endurance +// compared to writing 8 bit bytes. +// +# ifndef EEPROM_SIZE +# define EEPROM_SIZE 32 +# endif + +/* + ^^^ Here be dragons: + NXP AppNote AN4282 section 3.1 states that partitioning must only be done once. + Once EEPROM partitioning is done, the size is locked to this initial configuration. + Attempts to modify the EEPROM_SIZE setting may brick your board. +*/ + +// Writing unaligned 16 or 32 bit data is handled automatically when +// this is defined, but at a cost of extra code size. Without this, +// any unaligned write will cause a hard fault exception! If you're +// absolutely sure all 16 and 32 bit writes will be aligned, you can +// remove the extra unnecessary code. +// +# define HANDLE_UNALIGNED_WRITES + +# if defined(K20x) +# define EEPROM_MAX 2048 +# define EEPARTITION 0x03 // all 32K dataflash for EEPROM, none for Data +# define EEESPLIT 0x30 // must be 0x30 on these chips +# elif defined(MK66F18) +# define EEPROM_MAX 4096 +# define EEPARTITION 0x05 // 128K dataflash for EEPROM, 128K for Data +# define EEESPLIT 0x10 // best endurance: 0x00 = first 12%, 0x10 = first 25%, 0x30 = all equal +# endif + +// Minimum EEPROM Endurance +// ------------------------ +# if (EEPROM_SIZE == 4096) +# define EEESIZE 0x02 +# elif (EEPROM_SIZE == 2048) // 35000 writes/byte or 70000 writes/word +# define EEESIZE 0x03 +# elif (EEPROM_SIZE == 1024) // 75000 writes/byte or 150000 writes/word +# define EEESIZE 0x04 +# elif (EEPROM_SIZE == 512) // 155000 writes/byte or 310000 writes/word +# define EEESIZE 0x05 +# elif (EEPROM_SIZE == 256) // 315000 writes/byte or 630000 writes/word +# define EEESIZE 0x06 +# elif (EEPROM_SIZE == 128) // 635000 writes/byte or 1270000 writes/word +# define EEESIZE 0x07 +# elif (EEPROM_SIZE == 64) // 1275000 writes/byte or 2550000 writes/word +# define EEESIZE 0x08 +# elif (EEPROM_SIZE == 32) // 2555000 writes/byte or 5110000 writes/word +# define EEESIZE 0x09 +# endif + +/** \brief eeprom initialization + * + * FIXME: needs doc + */ +void eeprom_initialize(void) { + uint32_t count = 0; + uint16_t do_flash_cmd[] = {0xf06f, 0x037f, 0x7003, 0x7803, 0xf013, 0x0f80, 0xd0fb, 0x4770}; + uint8_t status; + + if (FTFL->FCNFG & FTFL_FCNFG_RAMRDY) { + uint8_t stat = FTFL->FSTAT & 0x70; + if (stat) FTFL->FSTAT = stat; + + // FlexRAM is configured as traditional RAM + // We need to reconfigure for EEPROM usage + kinetis_hsrun_disable(); + FTFL->FCCOB0 = 0x80; // PGMPART = Program Partition Command + FTFL->FCCOB3 = 0; + FTFL->FCCOB4 = EEESPLIT | EEESIZE; + FTFL->FCCOB5 = EEPARTITION; + __disable_irq(); + // do_flash_cmd() must execute from RAM. Luckily the C syntax is simple... + (*((void (*)(volatile uint8_t *))((uint32_t)do_flash_cmd | 1)))(&(FTFL->FSTAT)); + __enable_irq(); + kinetis_hsrun_enable(); + status = FTFL->FSTAT; + if (status & (FTFL_FSTAT_RDCOLERR | FTFL_FSTAT_ACCERR | FTFL_FSTAT_FPVIOL)) { + FTFL->FSTAT = (status & (FTFL_FSTAT_RDCOLERR | FTFL_FSTAT_ACCERR | FTFL_FSTAT_FPVIOL)); + return; // error + } + } + // wait for eeprom to become ready (is this really necessary?) + while (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) { + if (++count > 200000) break; + } +} + +# define FlexRAM ((volatile uint8_t *)0x14000000) + +/** \brief eeprom read byte + * + * FIXME: needs doc + */ +uint8_t eeprom_read_byte(const uint8_t *addr) { + uint32_t offset = (uint32_t)addr; + if (offset >= EEPROM_SIZE) return 0; + if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize(); + return FlexRAM[offset]; +} + +/** \brief eeprom read word + * + * FIXME: needs doc + */ +uint16_t eeprom_read_word(const uint16_t *addr) { + uint32_t offset = (uint32_t)addr; + if (offset >= EEPROM_SIZE - 1) return 0; + if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize(); + return *(uint16_t *)(&FlexRAM[offset]); +} + +/** \brief eeprom read dword + * + * FIXME: needs doc + */ +uint32_t eeprom_read_dword(const uint32_t *addr) { + uint32_t offset = (uint32_t)addr; + if (offset >= EEPROM_SIZE - 3) return 0; + if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize(); + return *(uint32_t *)(&FlexRAM[offset]); +} + +/** \brief eeprom read block + * + * FIXME: needs doc + */ +void eeprom_read_block(void *buf, const void *addr, uint32_t len) { + uint32_t offset = (uint32_t)addr; + uint8_t *dest = (uint8_t *)buf; + uint32_t end = offset + len; + + if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize(); + if (end > EEPROM_SIZE) end = EEPROM_SIZE; + while (offset < end) { + *dest++ = FlexRAM[offset++]; + } +} + +/** \brief eeprom is ready + * + * FIXME: needs doc + */ +int eeprom_is_ready(void) { return (FTFL->FCNFG & FTFL_FCNFG_EEERDY) ? 1 : 0; } + +/** \brief flexram wait + * + * FIXME: needs doc + */ +static void flexram_wait(void) { + while (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) { + // TODO: timeout + } +} + +/** \brief eeprom_write_byte + * + * FIXME: needs doc + */ +void eeprom_write_byte(uint8_t *addr, uint8_t value) { + uint32_t offset = (uint32_t)addr; + + if (offset >= EEPROM_SIZE) return; + if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize(); + if (FlexRAM[offset] != value) { + kinetis_hsrun_disable(); + uint8_t stat = FTFL->FSTAT & 0x70; + if (stat) FTFL->FSTAT = stat; + FlexRAM[offset] = value; + flexram_wait(); + kinetis_hsrun_enable(); + } +} + +/** \brief eeprom write word + * + * FIXME: needs doc + */ +void eeprom_write_word(uint16_t *addr, uint16_t value) { + uint32_t offset = (uint32_t)addr; + + if (offset >= EEPROM_SIZE - 1) return; + if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize(); +# ifdef HANDLE_UNALIGNED_WRITES + if ((offset & 1) == 0) { +# endif + if (*(uint16_t *)(&FlexRAM[offset]) != value) { + kinetis_hsrun_disable(); + uint8_t stat = FTFL->FSTAT & 0x70; + if (stat) FTFL->FSTAT = stat; + *(uint16_t *)(&FlexRAM[offset]) = value; + flexram_wait(); + kinetis_hsrun_enable(); + } +# ifdef HANDLE_UNALIGNED_WRITES + } else { + if (FlexRAM[offset] != value) { + kinetis_hsrun_disable(); + uint8_t stat = FTFL->FSTAT & 0x70; + if (stat) FTFL->FSTAT = stat; + FlexRAM[offset] = value; + flexram_wait(); + kinetis_hsrun_enable(); + } + if (FlexRAM[offset + 1] != (value >> 8)) { + kinetis_hsrun_disable(); + uint8_t stat = FTFL->FSTAT & 0x70; + if (stat) FTFL->FSTAT = stat; + FlexRAM[offset + 1] = value >> 8; + flexram_wait(); + kinetis_hsrun_enable(); + } + } +# endif +} + +/** \brief eeprom write dword + * + * FIXME: needs doc + */ +void eeprom_write_dword(uint32_t *addr, uint32_t value) { + uint32_t offset = (uint32_t)addr; + + if (offset >= EEPROM_SIZE - 3) return; + if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize(); +# ifdef HANDLE_UNALIGNED_WRITES + switch (offset & 3) { + case 0: +# endif + if (*(uint32_t *)(&FlexRAM[offset]) != value) { + kinetis_hsrun_disable(); + uint8_t stat = FTFL->FSTAT & 0x70; + if (stat) FTFL->FSTAT = stat; + *(uint32_t *)(&FlexRAM[offset]) = value; + flexram_wait(); + kinetis_hsrun_enable(); + } + return; +# ifdef HANDLE_UNALIGNED_WRITES + case 2: + if (*(uint16_t *)(&FlexRAM[offset]) != value) { + kinetis_hsrun_disable(); + uint8_t stat = FTFL->FSTAT & 0x70; + if (stat) FTFL->FSTAT = stat; + *(uint16_t *)(&FlexRAM[offset]) = value; + flexram_wait(); + kinetis_hsrun_enable(); + } + if (*(uint16_t *)(&FlexRAM[offset + 2]) != (value >> 16)) { + kinetis_hsrun_disable(); + uint8_t stat = FTFL->FSTAT & 0x70; + if (stat) FTFL->FSTAT = stat; + *(uint16_t *)(&FlexRAM[offset + 2]) = value >> 16; + flexram_wait(); + kinetis_hsrun_enable(); + } + return; + default: + if (FlexRAM[offset] != value) { + kinetis_hsrun_disable(); + uint8_t stat = FTFL->FSTAT & 0x70; + if (stat) FTFL->FSTAT = stat; + FlexRAM[offset] = value; + flexram_wait(); + kinetis_hsrun_enable(); + } + if (*(uint16_t *)(&FlexRAM[offset + 1]) != (value >> 8)) { + kinetis_hsrun_disable(); + uint8_t stat = FTFL->FSTAT & 0x70; + if (stat) FTFL->FSTAT = stat; + *(uint16_t *)(&FlexRAM[offset + 1]) = value >> 8; + flexram_wait(); + kinetis_hsrun_enable(); + } + if (FlexRAM[offset + 3] != (value >> 24)) { + kinetis_hsrun_disable(); + uint8_t stat = FTFL->FSTAT & 0x70; + if (stat) FTFL->FSTAT = stat; + FlexRAM[offset + 3] = value >> 24; + flexram_wait(); + kinetis_hsrun_enable(); + } + } +# endif +} + +/** \brief eeprom write block + * + * FIXME: needs doc + */ +void eeprom_write_block(const void *buf, void *addr, uint32_t len) { + uint32_t offset = (uint32_t)addr; + const uint8_t *src = (const uint8_t *)buf; + + if (offset >= EEPROM_SIZE) return; + if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize(); + if (len >= EEPROM_SIZE) len = EEPROM_SIZE; + if (offset + len >= EEPROM_SIZE) len = EEPROM_SIZE - offset; + kinetis_hsrun_disable(); + while (len > 0) { + uint32_t lsb = offset & 3; + if (lsb == 0 && len >= 4) { + // write aligned 32 bits + uint32_t val32; + val32 = *src++; + val32 |= (*src++ << 8); + val32 |= (*src++ << 16); + val32 |= (*src++ << 24); + if (*(uint32_t *)(&FlexRAM[offset]) != val32) { + uint8_t stat = FTFL->FSTAT & 0x70; + if (stat) FTFL->FSTAT = stat; + *(uint32_t *)(&FlexRAM[offset]) = val32; + flexram_wait(); + } + offset += 4; + len -= 4; + } else if ((lsb == 0 || lsb == 2) && len >= 2) { + // write aligned 16 bits + uint16_t val16; + val16 = *src++; + val16 |= (*src++ << 8); + if (*(uint16_t *)(&FlexRAM[offset]) != val16) { + uint8_t stat = FTFL->FSTAT & 0x70; + if (stat) FTFL->FSTAT = stat; + *(uint16_t *)(&FlexRAM[offset]) = val16; + flexram_wait(); + } + offset += 2; + len -= 2; + } else { + // write 8 bits + uint8_t val8 = *src++; + if (FlexRAM[offset] != val8) { + uint8_t stat = FTFL->FSTAT & 0x70; + if (stat) FTFL->FSTAT = stat; + FlexRAM[offset] = val8; + flexram_wait(); + } + offset++; + len--; + } + } + kinetis_hsrun_enable(); +} + +/* +void do_flash_cmd(volatile uint8_t *fstat) +{ + *fstat = 0x80; + while ((*fstat & 0x80) == 0) ; // wait +} +00000000 : + 0: f06f 037f mvn.w r3, #127 ; 0x7f + 4: 7003 strb r3, [r0, #0] + 6: 7803 ldrb r3, [r0, #0] + 8: f013 0f80 tst.w r3, #128 ; 0x80 + c: d0fb beq.n 6 + e: 4770 bx lr +*/ + +#elif defined(KL2x) /* chip selection */ +/* Teensy LC (emulated) */ + +# define SYMVAL(sym) (uint32_t)(((uint8_t *)&(sym)) - ((uint8_t *)0)) + +extern uint32_t __eeprom_workarea_start__; +extern uint32_t __eeprom_workarea_end__; + +# define EEPROM_SIZE 128 + +static uint32_t flashend = 0; + +void eeprom_initialize(void) { + const uint16_t *p = (uint16_t *)SYMVAL(__eeprom_workarea_start__); + + do { + if (*p++ == 0xFFFF) { + flashend = (uint32_t)(p - 2); + return; + } + } while (p < (uint16_t *)SYMVAL(__eeprom_workarea_end__)); + flashend = (uint32_t)(p - 1); +} + +uint8_t eeprom_read_byte(const uint8_t *addr) { + uint32_t offset = (uint32_t)addr; + const uint16_t *p = (uint16_t *)SYMVAL(__eeprom_workarea_start__); + const uint16_t *end = (const uint16_t *)((uint32_t)flashend); + uint16_t val; + uint8_t data = 0xFF; + + if (!end) { + eeprom_initialize(); + end = (const uint16_t *)((uint32_t)flashend); + } + if (offset < EEPROM_SIZE) { + while (p <= end) { + val = *p++; + if ((val & 255) == offset) data = val >> 8; + } + } + return data; +} + +static void flash_write(const uint16_t *code, uint32_t addr, uint32_t data) { + // with great power comes great responsibility.... + uint32_t stat; + *(uint32_t *)&(FTFA->FCCOB3) = 0x06000000 | (addr & 0x00FFFFFC); + *(uint32_t *)&(FTFA->FCCOB7) = data; + __disable_irq(); + (*((void (*)(volatile uint8_t *))((uint32_t)code | 1)))(&(FTFA->FSTAT)); + __enable_irq(); + stat = FTFA->FSTAT & (FTFA_FSTAT_RDCOLERR | FTFA_FSTAT_ACCERR | FTFA_FSTAT_FPVIOL); + if (stat) { + FTFA->FSTAT = stat; + } + MCM->PLACR |= MCM_PLACR_CFCC; +} + +void eeprom_write_byte(uint8_t *addr, uint8_t data) { + uint32_t offset = (uint32_t)addr; + const uint16_t *p, *end = (const uint16_t *)((uint32_t)flashend); + uint32_t i, val, flashaddr; + uint16_t do_flash_cmd[] = {0x2380, 0x7003, 0x7803, 0xb25b, 0x2b00, 0xdafb, 0x4770}; + uint8_t buf[EEPROM_SIZE]; + + if (offset >= EEPROM_SIZE) return; + if (!end) { + eeprom_initialize(); + end = (const uint16_t *)((uint32_t)flashend); + } + if (++end < (uint16_t *)SYMVAL(__eeprom_workarea_end__)) { + val = (data << 8) | offset; + flashaddr = (uint32_t)end; + flashend = flashaddr; + if ((flashaddr & 2) == 0) { + val |= 0xFFFF0000; + } else { + val <<= 16; + val |= 0x0000FFFF; + } + flash_write(do_flash_cmd, flashaddr, val); + } else { + for (i = 0; i < EEPROM_SIZE; i++) { + buf[i] = 0xFF; + } + val = 0; + for (p = (uint16_t *)SYMVAL(__eeprom_workarea_start__); p < (uint16_t *)SYMVAL(__eeprom_workarea_end__); p++) { + val = *p; + if ((val & 255) < EEPROM_SIZE) { + buf[val & 255] = val >> 8; + } + } + buf[offset] = data; + for (flashaddr = (uint32_t)(uint16_t *)SYMVAL(__eeprom_workarea_start__); flashaddr < (uint32_t)(uint16_t *)SYMVAL(__eeprom_workarea_end__); flashaddr += 1024) { + *(uint32_t *)&(FTFA->FCCOB3) = 0x09000000 | flashaddr; + __disable_irq(); + (*((void (*)(volatile uint8_t *))((uint32_t)do_flash_cmd | 1)))(&(FTFA->FSTAT)); + __enable_irq(); + val = FTFA->FSTAT & (FTFA_FSTAT_RDCOLERR | FTFA_FSTAT_ACCERR | FTFA_FSTAT_FPVIOL); + ; + if (val) FTFA->FSTAT = val; + MCM->PLACR |= MCM_PLACR_CFCC; + } + flashaddr = (uint32_t)(uint16_t *)SYMVAL(__eeprom_workarea_start__); + for (i = 0; i < EEPROM_SIZE; i++) { + if (buf[i] == 0xFF) continue; + if ((flashaddr & 2) == 0) { + val = (buf[i] << 8) | i; + } else { + val = val | (buf[i] << 24) | (i << 16); + flash_write(do_flash_cmd, flashaddr, val); + } + flashaddr += 2; + } + flashend = flashaddr; + if ((flashaddr & 2)) { + val |= 0xFFFF0000; + flash_write(do_flash_cmd, flashaddr, val); + } + } +} + +/* +void do_flash_cmd(volatile uint8_t *fstat) +{ + *fstat = 0x80; + while ((*fstat & 0x80) == 0) ; // wait +} +00000000 : + 0: 2380 movs r3, #128 ; 0x80 + 2: 7003 strb r3, [r0, #0] + 4: 7803 ldrb r3, [r0, #0] + 6: b25b sxtb r3, r3 + 8: 2b00 cmp r3, #0 + a: dafb bge.n 4 + c: 4770 bx lr +*/ + +uint16_t eeprom_read_word(const uint16_t *addr) { + const uint8_t *p = (const uint8_t *)addr; + return eeprom_read_byte(p) | (eeprom_read_byte(p + 1) << 8); +} + +uint32_t eeprom_read_dword(const uint32_t *addr) { + const uint8_t *p = (const uint8_t *)addr; + return eeprom_read_byte(p) | (eeprom_read_byte(p + 1) << 8) | (eeprom_read_byte(p + 2) << 16) | (eeprom_read_byte(p + 3) << 24); +} + +void eeprom_read_block(void *buf, const void *addr, uint32_t len) { + const uint8_t *p = (const uint8_t *)addr; + uint8_t * dest = (uint8_t *)buf; + while (len--) { + *dest++ = eeprom_read_byte(p++); + } +} + +int eeprom_is_ready(void) { return 1; } + +void eeprom_write_word(uint16_t *addr, uint16_t value) { + uint8_t *p = (uint8_t *)addr; + eeprom_write_byte(p++, value); + eeprom_write_byte(p, value >> 8); +} + +void eeprom_write_dword(uint32_t *addr, uint32_t value) { + uint8_t *p = (uint8_t *)addr; + eeprom_write_byte(p++, value); + eeprom_write_byte(p++, value >> 8); + eeprom_write_byte(p++, value >> 16); + eeprom_write_byte(p, value >> 24); +} + +void eeprom_write_block(const void *buf, void *addr, uint32_t len) { + uint8_t * p = (uint8_t *)addr; + const uint8_t *src = (const uint8_t *)buf; + while (len--) { + eeprom_write_byte(p++, *src++); + } +} + +#else +// No EEPROM supported, so emulate it + +# ifndef EEPROM_SIZE +# include "eeconfig.h" +# define EEPROM_SIZE (((EECONFIG_SIZE + 3) / 4) * 4) // based off eeconfig's current usage, aligned to 4-byte sizes, to deal with LTO +# endif +__attribute__((aligned(4))) static uint8_t buffer[EEPROM_SIZE]; + +uint8_t eeprom_read_byte(const uint8_t *addr) { + uint32_t offset = (uint32_t)addr; + return buffer[offset]; +} + +void eeprom_write_byte(uint8_t *addr, uint8_t value) { + uint32_t offset = (uint32_t)addr; + buffer[offset] = value; +} + +uint16_t eeprom_read_word(const uint16_t *addr) { + const uint8_t *p = (const uint8_t *)addr; + return eeprom_read_byte(p) | (eeprom_read_byte(p + 1) << 8); +} + +uint32_t eeprom_read_dword(const uint32_t *addr) { + const uint8_t *p = (const uint8_t *)addr; + return eeprom_read_byte(p) | (eeprom_read_byte(p + 1) << 8) | (eeprom_read_byte(p + 2) << 16) | (eeprom_read_byte(p + 3) << 24); +} + +void eeprom_read_block(void *buf, const void *addr, size_t len) { + const uint8_t *p = (const uint8_t *)addr; + uint8_t * dest = (uint8_t *)buf; + while (len--) { + *dest++ = eeprom_read_byte(p++); + } +} + +void eeprom_write_word(uint16_t *addr, uint16_t value) { + uint8_t *p = (uint8_t *)addr; + eeprom_write_byte(p++, value); + eeprom_write_byte(p, value >> 8); +} + +void eeprom_write_dword(uint32_t *addr, uint32_t value) { + uint8_t *p = (uint8_t *)addr; + eeprom_write_byte(p++, value); + eeprom_write_byte(p++, value >> 8); + eeprom_write_byte(p++, value >> 16); + eeprom_write_byte(p, value >> 24); +} + +void eeprom_write_block(const void *buf, void *addr, size_t len) { + uint8_t * p = (uint8_t *)addr; + const uint8_t *src = (const uint8_t *)buf; + while (len--) { + eeprom_write_byte(p++, *src++); + } +} + +#endif /* chip selection */ +// The update functions just calls write for now, but could probably be optimized + +void eeprom_update_byte(uint8_t *addr, uint8_t value) { eeprom_write_byte(addr, value); } + +void eeprom_update_word(uint16_t *addr, uint16_t value) { + uint8_t *p = (uint8_t *)addr; + eeprom_write_byte(p++, value); + eeprom_write_byte(p, value >> 8); +} + +void eeprom_update_dword(uint32_t *addr, uint32_t value) { + uint8_t *p = (uint8_t *)addr; + eeprom_write_byte(p++, value); + eeprom_write_byte(p++, value >> 8); + eeprom_write_byte(p++, value >> 16); + eeprom_write_byte(p, value >> 24); +} + +void eeprom_update_block(const void *buf, void *addr, size_t len) { + uint8_t * p = (uint8_t *)addr; + const uint8_t *src = (const uint8_t *)buf; + while (len--) { + eeprom_write_byte(p++, *src++); + } +} diff --git a/platforms/chibios/flash_stm32.c b/platforms/chibios/flash_stm32.c new file mode 100644 index 0000000000..72c41b8b78 --- /dev/null +++ b/platforms/chibios/flash_stm32.c @@ -0,0 +1,208 @@ +/* + * This software is experimental and a work in progress. + * Under no circumstances should these files be used in relation to any critical system(s). + * Use of these files is at your own risk. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR + * PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This files are free to use from https://github.com/rogerclarkmelbourne/Arduino_STM32 and + * https://github.com/leaflabs/libmaple + * + * Modifications for QMK and STM32F303 by Yiancar + */ + +#include +#include "flash_stm32.h" + +#if defined(STM32F1XX) +# define FLASH_SR_WRPERR FLASH_SR_WRPRTERR +#endif + +#if defined(MCU_GD32V) +/* GigaDevice GD32VF103 is a STM32F103 clone at heart. */ +# include "gd32v_compatibility.h" +#endif + +#if defined(STM32F4XX) +# define FLASH_SR_PGERR (FLASH_SR_PGSERR | FLASH_SR_PGPERR | FLASH_SR_PGAERR) + +# define FLASH_KEY1 0x45670123U +# define FLASH_KEY2 0xCDEF89ABU + +static uint8_t ADDR2PAGE(uint32_t Page_Address) { + switch (Page_Address) { + case 0x08000000 ... 0x08003FFF: + return 0; + case 0x08004000 ... 0x08007FFF: + return 1; + case 0x08008000 ... 0x0800BFFF: + return 2; + case 0x0800C000 ... 0x0800FFFF: + return 3; + } + + // TODO: bad times... + return 7; +} +#endif + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x00000FFF) +#define ProgramTimeout ((uint32_t)0x0000001F) + +#define ASSERT(exp) (void)((0)) + +/** + * @brief Inserts a time delay. + * @param None + * @retval None + */ +static void delay(void) { + __IO uint32_t i = 0; + for (i = 0xFF; i != 0; i--) { + } +} + +/** + * @brief Returns the FLASH Status. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE + */ +FLASH_Status FLASH_GetStatus(void) { + if ((FLASH->SR & FLASH_SR_BSY) == FLASH_SR_BSY) return FLASH_BUSY; + + if ((FLASH->SR & FLASH_SR_PGERR) != 0) return FLASH_ERROR_PG; + + if ((FLASH->SR & FLASH_SR_WRPERR) != 0) return FLASH_ERROR_WRP; + +#if defined(FLASH_OBR_OPTERR) + if ((FLASH->SR & FLASH_OBR_OPTERR) != 0) return FLASH_ERROR_OPT; +#endif + + return FLASH_COMPLETE; +} + +/** + * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. + * @param Timeout: FLASH progamming Timeout + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) { + FLASH_Status status; + + /* Check for the Flash Status */ + status = FLASH_GetStatus(); + /* Wait for a Flash operation to complete or a TIMEOUT to occur */ + while ((status == FLASH_BUSY) && (Timeout != 0x00)) { + delay(); + status = FLASH_GetStatus(); + Timeout--; + } + if (Timeout == 0) status = FLASH_TIMEOUT; + /* Return the operation status */ + return status; +} + +/** + * @brief Erases a specified FLASH page. + * @param Page_Address: The page address to be erased. + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ErasePage(uint32_t Page_Address) { + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + ASSERT(IS_FLASH_ADDRESS(Page_Address)); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if (status == FLASH_COMPLETE) { + /* if the previous operation is completed, proceed to erase the page */ +#if defined(FLASH_CR_SNB) + FLASH->CR &= ~FLASH_CR_SNB; + FLASH->CR |= FLASH_CR_SER | (ADDR2PAGE(Page_Address) << FLASH_CR_SNB_Pos); +#else + FLASH->CR |= FLASH_CR_PER; + FLASH->AR = Page_Address; +#endif + FLASH->CR |= FLASH_CR_STRT; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if (status != FLASH_TIMEOUT) { + /* if the erase operation is completed, disable the configured Bits */ +#if defined(FLASH_CR_SNB) + FLASH->CR &= ~(FLASH_CR_SER | FLASH_CR_SNB); +#else + FLASH->CR &= ~FLASH_CR_PER; +#endif + } + FLASH->SR = (FLASH_SR_EOP | FLASH_SR_PGERR | FLASH_SR_WRPERR); + } + /* Return the Erase Status */ + return status; +} + +/** + * @brief Programs a half word at a specified address. + * @param Address: specifies the address to be programmed. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) { + FLASH_Status status = FLASH_BAD_ADDRESS; + + if (IS_FLASH_ADDRESS(Address)) { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if (status == FLASH_COMPLETE) { + /* if the previous operation is completed, proceed to program the new data */ + +#if defined(FLASH_CR_PSIZE) + FLASH->CR &= ~FLASH_CR_PSIZE; + FLASH->CR |= FLASH_CR_PSIZE_0; +#endif + FLASH->CR |= FLASH_CR_PG; + *(__IO uint16_t*)Address = Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if (status != FLASH_TIMEOUT) { + /* if the program operation is completed, disable the PG Bit */ + FLASH->CR &= ~FLASH_CR_PG; + } + FLASH->SR = (FLASH_SR_EOP | FLASH_SR_PGERR | FLASH_SR_WRPERR); + } + } + return status; +} + +/** + * @brief Unlocks the FLASH Program Erase Controller. + * @param None + * @retval None + */ +void FLASH_Unlock(void) { + if (FLASH->CR & FLASH_CR_LOCK) { + /* Authorize the FPEC Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + } +} + +/** + * @brief Locks the FLASH Program Erase Controller. + * @param None + * @retval None + */ +void FLASH_Lock(void) { + /* Set the Lock Bit to lock the FPEC and the FCR */ + FLASH->CR |= FLASH_CR_LOCK; +} diff --git a/platforms/chibios/flash_stm32.h b/platforms/chibios/flash_stm32.h new file mode 100644 index 0000000000..6c66642ec5 --- /dev/null +++ b/platforms/chibios/flash_stm32.h @@ -0,0 +1,44 @@ +/* + * This software is experimental and a work in progress. + * Under no circumstances should these files be used in relation to any critical system(s). + * Use of these files is at your own risk. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR + * PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This files are free to use from https://github.com/rogerclarkmelbourne/Arduino_STM32 and + * https://github.com/leaflabs/libmaple + * + * Modifications for QMK and STM32F303 by Yiancar + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#ifdef FLASH_STM32_MOCKED +extern uint8_t FlashBuf[MOCK_FLASH_SIZE]; +#endif + +typedef enum { FLASH_BUSY = 1, FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_ERROR_OPT, FLASH_COMPLETE, FLASH_TIMEOUT, FLASH_BAD_ADDRESS } FLASH_Status; + +#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF)) + +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); +FLASH_Status FLASH_ErasePage(uint32_t Page_Address); +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); + +void FLASH_Unlock(void); +void FLASH_Lock(void); + +#ifdef __cplusplus +} +#endif diff --git a/platforms/chibios/gd32v_compatibility.h b/platforms/chibios/gd32v_compatibility.h new file mode 100644 index 0000000000..f4dcfd8c55 --- /dev/null +++ b/platforms/chibios/gd32v_compatibility.h @@ -0,0 +1,120 @@ +/* Copyright 2021 QMK + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#pragma once + +/* GD32VF103 has the same API as STM32F103, but uses different names for literally the same thing. + * As of 23.7.2021 QMK is tailored to use STM32 defines/names, for compatibility sake + * we just redefine the GD32 names. */ + +/* Close your eyes kids. */ +#define MCU_STM32 + +/* AFIO redefines */ +#define MAPR PCF0 +#define AFIO_MAPR_USART1_REMAP AFIO_PCF0_USART0_REMAP +#define AFIO_MAPR_USART2_REMAP AFIO_PCF0_USART1_REMAP +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_PCF0_USART2_REMAP_PARTIALREMAP +#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_PCF0_USART2_REMAP_FULLREMAP + +/* DMA redefines. */ +#define STM32_DMA_STREAM(stream) GD32_DMA_STREAM(stream) +#define STM32_DMA_STREAM_ID(peripheral, channel) GD32_DMA_STREAM_ID(peripheral - 1, channel - 1) +#define STM32_DMA_CR_DIR_M2P GD32_DMA_CTL_DIR_M2P +#define STM32_DMA_CR_PSIZE_WORD GD32_DMA_CTL_PWIDTH_WORD +#define STM32_DMA_CR_MSIZE_WORD GD32_DMA_CTL_MWIDTH_WORD +#define STM32_DMA_CR_MINC GD32_DMA_CTL_MNAGA +#define STM32_DMA_CR_CIRC GD32_DMA_CTL_CMEN +#define STM32_DMA_CR_PL GD32_DMA_CTL_PRIO +#define STM32_DMA_CR_CHSEL GD32_DMA_CTL_CHSEL +#define cr1 ctl0 +#define cr2 ctl1 +#define cr3 ctl2 +#define dier dmainten + +/* ADC redefines */ +#if HAL_USE_ADC +# define STM32_ADC_USE_ADC1 GD32_ADC_USE_ADC0 + +# define smpr1 sampt0 +# define smpr2 sampt1 +# define sqr1 rsq0 +# define sqr2 rsq1 +# define sqr3 rsq2 + +# define ADC_SMPR2_SMP_AN0 ADC_SAMPT1_SMP_SPT0 +# define ADC_SMPR2_SMP_AN1 ADC_SAMPT1_SMP_SPT1 +# define ADC_SMPR2_SMP_AN2 ADC_SAMPT1_SMP_SPT2 +# define ADC_SMPR2_SMP_AN3 ADC_SAMPT1_SMP_SPT3 +# define ADC_SMPR2_SMP_AN4 ADC_SAMPT1_SMP_SPT4 +# define ADC_SMPR2_SMP_AN5 ADC_SAMPT1_SMP_SPT5 +# define ADC_SMPR2_SMP_AN6 ADC_SAMPT1_SMP_SPT6 +# define ADC_SMPR2_SMP_AN7 ADC_SAMPT1_SMP_SPT7 +# define ADC_SMPR2_SMP_AN8 ADC_SAMPT1_SMP_SPT8 +# define ADC_SMPR2_SMP_AN9 ADC_SAMPT1_SMP_SPT9 + +# define ADC_SMPR1_SMP_AN10 ADC_SAMPT0_SMP_SPT10 +# define ADC_SMPR1_SMP_AN11 ADC_SAMPT0_SMP_SPT11 +# define ADC_SMPR1_SMP_AN12 ADC_SAMPT0_SMP_SPT12 +# define ADC_SMPR1_SMP_AN13 ADC_SAMPT0_SMP_SPT13 +# define ADC_SMPR1_SMP_AN14 ADC_SAMPT0_SMP_SPT14 +# define ADC_SMPR1_SMP_AN15 ADC_SAMPT0_SMP_SPT15 + +# define ADC_SQR3_SQ1_N ADC_RSQ2_RSQ1_N +#endif + +/* FLASH redefines */ +#if defined(EEPROM_ENABLE) +# define SR STAT +# define FLASH_SR_BSY FLASH_STAT_BUSY +# define FLASH_SR_PGERR FLASH_STAT_PGERR +# define FLASH_SR_EOP FLASH_STAT_ENDF +# define FLASH_SR_WRPRTERR FLASH_STAT_WPERR +# define FLASH_SR_WRPERR FLASH_SR_WRPRTERR +# define FLASH_OBR_OPTERR FLASH_OBSTAT_OBERR +# define AR ADDR +# define CR CTL +# define FLASH_CR_PER FLASH_CTL_PER +# define FLASH_CR_STRT FLASH_CTL_START +# define FLASH_CR_LOCK FLASH_CTL_LK +# define FLASH_CR_PG FLASH_CTL_PG +# define KEYR KEY +#endif + +/* Serial USART redefines. */ +#if HAL_USE_SERIAL +# if !defined(SERIAL_USART_CR1) +# define SERIAL_USART_CR1 (USART_CTL0_PCEN | USART_CTL0_PM | USART_CTL0_WL) // parity enable, odd parity, 9 bit length +# endif +# if !defined(SERIAL_USART_CR2) +# define SERIAL_USART_CR2 (USART_CTL1_STB_1) // 2 stop bits +# endif +# if !defined(SERIAL_USART_CR3) +# define SERIAL_USART_CR3 0x0 +# endif +# define USART_CR3_HDSEL USART_CTL2_HDEN +# define CCR CHCV +#endif + +/* SPI redefines. */ +#if HAL_USE_SPI +# define SPI_CR1_LSBFIRST SPI_CTL0_LF +# define SPI_CR1_CPHA SPI_CTL0_CKPH +# define SPI_CR1_CPOL SPI_CTL0_CKPL +# define SPI_CR1_BR_0 SPI_CTL0_PSC_0 +# define SPI_CR1_BR_1 SPI_CTL0_PSC_1 +# define SPI_CR1_BR_2 SPI_CTL0_PSC_2 +#endif diff --git a/platforms/chibios/gpio.h b/platforms/chibios/gpio.h new file mode 100644 index 0000000000..4d057f1cab --- /dev/null +++ b/platforms/chibios/gpio.h @@ -0,0 +1,50 @@ +/* Copyright 2021 QMK + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#pragma once + +#include +#include "pin_defs.h" + +typedef ioline_t pin_t; + +/* Operation of GPIO by pin. */ + +#define setPinInput(pin) palSetLineMode(pin, PAL_MODE_INPUT) +#define setPinInputHigh(pin) palSetLineMode(pin, PAL_MODE_INPUT_PULLUP) +#define setPinInputLow(pin) palSetLineMode(pin, PAL_MODE_INPUT_PULLDOWN) +#define setPinOutput(pin) palSetLineMode(pin, PAL_MODE_OUTPUT_PUSHPULL) + +#define writePinHigh(pin) palSetLine(pin) +#define writePinLow(pin) palClearLine(pin) +#define writePin(pin, level) ((level) ? (writePinHigh(pin)) : (writePinLow(pin))) + +#define readPin(pin) palReadLine(pin) + +#define togglePin(pin) palToggleLine(pin) + +/* Operation of GPIO by port. */ + +typedef uint16_t port_data_t; + +#define readPort(pin) palReadPort(PAL_PORT(pin)) + +#define setPortBitInput(pin, bit) palSetPadMode(PAL_PORT(pin), bit, PAL_MODE_INPUT) +#define setPortBitInputHigh(pin, bit) palSetPadMode(PAL_PORT(pin), bit, PAL_MODE_INPUT_PULLUP) +#define setPortBitInputLow(pin, bit) palSetPadMode(PAL_PORT(pin), bit, PAL_MODE_INPUT_PULLDOWN) +#define setPortBitOutput(pin, bit) palSetPadMode(PAL_PORT(pin), bit, PAL_MODE_OUTPUT_PUSHPULL) + +#define writePortBitLow(pin, bit) palClearLine(PAL_LINE(PAL_PORT(pin), bit)) +#define writePortBitHigh(pin, bit) palSetLine(PAL_LINE(PAL_PORT(pin), bit)) diff --git a/platforms/chibios/pin_defs.h b/platforms/chibios/pin_defs.h new file mode 100644 index 0000000000..c03f8de0c2 --- /dev/null +++ b/platforms/chibios/pin_defs.h @@ -0,0 +1,323 @@ +/* Copyright 2021 QMK + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#pragma once + +// Defines mapping for Proton C replacement +#ifdef CONVERT_TO_PROTON_C +// Left side (front) +# define D3 PAL_LINE(GPIOA, 9) +# define D2 PAL_LINE(GPIOA, 10) +// GND +// GND +# define D1 PAL_LINE(GPIOB, 7) +# define D0 PAL_LINE(GPIOB, 6) +# define D4 PAL_LINE(GPIOB, 5) +# define C6 PAL_LINE(GPIOB, 4) +# define D7 PAL_LINE(GPIOB, 3) +# define E6 PAL_LINE(GPIOB, 2) +# define B4 PAL_LINE(GPIOB, 1) +# define B5 PAL_LINE(GPIOB, 0) + +// Right side (front) +// RAW +// GND +// RESET +// VCC +# define F4 PAL_LINE(GPIOA, 2) +# define F5 PAL_LINE(GPIOA, 1) +# define F6 PAL_LINE(GPIOA, 0) +# define F7 PAL_LINE(GPIOB, 8) +# define B1 PAL_LINE(GPIOB, 13) +# define B3 PAL_LINE(GPIOB, 14) +# define B2 PAL_LINE(GPIOB, 15) +# define B6 PAL_LINE(GPIOB, 9) + +// LEDs (only D5/C13 uses an actual LED) +# ifdef CONVERT_TO_PROTON_C_RXLED +# define D5 PAL_LINE(GPIOC, 14) +# define B0 PAL_LINE(GPIOC, 13) +# else +# define D5 PAL_LINE(GPIOC, 13) +# define B0 PAL_LINE(GPIOC, 14) +# endif +#else +# define A0 PAL_LINE(GPIOA, 0) +# define A1 PAL_LINE(GPIOA, 1) +# define A2 PAL_LINE(GPIOA, 2) +# define A3 PAL_LINE(GPIOA, 3) +# define A4 PAL_LINE(GPIOA, 4) +# define A5 PAL_LINE(GPIOA, 5) +# define A6 PAL_LINE(GPIOA, 6) +# define A7 PAL_LINE(GPIOA, 7) +# define A8 PAL_LINE(GPIOA, 8) +# define A9 PAL_LINE(GPIOA, 9) +# define A10 PAL_LINE(GPIOA, 10) +# define A11 PAL_LINE(GPIOA, 11) +# define A12 PAL_LINE(GPIOA, 12) +# define A13 PAL_LINE(GPIOA, 13) +# define A14 PAL_LINE(GPIOA, 14) +# define A15 PAL_LINE(GPIOA, 15) +# define A16 PAL_LINE(GPIOA, 16) +# define A17 PAL_LINE(GPIOA, 17) +# define A18 PAL_LINE(GPIOA, 18) +# define A19 PAL_LINE(GPIOA, 19) +# define A20 PAL_LINE(GPIOA, 20) +# define A21 PAL_LINE(GPIOA, 21) +# define A22 PAL_LINE(GPIOA, 22) +# define A23 PAL_LINE(GPIOA, 23) +# define A24 PAL_LINE(GPIOA, 24) +# define A25 PAL_LINE(GPIOA, 25) +# define A26 PAL_LINE(GPIOA, 26) +# define A27 PAL_LINE(GPIOA, 27) +# define A28 PAL_LINE(GPIOA, 28) +# define A29 PAL_LINE(GPIOA, 29) +# define A30 PAL_LINE(GPIOA, 30) +# define A31 PAL_LINE(GPIOA, 31) +# define A32 PAL_LINE(GPIOA, 32) +# define B0 PAL_LINE(GPIOB, 0) +# define B1 PAL_LINE(GPIOB, 1) +# define B2 PAL_LINE(GPIOB, 2) +# define B3 PAL_LINE(GPIOB, 3) +# define B4 PAL_LINE(GPIOB, 4) +# define B5 PAL_LINE(GPIOB, 5) +# define B6 PAL_LINE(GPIOB, 6) +# define B7 PAL_LINE(GPIOB, 7) +# define B8 PAL_LINE(GPIOB, 8) +# define B9 PAL_LINE(GPIOB, 9) +# define B10 PAL_LINE(GPIOB, 10) +# define B11 PAL_LINE(GPIOB, 11) +# define B12 PAL_LINE(GPIOB, 12) +# define B13 PAL_LINE(GPIOB, 13) +# define B14 PAL_LINE(GPIOB, 14) +# define B15 PAL_LINE(GPIOB, 15) +# define B16 PAL_LINE(GPIOB, 16) +# define B17 PAL_LINE(GPIOB, 17) +# define B18 PAL_LINE(GPIOB, 18) +# define B19 PAL_LINE(GPIOB, 19) +# define B20 PAL_LINE(GPIOB, 20) +# define B21 PAL_LINE(GPIOB, 21) +# define B22 PAL_LINE(GPIOB, 22) +# define B23 PAL_LINE(GPIOB, 23) +# define B24 PAL_LINE(GPIOB, 24) +# define B25 PAL_LINE(GPIOB, 25) +# define B26 PAL_LINE(GPIOB, 26) +# define B27 PAL_LINE(GPIOB, 27) +# define B28 PAL_LINE(GPIOB, 28) +# define B29 PAL_LINE(GPIOB, 29) +# define B30 PAL_LINE(GPIOB, 30) +# define B31 PAL_LINE(GPIOB, 31) +# define B32 PAL_LINE(GPIOB, 32) +# define C0 PAL_LINE(GPIOC, 0) +# define C1 PAL_LINE(GPIOC, 1) +# define C2 PAL_LINE(GPIOC, 2) +# define C3 PAL_LINE(GPIOC, 3) +# define C4 PAL_LINE(GPIOC, 4) +# define C5 PAL_LINE(GPIOC, 5) +# define C6 PAL_LINE(GPIOC, 6) +# define C7 PAL_LINE(GPIOC, 7) +# define C8 PAL_LINE(GPIOC, 8) +# define C9 PAL_LINE(GPIOC, 9) +# define C10 PAL_LINE(GPIOC, 10) +# define C11 PAL_LINE(GPIOC, 11) +# define C12 PAL_LINE(GPIOC, 12) +# define C13 PAL_LINE(GPIOC, 13) +# define C14 PAL_LINE(GPIOC, 14) +# define C15 PAL_LINE(GPIOC, 15) +# define C16 PAL_LINE(GPIOC, 16) +# define C17 PAL_LINE(GPIOC, 17) +# define C18 PAL_LINE(GPIOC, 18) +# define C19 PAL_LINE(GPIOC, 19) +# define C20 PAL_LINE(GPIOC, 20) +# define C21 PAL_LINE(GPIOC, 21) +# define C22 PAL_LINE(GPIOC, 22) +# define C23 PAL_LINE(GPIOC, 23) +# define C24 PAL_LINE(GPIOC, 24) +# define C25 PAL_LINE(GPIOC, 25) +# define C26 PAL_LINE(GPIOC, 26) +# define C27 PAL_LINE(GPIOC, 27) +# define C28 PAL_LINE(GPIOC, 28) +# define C29 PAL_LINE(GPIOC, 29) +# define C30 PAL_LINE(GPIOC, 30) +# define C31 PAL_LINE(GPIOC, 31) +# define C32 PAL_LINE(GPIOC, 32) +# define D0 PAL_LINE(GPIOD, 0) +# define D1 PAL_LINE(GPIOD, 1) +# define D2 PAL_LINE(GPIOD, 2) +# define D3 PAL_LINE(GPIOD, 3) +# define D4 PAL_LINE(GPIOD, 4) +# define D5 PAL_LINE(GPIOD, 5) +# define D6 PAL_LINE(GPIOD, 6) +# define D7 PAL_LINE(GPIOD, 7) +# define D8 PAL_LINE(GPIOD, 8) +# define D9 PAL_LINE(GPIOD, 9) +# define D10 PAL_LINE(GPIOD, 10) +# define D11 PAL_LINE(GPIOD, 11) +# define D12 PAL_LINE(GPIOD, 12) +# define D13 PAL_LINE(GPIOD, 13) +# define D14 PAL_LINE(GPIOD, 14) +# define D15 PAL_LINE(GPIOD, 15) +# define D16 PAL_LINE(GPIOD, 16) +# define D17 PAL_LINE(GPIOD, 17) +# define D18 PAL_LINE(GPIOD, 18) +# define D19 PAL_LINE(GPIOD, 19) +# define D20 PAL_LINE(GPIOD, 20) +# define D21 PAL_LINE(GPIOD, 21) +# define D22 PAL_LINE(GPIOD, 22) +# define D23 PAL_LINE(GPIOD, 23) +# define D24 PAL_LINE(GPIOD, 24) +# define D25 PAL_LINE(GPIOD, 25) +# define D26 PAL_LINE(GPIOD, 26) +# define D27 PAL_LINE(GPIOD, 27) +# define D28 PAL_LINE(GPIOD, 28) +# define D29 PAL_LINE(GPIOD, 29) +# define D30 PAL_LINE(GPIOD, 30) +# define D31 PAL_LINE(GPIOD, 31) +# define D32 PAL_LINE(GPIOD, 32) +# define E0 PAL_LINE(GPIOE, 0) +# define E1 PAL_LINE(GPIOE, 1) +# define E2 PAL_LINE(GPIOE, 2) +# define E3 PAL_LINE(GPIOE, 3) +# define E4 PAL_LINE(GPIOE, 4) +# define E5 PAL_LINE(GPIOE, 5) +# define E6 PAL_LINE(GPIOE, 6) +# define E7 PAL_LINE(GPIOE, 7) +# define E8 PAL_LINE(GPIOE, 8) +# define E9 PAL_LINE(GPIOE, 9) +# define E10 PAL_LINE(GPIOE, 10) +# define E11 PAL_LINE(GPIOE, 11) +# define E12 PAL_LINE(GPIOE, 12) +# define E13 PAL_LINE(GPIOE, 13) +# define E14 PAL_LINE(GPIOE, 14) +# define E15 PAL_LINE(GPIOE, 15) +# define E16 PAL_LINE(GPIOE, 16) +# define E17 PAL_LINE(GPIOE, 17) +# define E18 PAL_LINE(GPIOE, 18) +# define E19 PAL_LINE(GPIOE, 19) +# define E20 PAL_LINE(GPIOE, 20) +# define E21 PAL_LINE(GPIOE, 21) +# define E22 PAL_LINE(GPIOE, 22) +# define E23 PAL_LINE(GPIOE, 23) +# define E24 PAL_LINE(GPIOE, 24) +# define E25 PAL_LINE(GPIOE, 25) +# define E26 PAL_LINE(GPIOE, 26) +# define E27 PAL_LINE(GPIOE, 27) +# define E28 PAL_LINE(GPIOE, 28) +# define E29 PAL_LINE(GPIOE, 29) +# define E30 PAL_LINE(GPIOE, 30) +# define E31 PAL_LINE(GPIOE, 31) +# define E32 PAL_LINE(GPIOE, 32) +# define F0 PAL_LINE(GPIOF, 0) +# define F1 PAL_LINE(GPIOF, 1) +# define F2 PAL_LINE(GPIOF, 2) +# define F3 PAL_LINE(GPIOF, 3) +# define F4 PAL_LINE(GPIOF, 4) +# define F5 PAL_LINE(GPIOF, 5) +# define F6 PAL_LINE(GPIOF, 6) +# define F7 PAL_LINE(GPIOF, 7) +# define F8 PAL_LINE(GPIOF, 8) +# define F9 PAL_LINE(GPIOF, 9) +# define F10 PAL_LINE(GPIOF, 10) +# define F11 PAL_LINE(GPIOF, 11) +# define F12 PAL_LINE(GPIOF, 12) +# define F13 PAL_LINE(GPIOF, 13) +# define F14 PAL_LINE(GPIOF, 14) +# define F15 PAL_LINE(GPIOF, 15) +# define G0 PAL_LINE(GPIOG, 0) +# define G1 PAL_LINE(GPIOG, 1) +# define G2 PAL_LINE(GPIOG, 2) +# define G3 PAL_LINE(GPIOG, 3) +# define G4 PAL_LINE(GPIOG, 4) +# define G5 PAL_LINE(GPIOG, 5) +# define G6 PAL_LINE(GPIOG, 6) +# define G7 PAL_LINE(GPIOG, 7) +# define G8 PAL_LINE(GPIOG, 8) +# define G9 PAL_LINE(GPIOG, 9) +# define G10 PAL_LINE(GPIOG, 10) +# define G11 PAL_LINE(GPIOG, 11) +# define G12 PAL_LINE(GPIOG, 12) +# define G13 PAL_LINE(GPIOG, 13) +# define G14 PAL_LINE(GPIOG, 14) +# define G15 PAL_LINE(GPIOG, 15) +# define H0 PAL_LINE(GPIOH, 0) +# define H1 PAL_LINE(GPIOH, 1) +# define H2 PAL_LINE(GPIOH, 2) +# define H3 PAL_LINE(GPIOH, 3) +# define H4 PAL_LINE(GPIOH, 4) +# define H5 PAL_LINE(GPIOH, 5) +# define H6 PAL_LINE(GPIOH, 6) +# define H7 PAL_LINE(GPIOH, 7) +# define H8 PAL_LINE(GPIOH, 8) +# define H9 PAL_LINE(GPIOH, 9) +# define H10 PAL_LINE(GPIOH, 10) +# define H11 PAL_LINE(GPIOH, 11) +# define H12 PAL_LINE(GPIOH, 12) +# define H13 PAL_LINE(GPIOH, 13) +# define H14 PAL_LINE(GPIOH, 14) +# define H15 PAL_LINE(GPIOH, 15) +# define I0 PAL_LINE(GPIOI, 0) +# define I1 PAL_LINE(GPIOI, 1) +# define I2 PAL_LINE(GPIOI, 2) +# define I3 PAL_LINE(GPIOI, 3) +# define I4 PAL_LINE(GPIOI, 4) +# define I5 PAL_LINE(GPIOI, 5) +# define I6 PAL_LINE(GPIOI, 6) +# define I7 PAL_LINE(GPIOI, 7) +# define I8 PAL_LINE(GPIOI, 8) +# define I9 PAL_LINE(GPIOI, 9) +# define I10 PAL_LINE(GPIOI, 10) +# define I11 PAL_LINE(GPIOI, 11) +# define I12 PAL_LINE(GPIOI, 12) +# define I13 PAL_LINE(GPIOI, 13) +# define I14 PAL_LINE(GPIOI, 14) +# define I15 PAL_LINE(GPIOI, 15) +# define J0 PAL_LINE(GPIOJ, 0) +# define J1 PAL_LINE(GPIOJ, 1) +# define J2 PAL_LINE(GPIOJ, 2) +# define J3 PAL_LINE(GPIOJ, 3) +# define J4 PAL_LINE(GPIOJ, 4) +# define J5 PAL_LINE(GPIOJ, 5) +# define J6 PAL_LINE(GPIOJ, 6) +# define J7 PAL_LINE(GPIOJ, 7) +# define J8 PAL_LINE(GPIOJ, 8) +# define J9 PAL_LINE(GPIOJ, 9) +# define J10 PAL_LINE(GPIOJ, 10) +# define J11 PAL_LINE(GPIOJ, 11) +# define J12 PAL_LINE(GPIOJ, 12) +# define J13 PAL_LINE(GPIOJ, 13) +# define J14 PAL_LINE(GPIOJ, 14) +# define J15 PAL_LINE(GPIOJ, 15) +// Keyboards can `#define KEYBOARD_REQUIRES_GPIOK` if they need to access GPIO-K pins. These conflict with a whole +// bunch of layout definitions, so it's intentionally left out unless absolutely required -- in that case, the +// keyboard designer should use a different symbol when defining their layout macros. +# ifdef KEYBOARD_REQUIRES_GPIOK +# define K0 PAL_LINE(GPIOK, 0) +# define K1 PAL_LINE(GPIOK, 1) +# define K2 PAL_LINE(GPIOK, 2) +# define K3 PAL_LINE(GPIOK, 3) +# define K4 PAL_LINE(GPIOK, 4) +# define K5 PAL_LINE(GPIOK, 5) +# define K6 PAL_LINE(GPIOK, 6) +# define K7 PAL_LINE(GPIOK, 7) +# define K8 PAL_LINE(GPIOK, 8) +# define K9 PAL_LINE(GPIOK, 9) +# define K10 PAL_LINE(GPIOK, 10) +# define K11 PAL_LINE(GPIOK, 11) +# define K12 PAL_LINE(GPIOK, 12) +# define K13 PAL_LINE(GPIOK, 13) +# define K14 PAL_LINE(GPIOK, 14) +# define K15 PAL_LINE(GPIOK, 15) +# endif +#endif diff --git a/platforms/chibios/platform.c b/platforms/chibios/platform.c new file mode 100644 index 0000000000..d4a229f278 --- /dev/null +++ b/platforms/chibios/platform.c @@ -0,0 +1,22 @@ +/* Copyright 2021 QMK + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "platform_deps.h" + +void platform_setup(void) { + halInit(); + chSysInit(); +} \ No newline at end of file diff --git a/platforms/chibios/platform.mk b/platforms/chibios/platform.mk new file mode 100644 index 0000000000..6b298732c2 --- /dev/null +++ b/platforms/chibios/platform.mk @@ -0,0 +1,436 @@ +# Hey Emacs, this is a -*- makefile -*- +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x800 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Imported source files and paths +OPT_OS = chibios +CHIBIOS = $(TOP_DIR)/lib/chibios +CHIBIOS_CONTRIB = $(TOP_DIR)/lib/chibios-contrib + +# +# Startup, Port and Platform support selection +############################################################################## + +ifeq ($(strip $(MCU)), risc-v) + # RISC-V Support + # As of 7.4.2021 there is only one supported RISC-V platform in Chibios-Contrib, + # therefore all required settings are hard-coded + STARTUP_MK = $(CHIBIOS_CONTRIB)/os/common/startup/RISCV-ECLIC/compilers/GCC/mk/startup_$(MCU_STARTUP).mk + PORT_V = $(CHIBIOS_CONTRIB)/os/common/ports/RISCV-ECLIC/compilers/GCC/mk/port.mk + RULESPATH = $(CHIBIOS_CONTRIB)/os/common/startup/RISCV-ECLIC/compilers/GCC + PLATFORM_MK = $(CHIBIOS_CONTRIB)/os/hal/ports/GD/GD32VF103/platform.mk +else + # ARM Support + CHIBIOS_PORT ?= + ifeq ("$(CHIBIOS_PORT)","") + CHIBIOS_PORT = ARMv$(ARMV)-M + endif + + # Startup files. Try a few different locations, for compability with old versions and + # for things hardware in the contrib repository + STARTUP_MK = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_$(MCU_STARTUP).mk + ifeq ("$(wildcard $(STARTUP_MK))","") + STARTUP_MK = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_$(MCU_STARTUP).mk + ifeq ("$(wildcard $(STARTUP_MK))","") + STARTUP_MK = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_$(MCU_STARTUP).mk + endif + endif + + # Port files. Try a few different locations, for compability with old versions and + # for things hardware in the contrib repository + PORT_V = $(CHIBIOS)/os/common/ports/$(CHIBIOS_PORT)/compilers/GCC/mk/port.mk + ifeq ("$(wildcard $(PORT_V))","") + PORT_V = $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v$(ARMV)m.mk + ifeq ("$(wildcard $(PORT_V))","") + PORT_V = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v$(ARMV)m.mk + endif + endif + + # Rules location. Try a few different locations, for compability with old versions and + # for things hardware in the contrib repository + RULESPATH = $(CHIBIOS)/os/common/ports/$(CHIBIOS_PORT)/compilers/GCC + ifeq ("$(wildcard $(RULESPATH)/rules.mk)","") + RULESPATH = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC + ifeq ("$(wildcard $(RULESPATH)/rules.mk)","") + RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC + endif + endif +endif + +ifeq ("$(PLATFORM_NAME)","") + PLATFORM_NAME = platform +endif + +ifeq ("$(wildcard $(PLATFORM_MK))","") + PLATFORM_MK = $(CHIBIOS)/os/hal/ports/$(MCU_FAMILY)/$(MCU_SERIES)/$(PLATFORM_NAME).mk + ifeq ("$(wildcard $(PLATFORM_MK))","") + PLATFORM_MK = $(CHIBIOS_CONTRIB)/os/hal/ports/$(MCU_FAMILY)/$(MCU_SERIES)/$(PLATFORM_NAME).mk + endif +endif + +include $(STARTUP_MK) +include $(PORT_V) +include $(PLATFORM_MK) + +# +# Board support selection. +############################################################################## + +BOARD_MK := + +ifneq ("$(wildcard $(KEYBOARD_PATH_5)/boards/$(BOARD)/board.mk)","") + BOARD_PATH = $(KEYBOARD_PATH_5) + BOARD_MK += $(KEYBOARD_PATH_5)/boards/$(BOARD)/board.mk +else ifneq ("$(wildcard $(KEYBOARD_PATH_4)/boards/$(BOARD)/board.mk)","") + BOARD_PATH = $(KEYBOARD_PATH_4) + BOARD_MK += $(KEYBOARD_PATH_4)/boards/$(BOARD)/board.mk +else ifneq ("$(wildcard $(KEYBOARD_PATH_3)/boards/$(BOARD)/board.mk)","") + BOARD_PATH = $(KEYBOARD_PATH_3) + BOARD_MK += $(KEYBOARD_PATH_3)/boards/$(BOARD)/board.mk +else ifneq ("$(wildcard $(KEYBOARD_PATH_2)/boards/$(BOARD)/board.mk)","") + BOARD_PATH = $(KEYBOARD_PATH_2) + BOARD_MK += $(KEYBOARD_PATH_2)/boards/$(BOARD)/board.mk +else ifneq ("$(wildcard $(KEYBOARD_PATH_1)/boards/$(BOARD)/board.mk)","") + BOARD_PATH = $(KEYBOARD_PATH_1) + BOARD_MK += $(KEYBOARD_PATH_1)/boards/$(BOARD)/board.mk +else ifneq ("$(wildcard $(TOP_DIR)/platforms/chibios/boards/$(BOARD)/board/board.mk)","") + BOARD_PATH = $(TOP_DIR)/platforms/chibios/boards/$(BOARD) + BOARD_MK += $(TOP_DIR)/platforms/chibios/boards/$(BOARD)/board/board.mk + KEYBOARD_PATHS += $(BOARD_PATH)/configs + ifneq ("$(wildcard $(BOARD_PATH)/rules.mk)","") + include $(BOARD_PATH)/rules.mk + endif +endif + +ifeq ("$(wildcard $(BOARD_MK))","") + BOARD_MK = $(CHIBIOS)/os/hal/boards/$(BOARD)/board.mk + ifeq ("$(wildcard $(BOARD_MK))","") + BOARD_MK = $(CHIBIOS_CONTRIB)/os/hal/boards/$(BOARD)/board.mk + endif +endif + +include $(BOARD_MK) + +# +# Bootloader selection. +############################################################################## + +# Set bootloader address if supplied. +ifdef STM32_BOOTLOADER_ADDRESS + OPT_DEFS += -DSTM32_BOOTLOADER_ADDRESS=$(STM32_BOOTLOADER_ADDRESS) +endif + +# Work out if we need to set up the include for the bootloader definitions +ifneq ("$(wildcard $(KEYBOARD_PATH_5)/bootloader_defs.h)","") + OPT_DEFS += -include $(KEYBOARD_PATH_5)/bootloader_defs.h +else ifneq ("$(wildcard $(KEYBOARD_PATH_5)/boards/$(BOARD)/bootloader_defs.h)","") + OPT_DEFS += -include $(KEYBOARD_PATH_5)/boards/$(BOARD)/bootloader_defs.h +else ifneq ("$(wildcard $(KEYBOARD_PATH_4)/bootloader_defs.h)","") + OPT_DEFS += -include $(KEYBOARD_PATH_4)/bootloader_defs.h +else ifneq ("$(wildcard $(KEYBOARD_PATH_4)/boards/$(BOARD)/bootloader_defs.h)","") + OPT_DEFS += -include $(KEYBOARD_PATH_4)/boards/$(BOARD)/bootloader_defs.h +else ifneq ("$(wildcard $(KEYBOARD_PATH_3)/bootloader_defs.h)","") + OPT_DEFS += -include $(KEYBOARD_PATH_3)/bootloader_defs.h +else ifneq ("$(wildcard $(KEYBOARD_PATH_3)/boards/$(BOARD)/bootloader_defs.h)","") + OPT_DEFS += -include $(KEYBOARD_PATH_3)/boards/$(BOARD)/bootloader_defs.h +else ifneq ("$(wildcard $(KEYBOARD_PATH_2)/bootloader_defs.h)","") + OPT_DEFS += -include $(KEYBOARD_PATH_2)/bootloader_defs.h +else ifneq ("$(wildcard $(KEYBOARD_PATH_2)/boards/$(BOARD)/bootloader_defs.h)","") + OPT_DEFS += -include $(KEYBOARD_PATH_2)/boards/$(BOARD)/bootloader_defs.h +else ifneq ("$(wildcard $(KEYBOARD_PATH_1)/bootloader_defs.h)","") + OPT_DEFS += -include $(KEYBOARD_PATH_1)/bootloader_defs.h +else ifneq ("$(wildcard $(KEYBOARD_PATH_1)/boards/$(BOARD)/bootloader_defs.h)","") + OPT_DEFS += -include $(KEYBOARD_PATH_1)/boards/$(BOARD)/bootloader_defs.h +else ifneq ("$(wildcard $(BOARD_PATH)/configs/bootloader_defs.h)","") + OPT_DEFS += -include $(BOARD_PATH)/configs/bootloader_defs.h +endif + +# +# ChibiOS config selection. +############################################################################## + +# Work out the config file directories +ifneq ("$(wildcard $(KEYBOARD_PATH_5)/chconf.h)","") + CHCONFDIR = $(KEYBOARD_PATH_5) +else ifneq ("$(wildcard $(KEYBOARD_PATH_4)/chconf.h)","") + CHCONFDIR = $(KEYBOARD_PATH_4) +else ifneq ("$(wildcard $(KEYBOARD_PATH_3)/chconf.h)","") + CHCONFDIR = $(KEYBOARD_PATH_3) +else ifneq ("$(wildcard $(KEYBOARD_PATH_2)/chconf.h)","") + CHCONFDIR = $(KEYBOARD_PATH_2) +else ifneq ("$(wildcard $(KEYBOARD_PATH_1)/chconf.h)","") + CHCONFDIR = $(KEYBOARD_PATH_1) +else ifneq ("$(wildcard $(TOP_DIR)/platforms/chibios/boards/$(BOARD)/configs/chconf.h)","") + CHCONFDIR = $(TOP_DIR)/platforms/chibios/boards/$(BOARD)/configs +else ifneq ("$(wildcard $(TOP_DIR)/platforms/boards/chibios/common/configs/chconf.h)","") + CHCONFDIR = $(TOP_DIR)/platforms/chibios/boards/common/configs +endif + +# +# HAL config selection. +############################################################################## + +ifneq ("$(wildcard $(KEYBOARD_PATH_5)/halconf.h)","") + HALCONFDIR = $(KEYBOARD_PATH_5) +else ifneq ("$(wildcard $(KEYBOARD_PATH_4)/halconf.h)","") + HALCONFDIR = $(KEYBOARD_PATH_4) +else ifneq ("$(wildcard $(KEYBOARD_PATH_3)/halconf.h)","") + HALCONFDIR = $(KEYBOARD_PATH_3) +else ifneq ("$(wildcard $(KEYBOARD_PATH_2)/halconf.h)","") + HALCONFDIR = $(KEYBOARD_PATH_2) +else ifneq ("$(wildcard $(KEYBOARD_PATH_1)/halconf.h)","") + HALCONFDIR = $(KEYBOARD_PATH_1) +else ifneq ("$(wildcard $(TOP_DIR)/platforms/chibios/boards/$(BOARD)/configs/halconf.h)","") + HALCONFDIR = $(TOP_DIR)/platforms/chibios/boards/$(BOARD)/configs +else ifneq ("$(wildcard $(TOP_DIR)/platforms/chibios/boards/common/configs/halconf.h)","") + HALCONFDIR = $(TOP_DIR)/platforms/chibios/boards/common/configs +endif + +# +# Linker script selection. +############################################################################## + +ifneq ("$(wildcard $(KEYBOARD_PATH_5)/ld/$(MCU_LDSCRIPT).ld)","") + LDSCRIPT = $(KEYBOARD_PATH_5)/ld/$(MCU_LDSCRIPT).ld +else ifneq ("$(wildcard $(KEYBOARD_PATH_4)/ld/$(MCU_LDSCRIPT).ld)","") + LDSCRIPT = $(KEYBOARD_PATH_4)/ld/$(MCU_LDSCRIPT).ld +else ifneq ("$(wildcard $(KEYBOARD_PATH_3)/ld/$(MCU_LDSCRIPT).ld)","") + LDSCRIPT = $(KEYBOARD_PATH_3)/ld/$(MCU_LDSCRIPT).ld +else ifneq ("$(wildcard $(KEYBOARD_PATH_2)/ld/$(MCU_LDSCRIPT).ld)","") + LDSCRIPT = $(KEYBOARD_PATH_2)/ld/$(MCU_LDSCRIPT).ld +else ifneq ("$(wildcard $(KEYBOARD_PATH_1)/ld/$(MCU_LDSCRIPT).ld)","") + LDSCRIPT = $(KEYBOARD_PATH_1)/ld/$(MCU_LDSCRIPT).ld +else ifneq ("$(wildcard $(TOP_DIR)/platforms/chibios/boards/$(BOARD)/ld/$(MCU_LDSCRIPT).ld)","") + LDFLAGS += -L$(TOP_DIR)/platforms/chibios/boards/$(BOARD)/ld + LDSCRIPT = $(TOP_DIR)/platforms/chibios/boards/$(BOARD)/ld/$(MCU_LDSCRIPT).ld +else ifneq ("$(wildcard $(TOP_DIR)/platforms/chibios/boards/common/ld/$(MCU_LDSCRIPT).ld)","") + LDSCRIPT = $(TOP_DIR)/platforms/chibios/boards/common/ld/$(MCU_LDSCRIPT).ld +else ifneq ("$(wildcard $(STARTUPLD_CONTRIB)/$(MCU_LDSCRIPT).ld)","") + LDSCRIPT = $(STARTUPLD_CONTRIB)/$(MCU_LDSCRIPT).ld + USE_CHIBIOS_CONTRIB = yes +else + LDSCRIPT = $(STARTUPLD)/$(MCU_LDSCRIPT).ld +endif + +# +# Include ChibiOS makefiles. +############################################################################## + +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +-include $(CHIBIOS)/os/hal/osal/rt/osal.mk # ChibiOS <= 19.x +-include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk # ChibiOS >= 20.x +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +# Other files (optional). +include $(CHIBIOS)/os/hal/lib/streams/streams.mk + +PLATFORM_SRC = \ + $(STARTUPSRC) \ + $(KERNSRC) \ + $(PORTSRC) \ + $(OSALSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(STREAMSSRC) \ + $(CHIBIOS)/os/various/syscalls.c \ + $(PLATFORM_COMMON_DIR)/syscall-fallbacks.c \ + $(PLATFORM_COMMON_DIR)/wait.c + +# Ensure the ASM files are not subjected to LTO -- it'll strip out interrupt handlers otherwise. +QUANTUM_LIB_SRC += $(STARTUPASM) $(PORTASM) $(OSALASM) $(PLATFORMASM) + +PLATFORM_SRC := $(patsubst $(TOP_DIR)/%,%,$(PLATFORM_SRC)) + +EXTRAINCDIRS += $(CHIBIOS)/os/license $(CHIBIOS)/os/oslib/include \ + $(TOP_DIR)/platforms/chibios/boards/$(BOARD)/configs \ + $(TOP_DIR)/platforms/chibios/boards/common/configs \ + $(HALCONFDIR) $(CHCONFDIR) \ + $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ + $(STREAMSINC) $(CHIBIOS)/os/various $(COMMON_VPATH) + +# +# ChibiOS-Contrib +############################################################################## + +# Work out if we're using ChibiOS-Contrib by checking if halconf_community.h exists +ifneq ("$(wildcard $(KEYBOARD_PATH_5)/halconf_community.h)","") + USE_CHIBIOS_CONTRIB = yes +else ifneq ("$(wildcard $(KEYBOARD_PATH_4)/halconf_community.h)","") + USE_CHIBIOS_CONTRIB = yes +else ifneq ("$(wildcard $(KEYBOARD_PATH_3)/halconf_community.h)","") + USE_CHIBIOS_CONTRIB = yes +else ifneq ("$(wildcard $(KEYBOARD_PATH_2)/halconf_community.h)","") + USE_CHIBIOS_CONTRIB = yes +else ifneq ("$(wildcard $(KEYBOARD_PATH_1)/halconf_community.h)","") + USE_CHIBIOS_CONTRIB = yes +else ifneq ("$(wildcard $(TOP_DIR)/platforms/chibios/boards/$(BOARD)/configs/halconf_community.h)","") + USE_CHIBIOS_CONTRIB = yes +endif + +ifeq ($(strip $(USE_CHIBIOS_CONTRIB)),yes) + include $(CHIBIOS_CONTRIB)/os/hal/hal.mk + PLATFORM_SRC += $(PLATFORMSRC_CONTRIB) $(HALSRC_CONTRIB) + EXTRAINCDIRS += $(PLATFORMINC_CONTRIB) $(HALINC_CONTRIB) $(CHIBIOS_CONTRIB)/os/various +endif + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Injected configs +# +ifneq ("$(wildcard $(BOARD_PATH)/configs/config.h)","") + CONFIG_H += $(BOARD_PATH)/configs/config.h +endif +ifneq ("$(wildcard $(BOARD_PATH)/configs/post_config.h)","") + POST_CONFIG_H += $(BOARD_PATH)/configs/post_config.h +endif + +############################################################################## +# Compiler and Linker configuration +# + +# Use defined stack sizes of the main thread in linker scripts +LDSYMBOLS =--defsym=__process_stack_size__=$(USE_PROCESS_STACKSIZE),--defsym=__main_stack_size__=$(USE_EXCEPTIONS_STACKSIZE) + +# Shared Compiler flags for all toolchains +SHARED_CFLAGS = -fomit-frame-pointer \ + -ffunction-sections \ + -fdata-sections \ + -fno-common \ + -fshort-wchar + +# Shared Linker flags for all toolchains +SHARED_LDFLAGS = -T $(LDSCRIPT) \ + -Wl,$(LDSYMBOLS) \ + -Wl,--gc-sections \ + -nostartfiles + +ifeq ($(strip $(MCU)), risc-v) + # RISC-V toolchain specific configuration + # Find suitable GCC compiler + ifeq ($(strip $(TOOLCHAIN)),) + ifneq ($(shell which riscv32-unknown-elf-gcc 2>/dev/null),) + TOOLCHAIN = riscv32-unknown-elf- + else + ifneq ($(shell which riscv64-unknown-elf-gcc 2>/dev/null),) + TOOLCHAIN = riscv64-unknown-elf- + else + $(error "No RISC-V toolchain found. Can't find riscv32-unknown-elf-gcc or riscv64-unknown-elf-gcc found in your systems PATH variable. Please install a valid toolchain and make it accessible!") + endif + endif + endif + + # Default to compiling with picolibc for RISC-V targets if available, + # which is available by default on current (bullseye) debian based systems. + ifeq ($(shell $(TOOLCHAIN)gcc --specs=picolibc.specs -E - 2>/dev/null >/dev/null . + */ +#pragma once + +#include +#include "chibios_config.h" diff --git a/platforms/chibios/sleep_led.c b/platforms/chibios/sleep_led.c new file mode 100644 index 0000000000..477056a454 --- /dev/null +++ b/platforms/chibios/sleep_led.c @@ -0,0 +1,192 @@ +#include +#include + +#include "led.h" +#include "sleep_led.h" + +/* All right, we go the "software" way: timer, toggle LED in interrupt. + * Based on hasu's code for AVRs. + * Use LP timer on Kinetises, TIM14 on STM32F0. + */ + +#ifndef SLEEP_LED_GPT_DRIVER +# if defined(STM32F0XX) +# define SLEEP_LED_GPT_DRIVER GPTD14 +# endif +#endif + +#if defined(KL2x) || defined(K20x) || defined(SLEEP_LED_GPT_DRIVER) /* common parts for timers/interrupts */ + +/* Breathing Sleep LED brighness(PWM On period) table + * (64[steps] * 4[duration]) / 64[PWM periods/s] = 4 second breath cycle + * + * http://www.wolframalpha.com/input/?i=%28sin%28+x%2F64*pi%29**8+*+255%2C+x%3D0+to+63 + * (0..63).each {|x| p ((sin(x/64.0*PI)**8)*255).to_i } + */ +static const uint8_t breathing_table[64] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 4, 6, 10, 15, 23, 32, 44, 58, 74, 93, 113, 135, 157, 179, 199, 218, 233, 245, 252, 255, 252, 245, 233, 218, 199, 179, 157, 135, 113, 93, 74, 58, 44, 32, 23, 15, 10, 6, 4, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + +void sleep_led_timer_callback(void) { + /* Software PWM + * timer:1111 1111 1111 1111 + * \_____/\/ \_______/____ count(0-255) + * \ \______________ duration of step(4) + * \__________________ index of step table(0-63) + */ + + // this works for cca 65536 irqs/sec + static union { + uint16_t row; + struct { + uint8_t count : 8; + uint8_t duration : 2; + uint8_t index : 6; + } pwm; + } timer = {.row = 0}; + + timer.row++; + + // LED on + if (timer.pwm.count == 0) { + led_set(1 << USB_LED_CAPS_LOCK); + } + // LED off + if (timer.pwm.count == breathing_table[timer.pwm.index]) { + led_set(0); + } +} + +#endif /* common parts for known platforms */ + +#if defined(KL2x) || defined(K20x) /* platform selection: familiar Kinetis chips */ + +/* Use Low Power Timer (LPTMR) */ +# define TIMER_INTERRUPT_VECTOR KINETIS_LPTMR0_IRQ_VECTOR +# define RESET_COUNTER LPTMR0->CSR |= LPTMRx_CSR_TCF + +/* LPTMR clock options */ +# define LPTMR_CLOCK_MCGIRCLK 0 /* 4MHz clock */ +# define LPTMR_CLOCK_LPO 1 /* 1kHz clock */ +# define LPTMR_CLOCK_ERCLK32K 2 /* external 32kHz crystal */ +# define LPTMR_CLOCK_OSCERCLK 3 /* output from OSC */ + +/* Work around inconsistencies in Freescale naming */ +# if !defined(SIM_SCGC5_LPTMR) +# define SIM_SCGC5_LPTMR SIM_SCGC5_LPTIMER +# endif + +/* interrupt handler */ +OSAL_IRQ_HANDLER(TIMER_INTERRUPT_VECTOR) { + OSAL_IRQ_PROLOGUE(); + + sleep_led_timer_callback(); + + /* Reset the counter */ + RESET_COUNTER; + + OSAL_IRQ_EPILOGUE(); +} + +/* Initialise the timer */ +void sleep_led_init(void) { + /* Make sure the clock to the LPTMR is enabled */ + SIM->SCGC5 |= SIM_SCGC5_LPTMR; + /* Reset LPTMR settings */ + LPTMR0->CSR = 0; + /* Set the compare value */ + LPTMR0->CMR = 0; // trigger on counter value (i.e. every time) + +/* Set up clock source and prescaler */ +/* Software PWM + * ______ ______ __ + * | ON |___OFF___| ON |___OFF___| .... + * |<-------------->|<-------------->|<- .... + * PWM period PWM period + * + * R interrupts/period[resolution] + * F periods/second[frequency] + * R * F interrupts/second + */ + +/* === OPTION 1 === */ +# if 0 + // 1kHz LPO + // No prescaler => 1024 irqs/sec + // Note: this is too slow for a smooth breathe + LPTMR0->PSR = LPTMRx_PSR_PCS(LPTMR_CLOCK_LPO)|LPTMRx_PSR_PBYP; +# endif /* OPTION 1 */ + +/* === OPTION 2 === */ +# if 1 + // nMHz IRC (n=4 on KL25Z, KL26Z and K20x; n=2 or 8 on KL27Z) + MCG->C2 |= MCG_C2_IRCS; // fast (4MHz) internal ref clock +# if defined(KL27) // divide the 8MHz IRC by 2, to have the same MCGIRCLK speed as others + MCG->MC |= MCG_MC_LIRC_DIV2_DIV2; +# endif /* KL27 */ + MCG->C1 |= MCG_C1_IRCLKEN; // enable internal ref clock + // to work in stop mode, also MCG_C1_IREFSTEN + // Divide 4MHz by 2^N (N=6) => 62500 irqs/sec => + // => approx F=61, R=256, duration = 4 + LPTMR0->PSR = LPTMRx_PSR_PCS(LPTMR_CLOCK_MCGIRCLK) | LPTMRx_PSR_PRESCALE(6); +# endif /* OPTION 2 */ + +/* === OPTION 3 === */ +# if 0 + // OSC output (external crystal), usually 8MHz or 16MHz + OSC0->CR |= OSC_CR_ERCLKEN; // enable ext ref clock + // to work in stop mode, also OSC_CR_EREFSTEN + // Divide by 2^N + LPTMR0->PSR = LPTMRx_PSR_PCS(LPTMR_CLOCK_OSCERCLK)|LPTMRx_PSR_PRESCALE(7); +# endif /* OPTION 3 */ + /* === END OPTIONS === */ + + /* Interrupt on TCF set (compare flag) */ + nvicEnableVector(LPTMR0_IRQn, 2); // vector, priority + LPTMR0->CSR |= LPTMRx_CSR_TIE; +} + +void sleep_led_enable(void) { + /* Enable the timer */ + LPTMR0->CSR |= LPTMRx_CSR_TEN; +} + +void sleep_led_disable(void) { + /* Disable the timer */ + LPTMR0->CSR &= ~LPTMRx_CSR_TEN; +} + +void sleep_led_toggle(void) { + /* Toggle the timer */ + LPTMR0->CSR ^= LPTMRx_CSR_TEN; +} + +#elif defined(SLEEP_LED_GPT_DRIVER) + +static void gptTimerCallback(GPTDriver *gptp) { + (void)gptp; + sleep_led_timer_callback(); +} + +static const GPTConfig gptcfg = {1000000, gptTimerCallback, 0, 0}; + +/* Initialise the timer */ +void sleep_led_init(void) { gptStart(&SLEEP_LED_GPT_DRIVER, &gptcfg); } + +void sleep_led_enable(void) { gptStartContinuous(&SLEEP_LED_GPT_DRIVER, gptcfg.frequency / 0xFFFF); } + +void sleep_led_disable(void) { gptStopTimer(&SLEEP_LED_GPT_DRIVER); } + +void sleep_led_toggle(void) { (SLEEP_LED_GPT_DRIVER.state == GPT_READY) ? sleep_led_enable() : sleep_led_disable(); } + +#else /* platform selection: not on familiar chips */ + +void sleep_led_init(void) {} + +void sleep_led_enable(void) { led_set(1 << USB_LED_CAPS_LOCK); } + +void sleep_led_disable(void) { led_set(0); } + +void sleep_led_toggle(void) { + // not implemented +} + +#endif /* platform selection */ diff --git a/platforms/chibios/suspend.c b/platforms/chibios/suspend.c new file mode 100644 index 0000000000..9310a99920 --- /dev/null +++ b/platforms/chibios/suspend.c @@ -0,0 +1,92 @@ +/* TODO */ + +#include +#include + +#include "matrix.h" +#include "action.h" +#include "action_util.h" +#include "mousekey.h" +#include "programmable_button.h" +#include "host.h" +#include "suspend.h" +#include "led.h" +#include "wait.h" + +/** \brief suspend idle + * + * FIXME: needs doc + */ +void suspend_idle(uint8_t time) { + // TODO: this is not used anywhere - what units is 'time' in? + wait_ms(time); +} + +/** \brief suspend power down + * + * FIXME: needs doc + */ +void suspend_power_down(void) { + suspend_power_down_quantum(); + // on AVR, this enables the watchdog for 15ms (max), and goes to + // SLEEP_MODE_PWR_DOWN + + wait_ms(17); +} + +/** \brief suspend wakeup condition + * + * FIXME: needs doc + */ +__attribute__((weak)) void matrix_power_up(void) {} +__attribute__((weak)) void matrix_power_down(void) {} +bool suspend_wakeup_condition(void) { + matrix_power_up(); + matrix_scan(); + matrix_power_down(); + for (uint8_t r = 0; r < MATRIX_ROWS; r++) { + if (matrix_get_row(r)) return true; + } + return false; +} + +/** \brief run user level code immediately after wakeup + * + * FIXME: needs doc + */ +__attribute__((weak)) void suspend_wakeup_init_user(void) {} + +/** \brief run keyboard level code immediately after wakeup + * + * FIXME: needs doc + */ +__attribute__((weak)) void suspend_wakeup_init_kb(void) { suspend_wakeup_init_user(); } + +/** \brief suspend wakeup condition + * + * run immediately after wakeup + * FIXME: needs doc + */ +void suspend_wakeup_init(void) { + // clear keyboard state + // need to do it manually, because we're running from ISR + // and clear_keyboard() calls print + // so only clear the variables in memory + // the reports will be sent from main.c afterwards + // or if the PC asks for GET_REPORT + clear_mods(); + clear_weak_mods(); + clear_keys(); +#ifdef MOUSEKEY_ENABLE + mousekey_clear(); +#endif /* MOUSEKEY_ENABLE */ +#ifdef PROGRAMMABLE_BUTTON_ENABLE + programmable_button_clear(); +#endif /* PROGRAMMABLE_BUTTON_ENABLE */ +#ifdef EXTRAKEY_ENABLE + host_system_send(0); + host_consumer_send(0); +#endif /* EXTRAKEY_ENABLE */ + + suspend_wakeup_init_quantum(); +} diff --git a/platforms/chibios/syscall-fallbacks.c b/platforms/chibios/syscall-fallbacks.c new file mode 100644 index 0000000000..4569879c7c --- /dev/null +++ b/platforms/chibios/syscall-fallbacks.c @@ -0,0 +1,110 @@ +/* Copyright 2021 Nick Brassel, QMK + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include + +/* To compile the ChibiOS syscall stubs with picolibc + * the _reent struct has to be defined. */ +#if defined(USE_PICOLIBC) +struct _reent; +#endif + +#pragma GCC diagnostic ignored "-Wmissing-prototypes" + +__attribute__((weak, used)) int _open_r(struct _reent *r, const char *path, int flag, int m) { + __errno_r(r) = ENOENT; + return -1; +} + +__attribute__((weak, used)) int _lseek_r(struct _reent *r, int file, int ptr, int dir) { + __errno_r(r) = EBADF; + return -1; +} + +__attribute__((weak, used)) int _read_r(struct _reent *r, int file, char *ptr, int len) { + __errno_r(r) = EBADF; + return -1; +} + +__attribute__((weak, used)) int _write_r(struct _reent *r, int file, char *ptr, int len) { + __errno_r(r) = EBADF; + return -1; +} + +__attribute__((weak, used)) int _close_r(struct _reent *r, int file) { + __errno_r(r) = EBADF; + return -1; +} + +__attribute__((weak, used)) int _link_r(struct _reent *r, const char *oldpath, const char *newpath) { + __errno_r(r) = EPERM; + return -1; +} + +__attribute__((weak, used)) int _unlink_r(struct _reent *r, const char *path) { + __errno_r(r) = EPERM; + return -1; +} + +__attribute__((weak, used)) clock_t _times_r(struct _reent *r, void *t) { + __errno_r(r) = EFAULT; + return -1; +} + +__attribute__((weak, used)) int _fstat_r(struct _reent *r, int file, struct stat *st) { + __errno_r(r) = EBADF; + return -1; +} + +__attribute__((weak, used)) int _isatty_r(struct _reent *r, int fd) { + __errno_r(r) = EBADF; + return 0; +} + +__attribute__((weak, used)) caddr_t _sbrk_r(struct _reent *r, int incr) { + __errno_r(r) = ENOMEM; + return (caddr_t)-1; +} + +__attribute__((weak, used)) int _kill(int pid, int sig) { + errno = EPERM; + return -1; +} + +__attribute__((weak, used)) pid_t _getpid(void) { return 1; } + +__attribute__((weak, used)) void _fini(void) { return; } + +__attribute__((weak, used, noreturn)) void _exit(int i) { + while (1) + ; +} + +__attribute__((weak, used)) int _gettimeofday_r(struct _reent *r, struct timeval *t, void *tzp) { + __errno_r(r) = EPERM; + return -1; +} + +__attribute__((weak, used)) void *__dso_handle; + +__attribute__((weak, used)) void __cxa_pure_virtual(void) { + while (1) + ; +} + +#pragma GCC diagnostic pop diff --git a/platforms/chibios/timer.c b/platforms/chibios/timer.c new file mode 100644 index 0000000000..9f664e1f79 --- /dev/null +++ b/platforms/chibios/timer.c @@ -0,0 +1,47 @@ +#include + +#include "timer.h" + +static uint32_t reset_point = 0; +#if CH_CFG_ST_RESOLUTION < 32 +static uint32_t last_systime = 0; +static uint32_t overflow = 0; +#endif + +void timer_init(void) { timer_clear(); } + +void timer_clear(void) { + reset_point = (uint32_t)chVTGetSystemTime(); +#if CH_CFG_ST_RESOLUTION < 32 + last_systime = reset_point; + overflow = 0; +#endif +} + +uint16_t timer_read(void) { return (uint16_t)timer_read32(); } + +uint32_t timer_read32(void) { + uint32_t systime = (uint32_t)chVTGetSystemTime(); + +#if CH_CFG_ST_RESOLUTION < 32 + // If/when we need to support 64-bit chips, this may need to be modified to match the native bit-ness of the MCU. + // At this point, the only SysTick resolution allowed other than 32 is 16 bit. + // In the 16-bit case, at: + // - CH_CFG_ST_FREQUENCY = 100000, overflow will occur every ~0.65 seconds + // - CH_CFG_ST_FREQUENCY = 10000, overflow will occur every ~6.5 seconds + // - CH_CFG_ST_FREQUENCY = 1000, overflow will occur every ~65 seconds + // With this implementation, as long as we ensure a timer read happens at least once during the overflow period, timing should be accurate. + if (systime < last_systime) { + overflow += ((uint32_t)1) << CH_CFG_ST_RESOLUTION; + } + + last_systime = systime; + return (uint32_t)TIME_I2MS(systime - reset_point + overflow); +#else + return (uint32_t)TIME_I2MS(systime - reset_point); +#endif +} + +uint16_t timer_elapsed(uint16_t last) { return TIMER_DIFF_16(timer_read(), last); } + +uint32_t timer_elapsed32(uint32_t last) { return TIMER_DIFF_32(timer_read32(), last); } diff --git a/platforms/chibios/wait.c b/platforms/chibios/wait.c new file mode 100644 index 0000000000..56fd6ffcec --- /dev/null +++ b/platforms/chibios/wait.c @@ -0,0 +1,41 @@ +/* Copyright 2021 QMK + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +#include "_wait.h" + +#ifdef WAIT_US_TIMER +void wait_us(uint16_t duration) { + static const GPTConfig gpt_cfg = {1000000, NULL, 0, 0}; /* 1MHz timer, no callback */ + + if (duration == 0) { + duration = 1; + } + + /* + * Only use this timer on the main thread; + * other threads need to use their own timer. + */ + if (chThdGetSelfX() == &ch.mainthread && duration < (1ULL << (sizeof(gptcnt_t) * 8))) { + gptStart(&WAIT_US_TIMER, &gpt_cfg); + gptPolledDelay(&WAIT_US_TIMER, duration); + } else { + chThdSleepMicroseconds(duration); + } +} +#endif -- cgit v1.2.3