From 1f2b1dedccdf21b629c45ece80b4ca32f6653296 Mon Sep 17 00:00:00 2001 From: Nick Brassel Date: Wed, 13 Apr 2022 18:00:18 +1000 Subject: Quantum Painter (#10174) * Install dependencies before executing unit tests. * Split out UTF-8 decoder. * Fixup python formatting rules. * Add documentation for QGF/QFF and the RLE format used. * Add CLI commands for converting images and fonts. * Add stub rules.mk for QP. * Add stream type. * Add base driver and comms interfaces. * Add support for SPI, SPI+D/C comms drivers. * Include when enabled. * Add base support for SPI+D/C+RST panels, as well as concrete implementation of ST7789. * Add support for GC9A01. * Add support for ILI9341. * Add support for ILI9163. * Add support for SSD1351. * Implement qp_setpixel, including pixdata buffer management. * Implement qp_line. * Implement qp_rect. * Implement qp_circle. * Implement qp_ellipse. * Implement palette interpolation. * Allow for streams to work with either flash or RAM. * Image loading. * Font loading. * QGF palette loading. * Progressive decoder of pixel data supporting Raw+RLE, 1-,2-,4-,8-bpp monochrome and palette-based images. * Image drawing. * Animations. * Font rendering. * Check against 256 colours, dump out the loaded palette if debugging enabled. * Fix build. * AVR is not the intended audience. * `qmk format-c` * Generation fix. * First batch of docs. * More docs and examples. * Review comments. * Public API documentation. --- drivers/painter/gc9a01/qp_gc9a01.c | 150 +++++++++++++++++++++++++++++ drivers/painter/gc9a01/qp_gc9a01.h | 37 +++++++ drivers/painter/gc9a01/qp_gc9a01_opcodes.h | 78 +++++++++++++++ 3 files changed, 265 insertions(+) create mode 100644 drivers/painter/gc9a01/qp_gc9a01.c create mode 100644 drivers/painter/gc9a01/qp_gc9a01.h create mode 100644 drivers/painter/gc9a01/qp_gc9a01_opcodes.h (limited to 'drivers/painter/gc9a01') diff --git a/drivers/painter/gc9a01/qp_gc9a01.c b/drivers/painter/gc9a01/qp_gc9a01.c new file mode 100644 index 0000000000..ad76d58b07 --- /dev/null +++ b/drivers/painter/gc9a01/qp_gc9a01.c @@ -0,0 +1,150 @@ +// Copyright 2021 Paul Cotter (@gr1mr3aver) +// SPDX-License-Identifier: GPL-2.0-or-later + +#include +#include "qp_internal.h" +#include "qp_comms.h" +#include "qp_gc9a01.h" +#include "qp_gc9a01_opcodes.h" +#include "qp_tft_panel.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// Driver storage +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +tft_panel_dc_reset_painter_device_t gc9a01_drivers[GC9A01_NUM_DEVICES] = {0}; + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// Initialization +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +bool qp_gc9a01_init(painter_device_t device, painter_rotation_t rotation) { + // A lot of these "unknown" opcodes are sourced from other OSS projects and are seemingly required for this display to function. + // clang-format off + const uint8_t gc9a01_init_sequence[] = { + // Command, Delay, N, Data[N] + GC9A01_SET_INTER_REG_ENABLE2, 0, 0, + 0xEB, 0, 1, 0x14, + GC9A01_SET_INTER_REG_ENABLE1, 0, 0, + GC9A01_SET_INTER_REG_ENABLE2, 0, 0, + 0xEB, 0, 1, 0x14, + 0x84, 0, 1, 0x40, + 0x85, 0, 1, 0xFF, + 0x86, 0, 1, 0xFF, + 0x87, 0, 1, 0xFF, + 0x88, 0, 1, 0x0A, + 0x89, 0, 1, 0x21, + 0x8a, 0, 1, 0x00, + 0x8b, 0, 1, 0x80, + 0x8c, 0, 1, 0x01, + 0x8d, 0, 1, 0x01, + 0x8e, 0, 1, 0xFF, + 0x8f, 0, 1, 0xFF, + GC9A01_SET_FUNCTION_CTL, 0, 2, 0x00, 0x20, + GC9A01_SET_PIX_FMT, 0, 1, 0x55, + 0x90, 0, 4, 0x08, 0x08, 0x08, 0x08, + 0xBD, 0, 1, 0x06, + 0xBC, 0, 1, 0x00, + 0xFF, 0, 3, 0x60, 0x01, 0x04, + GC9A01_SET_POWER_CTL_2, 0, 1, 0x13, + GC9A01_SET_POWER_CTL_3, 0, 1, 0x13, + GC9A01_SET_POWER_CTL_4, 0, 1, 0x22, + 0xBE, 0, 1, 0x11, + 0xE1, 0, 2, 0x10, 0x0E, + 0xDF, 0, 3, 0x21, 0x0C, 0x02, + GC9A01_SET_GAMMA1, 0, 6, 0x45, 0x09, 0x08, 0x08, 0x26, 0x2A, + GC9A01_SET_GAMMA2, 0, 6, 0x43, 0x70, 0x72, 0x36, 0x37, 0x6F, + GC9A01_SET_GAMMA3, 0, 6, 0x45, 0x09, 0x08, 0x08, 0x26, 0x2A, + GC9A01_SET_GAMMA4, 0, 6, 0x43, 0x70, 0x72, 0x36, 0x37, 0x6F, + 0xED, 0, 2, 0x1B, 0x0B, + 0xAE, 0, 1, 0x77, + 0xCD, 0, 1, 0x63, + 0x70, 0, 9, 0x07, 0x07, 0x04, 0x0E, 0x0F, 0x09, 0x07, 0x08, 0x03, + GC9A01_SET_FRAME_RATE, 0, 1, 0x34, + 0x62, 0, 12, 0x18, 0x0D, 0x71, 0xED, 0x70, 0x70, 0x18, 0x0F, 0x71, 0xEF, 0x70, 0x70, + 0x63, 0, 12, 0x18, 0x11, 0x71, 0xF1, 0x70, 0x70, 0x18, 0x13, 0x71, 0xF3, 0x70, 0x70, + 0x64, 0, 7, 0x28, 0x29, 0xF1, 0x01, 0xF1, 0x00, 0x07, + 0x66, 0, 10, 0x3C, 0x00, 0xCD, 0x67, 0x45, 0x45, 0x10, 0x00, 0x00, 0x00, + 0x67, 0, 10, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0x54, 0x10, 0x32, 0x98, + 0x74, 0, 7, 0x10, 0x85, 0x80, 0x00, 0x00, 0x4E, 0x00, + 0x98, 0, 2, 0x3E, 0x07, + GC9A01_CMD_TEARING_OFF, 0, 0, + GC9A01_CMD_INVERT_OFF, 0, 0, + GC9A01_CMD_SLEEP_OFF, 120, 0, + GC9A01_CMD_DISPLAY_ON, 20, 0 + }; + // clang-format on + + // clang-format on + qp_comms_bulk_command_sequence(device, gc9a01_init_sequence, sizeof(gc9a01_init_sequence)); + + // Configure the rotation (i.e. the ordering and direction of memory writes in GRAM) + const uint8_t madctl[] = { + [QP_ROTATION_0] = GC9A01_MADCTL_BGR, + [QP_ROTATION_90] = GC9A01_MADCTL_BGR | GC9A01_MADCTL_MX | GC9A01_MADCTL_MV, + [QP_ROTATION_180] = GC9A01_MADCTL_BGR | GC9A01_MADCTL_MX | GC9A01_MADCTL_MY, + [QP_ROTATION_270] = GC9A01_MADCTL_BGR | GC9A01_MADCTL_MV | GC9A01_MADCTL_MY, + }; + qp_comms_command_databyte(device, GC9A01_SET_MEM_ACS_CTL, madctl[rotation]); + + return true; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// Driver vtable +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +const struct tft_panel_dc_reset_painter_driver_vtable_t gc9a01_driver_vtable = { + .base = + { + .init = qp_gc9a01_init, + .power = qp_tft_panel_power, + .clear = qp_tft_panel_clear, + .flush = qp_tft_panel_flush, + .pixdata = qp_tft_panel_pixdata, + .viewport = qp_tft_panel_viewport, + .palette_convert = qp_tft_panel_palette_convert, + .append_pixels = qp_tft_panel_append_pixels, + }, + .rgb888_to_native16bit = qp_rgb888_to_rgb565_swapped, + .num_window_bytes = 2, + .swap_window_coords = false, + .opcodes = + { + .display_on = GC9A01_CMD_DISPLAY_ON, + .display_off = GC9A01_CMD_DISPLAY_OFF, + .set_column_address = GC9A01_SET_COL_ADDR, + .set_row_address = GC9A01_SET_PAGE_ADDR, + .enable_writes = GC9A01_SET_MEM, + }, +}; + +#ifdef QUANTUM_PAINTER_GC9A01_SPI_ENABLE +// Factory function for creating a handle to the ILI9341 device +painter_device_t qp_gc9a01_make_spi_device(uint16_t panel_width, uint16_t panel_height, pin_t chip_select_pin, pin_t dc_pin, pin_t reset_pin, uint16_t spi_divisor, int spi_mode) { + for (uint32_t i = 0; i < GC9A01_NUM_DEVICES; ++i) { + tft_panel_dc_reset_painter_device_t *driver = &gc9a01_drivers[i]; + if (!driver->base.driver_vtable) { + driver->base.driver_vtable = (const struct painter_driver_vtable_t *)&gc9a01_driver_vtable; + driver->base.comms_vtable = (const struct painter_comms_vtable_t *)&spi_comms_with_dc_vtable; + driver->base.native_bits_per_pixel = 16; // RGB565 + driver->base.panel_width = panel_width; + driver->base.panel_height = panel_height; + driver->base.rotation = QP_ROTATION_0; + driver->base.offset_x = 0; + driver->base.offset_y = 0; + + // SPI and other pin configuration + driver->base.comms_config = &driver->spi_dc_reset_config; + driver->spi_dc_reset_config.spi_config.chip_select_pin = chip_select_pin; + driver->spi_dc_reset_config.spi_config.divisor = spi_divisor; + driver->spi_dc_reset_config.spi_config.lsb_first = false; + driver->spi_dc_reset_config.spi_config.mode = spi_mode; + driver->spi_dc_reset_config.dc_pin = dc_pin; + driver->spi_dc_reset_config.reset_pin = reset_pin; + return (painter_device_t)driver; + } + } + return NULL; +} + +#endif // QUANTUM_PAINTER_GC9A01_SPI_ENABLE diff --git a/drivers/painter/gc9a01/qp_gc9a01.h b/drivers/painter/gc9a01/qp_gc9a01.h new file mode 100644 index 0000000000..e2b1939564 --- /dev/null +++ b/drivers/painter/gc9a01/qp_gc9a01.h @@ -0,0 +1,37 @@ +// Copyright 2021 Paul Cotter (@gr1mr3aver) +// SPDX-License-Identifier: GPL-2.0-or-later + +#pragma once + +#include "gpio.h" +#include "qp_internal.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// Quantum Painter GC9A01 configurables (add to your keyboard's config.h) + +#ifndef GC9A01_NUM_DEVICES +/** + * @def This controls the maximum number of GC9A01 devices that Quantum Painter can communicate with at any one time. + * Increasing this number allows for multiple displays to be used. + */ +# define GC9A01_NUM_DEVICES 1 +#endif + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// Quantum Painter GC9A01 device factories + +#ifdef QUANTUM_PAINTER_GC9A01_SPI_ENABLE +/** + * Factory method for an GC9A01 SPI LCD device. + * + * @param panel_width[in] the width of the display panel + * @param panel_height[in] the height of the display panel + * @param chip_select_pin[in] the GPIO pin used for SPI chip select + * @param dc_pin[in] the GPIO pin used for D/C control + * @param reset_pin[in] the GPIO pin used for RST + * @param spi_divisor[in] the SPI divisor to use when communicating with the display + * @param spi_mode[in] the SPI mode to use when communicating with the display + * @return the device handle used with all drawing routines in Quantum Painter + */ +painter_device_t qp_gc9a01_make_spi_device(uint16_t panel_width, uint16_t panel_height, pin_t chip_select_pin, pin_t dc_pin, pin_t reset_pin, uint16_t spi_divisor, int spi_mode); +#endif // QUANTUM_PAINTER_GC9A01_SPI_ENABLE diff --git a/drivers/painter/gc9a01/qp_gc9a01_opcodes.h b/drivers/painter/gc9a01/qp_gc9a01_opcodes.h new file mode 100644 index 0000000000..6ff4efe7a8 --- /dev/null +++ b/drivers/painter/gc9a01/qp_gc9a01_opcodes.h @@ -0,0 +1,78 @@ +// Copyright 2021 Paul Cotter (@gr1mr3aver) +// SPDX-License-Identifier: GPL-2.0-or-later + +#pragma once + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// Quantum Painter GC9A01 command opcodes +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// Level 1 command opcodes + +#define GC9A01_GET_ID_INFO 0x04 // Get ID information +#define GC9A01_GET_STATUS 0x09 // Get status +#define GC9A01_CMD_SLEEP_ON 0x10 // Enter sleep mode +#define GC9A01_CMD_SLEEP_OFF 0x11 // Exit sleep mode +#define GC9A01_CMD_PARTIAL_ON 0x12 // Enter partial mode +#define GC9A01_CMD_PARTIAL_OFF 0x13 // Exit partial mode +#define GC9A01_CMD_INVERT_ON 0x20 // Enter inverted mode +#define GC9A01_CMD_INVERT_OFF 0x21 // Exit inverted mode +#define GC9A01_CMD_DISPLAY_OFF 0x28 // Disable display +#define GC9A01_CMD_DISPLAY_ON 0x29 // Enable display +#define GC9A01_SET_COL_ADDR 0x2A // Set column address +#define GC9A01_SET_PAGE_ADDR 0x2B // Set page address +#define GC9A01_SET_MEM 0x2C // Set memory +#define GC9A01_SET_PARTIAL_AREA 0x30 // Set partial area +#define GC9A01_SET_VSCROLL 0x33 // Set vertical scroll def +#define GC9A01_CMD_TEARING_ON 0x34 // Tearing line enabled +#define GC9A01_CMD_TEARING_OFF 0x35 // Tearing line disabled +#define GC9A01_SET_MEM_ACS_CTL 0x36 // Set mem access ctl +#define GC9A01_SET_VSCROLL_ADDR 0x37 // Set vscroll start addr +#define GC9A01_CMD_IDLE_OFF 0x38 // Exit idle mode +#define GC9A01_CMD_IDLE_ON 0x39 // Enter idle mode +#define GC9A01_SET_PIX_FMT 0x3A // Set pixel format +#define GC9A01_SET_MEM_CONT 0x3C // Set memory continue +#define GC9A01_SET_TEAR_SCANLINE 0x44 // Set tearing scanline +#define GC9A01_GET_TEAR_SCANLINE 0x45 // Get tearing scanline +#define GC9A01_SET_BRIGHTNESS 0x51 // Set brightness +#define GC9A01_SET_DISPLAY_CTL 0x53 // Set display ctl +#define GC9A01_GET_ID1 0xDA // Get ID1 +#define GC9A01_GET_ID2 0xDB // Get ID2 +#define GC9A01_GET_ID3 0xDC // Get ID3 + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// Level 2 command opcodes + +#define GC9A01_SET_RGB_IF_SIG_CTL 0xB0 // RGB IF signal ctl +#define GC9A01_SET_BLANKING_PORCH_CTL 0xB5 // Set blanking porch ctl +#define GC9A01_SET_FUNCTION_CTL 0xB6 // Set function ctl +#define GC9A01_SET_TEARING_EFFECT 0xBA // Set backlight ctl 3 +#define GC9A01_SET_IF_CTL 0xF6 // Set interface control + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// Level 3 command opcodes + +#define GC9A01_SET_FRAME_RATE 0xE8 // Set frame rate +#define GC9A01_SET_SPI_2DATA 0xE9 // Set frame rate +#define GC9A01_SET_POWER_CTL_1 0xC1 // Set power ctl 1 +#define GC9A01_SET_POWER_CTL_2 0xC3 // Set power ctl 2 +#define GC9A01_SET_POWER_CTL_3 0xC4 // Set power ctl 3 +#define GC9A01_SET_POWER_CTL_4 0xC9 // Set power ctl 4 +#define GC9A01_SET_POWER_CTL_7 0xA7 // Set power ctl 7 +#define GC9A01_SET_INTER_REG_ENABLE1 0xFE // Enable Inter Register 1 +#define GC9A01_SET_INTER_REG_ENABLE2 0xEF // Enable Inter Register 2 +#define GC9A01_SET_GAMMA1 0xF0 // +#define GC9A01_SET_GAMMA2 0xF1 +#define GC9A01_SET_GAMMA3 0xF2 +#define GC9A01_SET_GAMMA4 0xF3 + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// MADCTL Flags +#define GC9A01_MADCTL_MY 0b10000000 +#define GC9A01_MADCTL_MX 0b01000000 +#define GC9A01_MADCTL_MV 0b00100000 +#define GC9A01_MADCTL_ML 0b00010000 +#define GC9A01_MADCTL_RGB 0b00000000 +#define GC9A01_MADCTL_BGR 0b00001000 +#define GC9A01_MADCTL_MH 0b00000100 -- cgit v1.2.3