diff options
Diffstat (limited to 'tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40')
4 files changed, 381 insertions, 0 deletions
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h new file mode 100644 index 0000000000..3db5f772a8 --- /dev/null +++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h @@ -0,0 +1,130 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 Nordic Semiconductor + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PORT_SHIFT 3 + +typedef enum { + NC = (int)0xFFFFFFFF, + p0 = 0, + p1 = 1, + p2 = 2, + p3 = 3, + p4 = 4, + p5 = 5, + p6 = 6, + p7 = 7, + p8 = NC, + p9 = NC, + p10 = NC, + p11 = NC, + p12 = NC, + p13 = 13, + p14 = NC, + p15 = NC, + p16 = 16, + p17 = 17, + p18 = NC, + p19 = 19, + p20 = 20, + p21 = 21, + p22 = 22, + p23 = 23, + p24 = 24, + p25 = 25, + p26 = 26, + p27 = 27, + p28 = NC, + p29 = 29, + p30 = 30, + p31 = 31, + + LED1 = p7, + LED2 = p13, + + BUTTON0 = p16, + BUTTON1 = p17, + + RX_PIN_NUMBER = p23, + TX_PIN_NUMBER = p25, + + // mBed interface Pins + USBTX = TX_PIN_NUMBER, + USBRX = RX_PIN_NUMBER, + + SPI_PSELMOSI0 = p24, + SPI_PSELMISO0 = p29, + SPI_PSELSS0 = p6, + SPI_PSELSCK0 = p21, + + SPIS_PSELMOSI = p24, + SPIS_PSELMISO = p29, + SPIS_PSELSS = p6, + SPIS_PSELSCK = p21, + + I2C_SDA0 = p22, + I2C_SCL0 = p20, + + A0 = p0, + A1 = p1, + A2 = p2, + A3 = p3, + A4 = p4, + A5 = p5, + + SWIO = p19, + VERF0 = p0, + + // SPI for controlling internal flash, don't use it. + FLASH_SPIMOSI = 15, + FLASH_SPIMISO = 9, + FLASH_SPICS = 28, + FLASH_SPICLK = 11, + // Not connected + CTS_PIN_NUMBER= NC, + RTS_PIN_NUMBER= NC, + SPI_PSELMOSI1 = NC, + SPI_PSELMISO1 = NC, + SPI_PSELSS1 = NC, + SPI_PSELSCK1 = NC, + LED3 = NC, + LED4 = NC +} PinName; + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 3, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/device.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/device.h new file mode 100644 index 0000000000..2b5a0b6b3f --- /dev/null +++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/device.h @@ -0,0 +1,57 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 0 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 1 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 1 + +#define DEVICE_STDIO_MESSAGES 0 + +#define DEVICE_ERROR_PATTERN 1 + +#include "objects.h" + +#endif diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c new file mode 100644 index 0000000000..d3d2fe0d64 --- /dev/null +++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c @@ -0,0 +1,123 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "cmsis.h" + + +#define SPIM1_SCK_PIN 11u /**< SPI clock GPIO pin number. */ +#define SPIM1_MOSI_PIN 15u /**< SPI Master Out Slave In GPIO pin number. */ +#define SPIM1_MISO_PIN 9u /**< SPI Master In Slave Out GPIO pin number. */ +#define SPIM1_SS_PIN 28u /**< SPI Slave Select GPIO pin number. */ + +#define CMD_POWER_UP (0xAB) +#define CMD_POWER_DOWN (0xB9) + +void spi_flash_init(void) +{ + NRF_GPIO->PIN_CNF[SPIM1_MOSI_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) + | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) + | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) + | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) + | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos); + NRF_GPIO->PIN_CNF[SPIM1_MISO_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) + | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) + | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) + | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) + | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos); + NRF_GPIO->PIN_CNF[SPIM1_SCK_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) + | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) + | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) + | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) + | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos); + + NRF_GPIO->PIN_CNF[SPIM1_SS_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) + | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) + | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) + | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) + | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + //cs = 1; + NRF_GPIO->OUTSET = (GPIO_OUTSET_PIN28_High << GPIO_OUTSET_PIN28_Pos); + + NRF_SPI1->ENABLE = 1; + NRF_SPI1->PSELSCK = SPIM1_SCK_PIN; + NRF_SPI1->PSELMOSI = SPIM1_MISO_PIN; + NRF_SPI1->PSELMISO = SPIM1_MOSI_PIN; + //spi.frequency(1000000); + NRF_SPI1->FREQUENCY = 0x10000000; //1MHz + + //spi.format(8,0); + uint32_t config_mode = 0; + config_mode = (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos); //mode 0 + NRF_SPI1->CONFIG = (config_mode | (SPI_CONFIG_ORDER_MsbFirst << SPI_CONFIG_ORDER_Pos)); + //cs = 0; + NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN28_Clear << GPIO_OUTCLR_PIN28_Pos); + //spi.write(CMD_POWER_UP); + while (!NRF_SPI1->EVENTS_READY == 0) { + } + NRF_SPI1->TXD = (uint32_t)CMD_POWER_UP; + while (!NRF_SPI1->EVENTS_READY == 1) { + } + NRF_SPI1->EVENTS_READY = 0; + NRF_SPI1->RXD; + //wait_ms(30); + // Deselect the device + //cs = 1; + NRF_GPIO->OUTSET = (GPIO_OUTSET_PIN28_High << GPIO_OUTSET_PIN28_Pos); + +} + +void spi_flash_powerDown(void) +{ + NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN28_Clear << GPIO_OUTCLR_PIN28_Pos); + //spi.write(CMD_POWER_DOWN); + while (!NRF_SPI1->EVENTS_READY == 0) { + } + NRF_SPI1->TXD = (uint32_t)CMD_POWER_DOWN; + while (!NRF_SPI1->EVENTS_READY == 1) { + } + NRF_SPI1->EVENTS_READY = 0; + NRF_SPI1->RXD; + NRF_GPIO->OUTSET = (GPIO_OUTSET_PIN28_High << GPIO_OUTSET_PIN28_Pos); + + //wait for sleep + //wait_us(3); +} + +void mbed_sdk_init() +{ + // Default SWIO setting, pull SWIO(p19) to low for turning antenna switch to BLE radiated path + NRF_GPIO->PIN_CNF[19] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) + | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) + | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) + | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos) + | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + + NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN19_Clear << GPIO_OUTCLR_PIN19_Pos); + + // Config External Crystal to 32MHz + NRF_CLOCK->XTALFREQ = 0x00; + NRF_CLOCK->EVENTS_HFCLKSTARTED = 0; + NRF_CLOCK->TASKS_HFCLKSTART = 1; + while (NRF_CLOCK->EVENTS_HFCLKSTARTED == 0) + {// Do nothing. + } + + spi_flash_init(); + + //nrf_delay_ms(10); + spi_flash_powerDown(); + +} diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/rtc_api.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/rtc_api.c new file mode 100644 index 0000000000..527d308058 --- /dev/null +++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/rtc_api.c @@ -0,0 +1,71 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "rtc_api.h" + + +#define LFCLK_FREQUENCY (32768UL) +#define RTC0_COUNTER_PRESCALER ((LFCLK_FREQUENCY/8) - 1) +#define COMPARE_COUNTERTIME (691200UL) //86400 x 8 + + +time_t initTime; + +void rtc_init(void) { + + NVIC_EnableIRQ(RTC0_IRQn); // Enable Interrupt for the RTC in the core. + //NRF_RTC0->TASKS_STOP =1; + NRF_RTC0->PRESCALER = RTC0_COUNTER_PRESCALER; // Set prescaler to a TICK of RTC_FREQUENCY. + NRF_RTC0->CC[0] = COMPARE_COUNTERTIME; // Compare0 after approx COMPARE_COUNTERTIME seconds. + + // Enable COMPARE0 event and COMPARE0 interrupt: + NRF_RTC0->EVTENSET = RTC_EVTENSET_COMPARE0_Msk; + NRF_RTC0->INTENSET = RTC_INTENSET_COMPARE0_Msk; + NRF_RTC0->TASKS_START = 1; +} + +void rtc_free(void) { + // [TODO] +} + +/* + * Little check routine to see if the RTC has been enabled + * + * Clock Control Register + * RTC_CCR[0] : 0 = Disabled, 1 = Enabled + * + */ +int rtc_isenabled(void) { + // [TODO] return(((NRF_RTC0->TASKS_START) & 0x01) != 0); +} + +time_t rtc_read(void) { + + time_t t = initTime; + t += (86400*NRF_RTC0->EVENTS_COMPARE[0]); + t += (int)((NRF_RTC0->COUNTER)/8); + return(t); +} + +void rtc_write(time_t t) { + // Convert the time in to a tm + + // Pause clock, and clear counter register (clears us count) + NRF_RTC0->TASKS_STOP = 1; + + initTime = t; + // Restart clock + NRF_RTC0->TASKS_START = 1; +} |