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diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/fsl_bitaccess.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/fsl_bitaccess.h
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+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/fsl_bitaccess.h
@@ -0,0 +1,526 @@
+/*
+** ###################################################################
+** Version: rev. 2.5, 2014-05-06
+** Build: b140604
+**
+** Abstract:
+** Register bit field access macros.
+**
+** Copyright (c) 2014 Freescale Semiconductor, Inc.
+** All rights reserved.
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2013-07-23)
+** Initial version.
+** - rev. 1.1 (2013-09-17)
+** RM rev. 0.4 update.
+** - rev. 2.0 (2013-10-29)
+** Register accessor macros added to the memory map.
+** Symbols for Processor Expert memory map compatibility added to the memory map.
+** Startup file for gcc has been updated according to CMSIS 3.2.
+** System initialization updated.
+** - rev. 2.1 (2013-10-30)
+** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+** - rev. 2.2 (2013-12-20)
+** Update according to reference manual rev. 0.6,
+** - rev. 2.3 (2014-01-13)
+** Update according to reference manual rev. 0.61,
+** - rev. 2.4 (2014-02-10)
+** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
+** - rev. 2.5 (2014-05-06)
+** Update according to reference manual rev. 1.0,
+** Update of system and startup files.
+** Module access macro module_BASES replaced by module_BASE_PTRS.
+**
+** ###################################################################
+*/
+
+
+#ifndef _FSL_BITACCESS_H
+#define _FSL_BITACCESS_H 1
+
+#include <stdint.h>
+#include <stdlib.h>
+
+/**
+ * @brief Macro to access a single bit of a 32-bit peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_ACCESS32(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
+
+/**
+ * @brief Macro to access a single bit of a 16-bit peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_ACCESS16(Reg,Bit) (*((uint16_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
+
+/**
+ * @brief Macro to access a single bit of an 8-bit peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_ACCESS8(Reg,Bit) (*((uint8_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
+
+/*
+ * Macros for single instance registers
+ */
+
+#define BF_SET(reg, field) HW_##reg##_SET(BM_##reg##_##field)
+#define BF_CLR(reg, field) HW_##reg##_CLR(BM_##reg##_##field)
+#define BF_TOG(reg, field) HW_##reg##_TOG(BM_##reg##_##field)
+
+#define BF_SETV(reg, field, v) HW_##reg##_SET(BF_##reg##_##field(v))
+#define BF_CLRV(reg, field, v) HW_##reg##_CLR(BF_##reg##_##field(v))
+#define BF_TOGV(reg, field, v) HW_##reg##_TOG(BF_##reg##_##field(v))
+
+#define BV_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
+#define BV_VAL(reg, field, sym) BV_##reg##_##field##__##sym
+
+#define BF_RD(reg, field) HW_##reg.B.field
+#define BF_WR(reg, field, v) BW_##reg##_##field(v)
+
+#define BF_CS1(reg, f1, v1) \
+ (HW_##reg##_CLR(BM_##reg##_##f1), \
+ HW_##reg##_SET(BF_##reg##_##f1(v1)))
+
+#define BF_CS2(reg, f1, v1, f2, v2) \
+ (HW_##reg##_CLR(BM_##reg##_##f1 | \
+ BM_##reg##_##f2), \
+ HW_##reg##_SET(BF_##reg##_##f1(v1) | \
+ BF_##reg##_##f2(v2)))
+
+#define BF_CS3(reg, f1, v1, f2, v2, f3, v3) \
+ (HW_##reg##_CLR(BM_##reg##_##f1 | \
+ BM_##reg##_##f2 | \
+ BM_##reg##_##f3), \
+ HW_##reg##_SET(BF_##reg##_##f1(v1) | \
+ BF_##reg##_##f2(v2) | \
+ BF_##reg##_##f3(v3)))
+
+#define BF_CS4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \
+ (HW_##reg##_CLR(BM_##reg##_##f1 | \
+ BM_##reg##_##f2 | \
+ BM_##reg##_##f3 | \
+ BM_##reg##_##f4), \
+ HW_##reg##_SET(BF_##reg##_##f1(v1) | \
+ BF_##reg##_##f2(v2) | \
+ BF_##reg##_##f3(v3) | \
+ BF_##reg##_##f4(v4)))
+
+#define BF_CS5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
+ (HW_##reg##_CLR(BM_##reg##_##f1 | \
+ BM_##reg##_##f2 | \
+ BM_##reg##_##f3 | \
+ BM_##reg##_##f4 | \
+ BM_##reg##_##f5), \
+ HW_##reg##_SET(BF_##reg##_##f1(v1) | \
+ BF_##reg##_##f2(v2) | \
+ BF_##reg##_##f3(v3) | \
+ BF_##reg##_##f4(v4) | \
+ BF_##reg##_##f5(v5)))
+
+#define BF_CS6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
+ (HW_##reg##_CLR(BM_##reg##_##f1 | \
+ BM_##reg##_##f2 | \
+ BM_##reg##_##f3 | \
+ BM_##reg##_##f4 | \
+ BM_##reg##_##f5 | \
+ BM_##reg##_##f6), \
+ HW_##reg##_SET(BF_##reg##_##f1(v1) | \
+ BF_##reg##_##f2(v2) | \
+ BF_##reg##_##f3(v3) | \
+ BF_##reg##_##f4(v4) | \
+ BF_##reg##_##f5(v5) | \
+ BF_##reg##_##f6(v6)))
+
+#define BF_CS7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
+ (HW_##reg##_CLR(BM_##reg##_##f1 | \
+ BM_##reg##_##f2 | \
+ BM_##reg##_##f3 | \
+ BM_##reg##_##f4 | \
+ BM_##reg##_##f5 | \
+ BM_##reg##_##f6 | \
+ BM_##reg##_##f7), \
+ HW_##reg##_SET(BF_##reg##_##f1(v1) | \
+ BF_##reg##_##f2(v2) | \
+ BF_##reg##_##f3(v3) | \
+ BF_##reg##_##f4(v4) | \
+ BF_##reg##_##f5(v5) | \
+ BF_##reg##_##f6(v6) | \
+ BF_##reg##_##f7(v7)))
+
+#define BF_CS8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
+ (HW_##reg##_CLR(BM_##reg##_##f1 | \
+ BM_##reg##_##f2 | \
+ BM_##reg##_##f3 | \
+ BM_##reg##_##f4 | \
+ BM_##reg##_##f5 | \
+ BM_##reg##_##f6 | \
+ BM_##reg##_##f7 | \
+ BM_##reg##_##f8), \
+ HW_##reg##_SET(BF_##reg##_##f1(v1) | \
+ BF_##reg##_##f2(v2) | \
+ BF_##reg##_##f3(v3) | \
+ BF_##reg##_##f4(v4) | \
+ BF_##reg##_##f5(v5) | \
+ BF_##reg##_##f6(v6) | \
+ BF_##reg##_##f7(v7) | \
+ BF_##reg##_##f8(v8)))
+
+/*
+ * Macros for multiple instance registers
+ */
+
+#define BF_SETn(reg, n, field) HW_##reg##_SET(n, BM_##reg##_##field)
+#define BF_CLRn(reg, n, field) HW_##reg##_CLR(n, BM_##reg##_##field)
+#define BF_TOGn(reg, n, field) HW_##reg##_TOG(n, BM_##reg##_##field)
+
+#define BF_SETVn(reg, n, field, v) HW_##reg##_SET(n, BF_##reg##_##field(v))
+#define BF_CLRVn(reg, n, field, v) HW_##reg##_CLR(n, BF_##reg##_##field(v))
+#define BF_TOGVn(reg, n, field, v) HW_##reg##_TOG(n, BF_##reg##_##field(v))
+
+#define BV_FLDn(reg, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
+#define BV_VALn(reg, n, field, sym) BV_##reg##_##field##__##sym
+
+#define BF_RDn(reg, n, field) HW_##reg(n).B.field
+#define BF_WRn(reg, n, field, v) BW_##reg##_##field(n, v)
+
+#define BF_CS1n(reg, n, f1, v1) \
+ (HW_##reg##_CLR(n, (BM_##reg##_##f1)), \
+ HW_##reg##_SET(n, (BF_##reg##_##f1(v1))))
+
+#define BF_CS2n(reg, n, f1, v1, f2, v2) \
+ (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
+ BM_##reg##_##f2)), \
+ HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
+ BF_##reg##_##f2(v2))))
+
+#define BF_CS3n(reg, n, f1, v1, f2, v2, f3, v3) \
+ (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
+ BM_##reg##_##f2 | \
+ BM_##reg##_##f3)), \
+ HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
+ BF_##reg##_##f2(v2) | \
+ BF_##reg##_##f3(v3))))
+
+#define BF_CS4n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4) \
+ (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
+ BM_##reg##_##f2 | \
+ BM_##reg##_##f3 | \
+ BM_##reg##_##f4)), \
+ HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
+ BF_##reg##_##f2(v2) | \
+ BF_##reg##_##f3(v3) | \
+ BF_##reg##_##f4(v4))))
+
+#define BF_CS5n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
+ (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
+ BM_##reg##_##f2 | \
+ BM_##reg##_##f3 | \
+ BM_##reg##_##f4 | \
+ BM_##reg##_##f5)), \
+ HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
+ BF_##reg##_##f2(v2) | \
+ BF_##reg##_##f3(v3) | \
+ BF_##reg##_##f4(v4) | \
+ BF_##reg##_##f5(v5))))
+
+#define BF_CS6n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
+ (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
+ BM_##reg##_##f2 | \
+ BM_##reg##_##f3 | \
+ BM_##reg##_##f4 | \
+ BM_##reg##_##f5 | \
+ BM_##reg##_##f6)), \
+ HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
+ BF_##reg##_##f2(v2) | \
+ BF_##reg##_##f3(v3) | \
+ BF_##reg##_##f4(v4) | \
+ BF_##reg##_##f5(v5) | \
+ BF_##reg##_##f6(v6))))
+
+#define BF_CS7n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
+ (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
+ BM_##reg##_##f2 | \
+ BM_##reg##_##f3 | \
+ BM_##reg##_##f4 | \
+ BM_##reg##_##f5 | \
+ BM_##reg##_##f6 | \
+ BM_##reg##_##f7)), \
+ HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
+ BF_##reg##_##f2(v2) | \
+ BF_##reg##_##f3(v3) | \
+ BF_##reg##_##f4(v4) | \
+ BF_##reg##_##f5(v5) | \
+ BF_##reg##_##f6(v6) | \
+ BF_##reg##_##f7(v7))))
+
+#define BF_CS8n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
+ (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
+ BM_##reg##_##f2 | \
+ BM_##reg##_##f3 | \
+ BM_##reg##_##f4 | \
+ BM_##reg##_##f5 | \
+ BM_##reg##_##f6 | \
+ BM_##reg##_##f7 | \
+ BM_##reg##_##f8)), \
+ HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
+ BF_##reg##_##f2(v2) | \
+ BF_##reg##_##f3(v3) | \
+ BF_##reg##_##f4(v4) | \
+ BF_##reg##_##f5(v5) | \
+ BF_##reg##_##f6(v6) | \
+ BF_##reg##_##f7(v7) | \
+ BF_##reg##_##f8(v8))))
+
+/*
+ * Macros for single instance MULTI-BLOCK registers
+ */
+
+#define BFn_SET(reg, blk, field) HW_##reg##_SET(blk, BM_##reg##_##field)
+#define BFn_CLR(reg, blk, field) HW_##reg##_CLR(blk, BM_##reg##_##field)
+#define BFn_TOG(reg, blk, field) HW_##reg##_TOG(blk, BM_##reg##_##field)
+
+#define BFn_SETV(reg, blk, field, v) HW_##reg##_SET(blk, BF_##reg##_##field(v))
+#define BFn_CLRV(reg, blk, field, v) HW_##reg##_CLR(blk, BF_##reg##_##field(v))
+#define BFn_TOGV(reg, blk, field, v) HW_##reg##_TOG(blk, BF_##reg##_##field(v))
+
+#define BVn_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
+#define BVn_VAL(reg, field, sym) BV_##reg##_##field##__##sym
+
+#define BFn_RD(reg, blk, field) HW_##reg(blk).B.field
+#define BFn_WR(reg, blk, field, v) BW_##reg##_##field(blk, v)
+
+#define BFn_CS1(reg, blk, f1, v1) \
+ (HW_##reg##_CLR(blk, BM_##reg##_##f1), \
+ HW_##reg##_SET(blk, BF_##reg##_##f1(v1)))
+
+#define BFn_CS2(reg, blk, f1, v1, f2, v2) \
+ (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
+ BM_##reg##_##f2), \
+ HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
+ BF_##reg##_##f2(v2)))
+
+#define BFn_CS3(reg, blk, f1, v1, f2, v2, f3, v3) \
+ (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
+ BM_##reg##_##f2 | \
+ BM_##reg##_##f3), \
+ HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
+ BF_##reg##_##f2(v2) | \
+ BF_##reg##_##f3(v3)))
+
+#define BFn_CS4(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4) \
+ (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
+ BM_##reg##_##f2 | \
+ BM_##reg##_##f3 | \
+ BM_##reg##_##f4), \
+ HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
+ BF_##reg##_##f2(v2) | \
+ BF_##reg##_##f3(v3) | \
+ BF_##reg##_##f4(v4)))
+
+#define BFn_CS5(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
+ (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
+ BM_##reg##_##f2 | \
+ BM_##reg##_##f3 | \
+ BM_##reg##_##f4 | \
+ BM_##reg##_##f5), \
+ HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
+ BF_##reg##_##f2(v2) | \
+ BF_##reg##_##f3(v3) | \
+ BF_##reg##_##f4(v4) | \
+ BF_##reg##_##f5(v5)))
+
+#define BFn_CS6(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
+ (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
+ BM_##reg##_##f2 | \
+ BM_##reg##_##f3 | \
+ BM_##reg##_##f4 | \
+ BM_##reg##_##f5 | \
+ BM_##reg##_##f6), \
+ HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
+ BF_##reg##_##f2(v2) | \
+ BF_##reg##_##f3(v3) | \
+ BF_##reg##_##f4(v4) | \
+ BF_##reg##_##f5(v5) | \
+ BF_##reg##_##f6(v6)))
+
+#define BFn_CS7(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
+ (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
+ BM_##reg##_##f2 | \
+ BM_##reg##_##f3 | \
+ BM_##reg##_##f4 | \
+ BM_##reg##_##f5 | \
+ BM_##reg##_##f6 | \
+ BM_##reg##_##f7), \
+ HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
+ BF_##reg##_##f2(v2) | \
+ BF_##reg##_##f3(v3) | \
+ BF_##reg##_##f4(v4) | \
+ BF_##reg##_##f5(v5) | \
+ BF_##reg##_##f6(v6) | \
+ BF_##reg##_##f7(v7)))
+
+#define BFn_CS8(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
+ (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
+ BM_##reg##_##f2 | \
+ BM_##reg##_##f3 | \
+ BM_##reg##_##f4 | \
+ BM_##reg##_##f5 | \
+ BM_##reg##_##f6 | \
+ BM_##reg##_##f7 | \
+ BM_##reg##_##f8), \
+ HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
+ BF_##reg##_##f2(v2) | \
+ BF_##reg##_##f3(v3) | \
+ BF_##reg##_##f4(v4) | \
+ BF_##reg##_##f5(v5) | \
+ BF_##reg##_##f6(v6) | \
+ BF_##reg##_##f7(v7) | \
+ BF_##reg##_##f8(v8)))
+
+/*
+ * Macros for MULTI-BLOCK multiple instance registers
+ */
+
+#define BFn_SETn(reg, blk, n, field) HW_##reg##_SET(blk, n, BM_##reg##_##field)
+#define BFn_CLRn(reg, blk, n, field) HW_##reg##_CLR(blk, n, BM_##reg##_##field)
+#define BFn_TOGn(reg, blk, n, field) HW_##reg##_TOG(blk, n, BM_##reg##_##field)
+
+#define BFn_SETVn(reg, blk, n, field, v) HW_##reg##_SET(blk, n, BF_##reg##_##field(v))
+#define BFn_CLRVn(reg, blk, n, field, v) HW_##reg##_CLR(blk, n, BF_##reg##_##field(v))
+#define BFn_TOGVn(reg, blk, n, field, v) HW_##reg##_TOG(blk, n, BF_##reg##_##field(v))
+
+#define BVn_FLDn(reg, blk, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
+#define BVn_VALn(reg, blk, n, field, sym) BV_##reg##_##field##__##sym
+
+#define BFn_RDn(reg, blk, n, field) HW_##reg(n).B.field
+#define BFn_WRn(reg, blk, n, field, v) BW_##reg##_##field(n, v)
+
+#define BFn_CS1n(reg, blk, n, f1, v1) \
+ (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1)), \
+ HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1))))
+
+#define BFn_CS2n(reg, blk, n, f1, v1, f2, v2) \
+ (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
+ BM_##reg##_##f2)), \
+ HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
+ BF_##reg##_##f2(v2))))
+
+#define BFn_CS3n(reg, blk, n, f1, v1, f2, v2, f3, v3) \
+ (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
+ BM_##reg##_##f2 | \
+ BM_##reg##_##f3)), \
+ HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
+ BF_##reg##_##f2(v2) | \
+ BF_##reg##_##f3(v3))))
+
+#define BFn_CS4n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4) \
+ (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
+ BM_##reg##_##f2 | \
+ BM_##reg##_##f3 | \
+ BM_##reg##_##f4)), \
+ HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
+ BF_##reg##_##f2(v2) | \
+ BF_##reg##_##f3(v3) | \
+ BF_##reg##_##f4(v4))))
+
+#define BFn_CS5n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
+ (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
+ BM_##reg##_##f2 | \
+ BM_##reg##_##f3 | \
+ BM_##reg##_##f4 | \
+ BM_##reg##_##f5)), \
+ HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
+ BF_##reg##_##f2(v2) | \
+ BF_##reg##_##f3(v3) | \
+ BF_##reg##_##f4(v4) | \
+ BF_##reg##_##f5(v5))))
+
+#define BFn_CS6n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
+ (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
+ BM_##reg##_##f2 | \
+ BM_##reg##_##f3 | \
+ BM_##reg##_##f4 | \
+ BM_##reg##_##f5 | \
+ BM_##reg##_##f6)), \
+ HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
+ BF_##reg##_##f2(v2) | \
+ BF_##reg##_##f3(v3) | \
+ BF_##reg##_##f4(v4) | \
+ BF_##reg##_##f5(v5) | \
+ BF_##reg##_##f6(v6))))
+
+#define BFn_CS7n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
+ (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
+ BM_##reg##_##f2 | \
+ BM_##reg##_##f3 | \
+ BM_##reg##_##f4 | \
+ BM_##reg##_##f5 | \
+ BM_##reg##_##f6 | \
+ BM_##reg##_##f7)), \
+ HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
+ BF_##reg##_##f2(v2) | \
+ BF_##reg##_##f3(v3) | \
+ BF_##reg##_##f4(v4) | \
+ BF_##reg##_##f5(v5) | \
+ BF_##reg##_##f6(v6) | \
+ BF_##reg##_##f7(v7))))
+
+#define BFn_CS8n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
+ (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
+ BM_##reg##_##f2 | \
+ BM_##reg##_##f3 | \
+ BM_##reg##_##f4 | \
+ BM_##reg##_##f5 | \
+ BM_##reg##_##f6 | \
+ BM_##reg##_##f7 | \
+ BM_##reg##_##f8)), \
+ HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
+ BF_##reg##_##f2(v2) | \
+ BF_##reg##_##f3(v3) | \
+ BF_##reg##_##f4(v4) | \
+ BF_##reg##_##f5(v5) | \
+ BF_##reg##_##f6(v6) | \
+ BF_##reg##_##f7(v7) | \
+ BF_##reg##_##f8(v8))))
+
+#endif /* _FSL_BITACCESS_H */
+
+/******************************************************************************/
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-28 19:06:40 +0000