diff options
Diffstat (limited to 'tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z')
8 files changed, 1267 insertions, 0 deletions
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/PeripheralNames.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/PeripheralNames.h new file mode 100644 index 0000000000..c2b5d96188 --- /dev/null +++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/PeripheralNames.h @@ -0,0 +1,119 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + OSC32KCLK = 0, + RTC_CLKIN = 2 +} RTCName; + +typedef enum { + UART_0 = (int)UART0_BASE, + UART_1 = (int)UART1_BASE, + UART_2 = (int)UART2_BASE +} UARTName; +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART UART_0 + +typedef enum { + I2C_0 = (int)I2C0_BASE, + I2C_1 = (int)I2C1_BASE, +} I2CName; + +#define TPM_SHIFT 8 +typedef enum { + PWM_1 = (0 << TPM_SHIFT) | (0), // TPM0 CH0 + PWM_2 = (0 << TPM_SHIFT) | (1), // TPM0 CH1 + PWM_3 = (0 << TPM_SHIFT) | (2), // TPM0 CH2 + PWM_4 = (0 << TPM_SHIFT) | (3), // TPM0 CH3 + PWM_5 = (0 << TPM_SHIFT) | (4), // TPM0 CH4 + PWM_6 = (0 << TPM_SHIFT) | (5), // TPM0 CH5 + + PWM_7 = (1 << TPM_SHIFT) | (0), // TPM1 CH0 + PWM_8 = (1 << TPM_SHIFT) | (1), // TPM1 CH1 + + PWM_9 = (2 << TPM_SHIFT) | (0), // TPM2 CH0 + PWM_10 = (2 << TPM_SHIFT) | (1) // TPM2 CH1 +} PWMName; + +#define CHANNELS_A_SHIFT 5 +typedef enum { + ADC0_SE0 = 0, + ADC0_SE3 = 3, + ADC0_SE4a = (1 << CHANNELS_A_SHIFT) | (4), + ADC0_SE4b = 4, + ADC0_SE5b = 5, + ADC0_SE6b = 6, + ADC0_SE7a = (1 << CHANNELS_A_SHIFT) | (7), + ADC0_SE7b = 7, + ADC0_SE8 = 8, + ADC0_SE9 = 9, + ADC0_SE11 = 11, + ADC0_SE12 = 12, + ADC0_SE13 = 13, + ADC0_SE14 = 14, + ADC0_SE15 = 15, + ADC0_SE23 = 23 +} ADCName; + +typedef enum { + DAC_0 = 0 +} DACName; + + +typedef enum { + SPI_0 = (int)SPI0_BASE, + SPI_1 = (int)SPI1_BASE, +} SPIName; + +// Default peripherals +#define MBED_SPI0 PTD2, PTD3, PTD1, PTD0 + +#define MBED_UART0 PTC4, PTC3 +#define MBED_UART1 PTD3, PTD2 +#define MBED_UARTUSB PTA2, PTA1 + +#define MBED_I2C0 PTC9, PTC8 +#define MBED_I2C1 PTE1, PTE0 + +#define MBED_ANALOGOUT0 PTE30 + +#define MBED_ANALOGIN0 PTC2 +#define MBED_ANALOGIN1 PTB3 +#define MBED_ANALOGIN2 PTB2 +#define MBED_ANALOGIN3 PTB1 +#define MBED_ANALOGIN4 PTB0 + +#define MBED_PWMOUT0 PTD4 +#define MBED_PWMOUT1 PTA12 +#define MBED_PWMOUT2 PTA4 +#define MBED_PWMOUT3 PTA5 +#define MBED_PWMOUT4 PTC8 +#define MBED_PWMOUT5 PTC9 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/PeripheralPins.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/PeripheralPins.c new file mode 100644 index 0000000000..ef77ff1882 --- /dev/null +++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/PeripheralPins.c @@ -0,0 +1,197 @@ + +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************RTC***************/ +const PinMap PinMap_RTC[] = { + {PTC1, RTC_CLKIN, 1}, +}; + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {PTE20, ADC0_SE0, 0}, + {PTE22, ADC0_SE3, 0}, + {PTE21, ADC0_SE4a, 0}, + {PTE29, ADC0_SE4b, 0}, + {PTE30, ADC0_SE23, 0}, + {PTE23, ADC0_SE7a, 0}, + {PTB0, ADC0_SE8, 0}, + {PTB1, ADC0_SE9, 0}, + {PTB2, ADC0_SE12, 0}, + {PTB3, ADC0_SE13, 0}, + {PTC0, ADC0_SE14, 0}, + {PTC1, ADC0_SE15, 0}, + {PTC2, ADC0_SE11, 0}, + {PTD1, ADC0_SE5b, 0}, + {PTD5, ADC0_SE6b, 0}, + {PTD6, ADC0_SE7b, 0}, + {NC, NC, 0} +}; + +/************DAC***************/ +const PinMap PinMap_DAC[] = { + {PTE30, DAC_0, 0}, + {NC , NC , 0} +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {PTE25, I2C_0, 5}, + {PTC9, I2C_0, 2}, + {PTE0, I2C_1, 6}, + {PTB1, I2C_0, 2}, + {PTB3, I2C_0, 2}, + {PTC11, I2C_1, 2}, + {PTC2, I2C_1, 2}, + {PTA4, I2C_1, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PTE24, I2C_0, 5}, + {PTC8, I2C_0, 2}, + {PTE1, I2C_1, 6}, + {PTB0, I2C_0, 2}, + {PTB2, I2C_0, 2}, + {PTC10, I2C_1, 2}, + {PTC1, I2C_1, 2}, + {NC , NC, 0} +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {PTC4, UART_1, 3}, + {PTA2, UART_0, 2}, + {PTD5, UART_2, 3}, + {PTD3, UART_2, 3}, + {PTD7, UART_0, 3}, + {PTE20, UART_0, 4}, + {PTE22, UART_2, 4}, + {PTE0, UART_1, 3}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PTC3, UART_1, 3}, + {PTA1, UART_0, 2}, + {PTD4, UART_2, 3}, + {PTD2, UART_2, 3}, + {PTD6, UART_0, 3}, + {PTE23, UART_2, 4}, + {PTE21, UART_0, 4}, + {PTE1, UART_1, 3}, + {NC , NC , 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + {PTA15, SPI_0, 2}, + {PTB11, SPI_1, 2}, + {PTC5, SPI_0, 2}, + {PTD1, SPI_0, 2}, + {PTD5, SPI_1, 2}, + {PTE2, SPI_1, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {PTA16, SPI_0, 2}, + {PTA17, SPI_0, 5}, + {PTB16, SPI_1, 2}, + {PTB17, SPI_1, 5}, + {PTC6, SPI_0, 2}, + {PTC7, SPI_0, 5}, + {PTD2, SPI_0, 2}, + {PTD3, SPI_0, 5}, + {PTD6, SPI_1, 2}, + {PTD7, SPI_1, 5}, + {PTE1, SPI_1, 2}, + {PTE3, SPI_1, 5}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PTA16, SPI_0, 5}, + {PTA17, SPI_0, 2}, + {PTB16, SPI_1, 5}, + {PTB17, SPI_1, 2}, + {PTC6, SPI_0, 5}, + {PTC7, SPI_0, 2}, + {PTD2, SPI_0, 5}, + {PTD3, SPI_0, 2}, + {PTD6, SPI_1, 5}, + {PTD7, SPI_1, 2}, + {PTE1, SPI_1, 5}, + {PTE3, SPI_1, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PTA14, SPI_0, 2}, + {PTB10, SPI_1, 2}, + {PTC4, SPI_0, 2}, + {PTD0, SPI_0, 2}, + {PTD4, SPI_1, 2}, + {PTE4, SPI_1, 2}, + {NC , NC , 0} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + {PTA0, PWM_6, 3}, // PTA0 , TPM0 CH5 + {PTA1, PWM_9 , 3}, // PTA1 , TPM2 CH0 + {PTA2, PWM_10, 3}, // PTA2 , TPM2 CH1 + {PTA3, PWM_1, 3}, // PTA3 , TPM0 CH0 + {PTA4, PWM_2 , 3}, // PTA4 , TPM0 CH1 + {PTA5, PWM_3 , 3}, // PTA5 , TPM0 CH2 + {PTA12, PWM_7 , 3}, // PTA12, TPM1 CH0 + {PTA13, PWM_8 , 3}, // PTA13, TPM1 CH1 + + {PTB0, PWM_7, 3}, // PTB0 , TPM1 CH0 + {PTB1, PWM_8, 3}, // PTB1 , TPM1 CH1 + {PTB2, PWM_9, 3}, // PTB2 , TPM2 CH0 + {PTB3, PWM_10, 3}, // PTB3 , TPM2 CH1 + {PTB18, PWM_9, 3}, // PTB18, TPM2 CH0 + {PTB19, PWM_10, 3}, // PTB18, TPM2 CH1 + + {PTC1, PWM_1, 4}, // PTC1 , TPM0 CH0 + {PTC2, PWM_2, 4}, // PTC2 , TPM0 CH1 + {PTC3, PWM_3, 4}, // PTC3 , TPM0 CH2 + {PTC4, PWM_4, 4}, // PTC4 , TPM0 CH3 + {PTC8, PWM_5 , 3}, // PTC8 , TPM0 CH4 + {PTC9, PWM_6 , 3}, // PTC9 , TPM0 CH5 + + {PTD0, PWM_1 , 4}, // PTD0 , TPM0 CH0 + {PTD1, PWM_2 , 4}, // PTD0 , TPM0 CH1 + {PTD2, PWM_3 , 4}, // PTD2 , TPM0 CH2 + {PTD3, PWM_4 , 4}, // PTD3 , TPM0 CH3 + {PTD4, PWM_5 , 4}, // PTD4 , TPM0 CH4 + {PTD5, PWM_6 , 4}, // PTD5 , TPM0 CH5 + + {PTE20, PWM_7, 3}, // PTE20, TPM1 CH0 + {PTE21, PWM_8, 3}, // PTE21, TPM1 CH1 + {PTE22, PWM_9, 3}, // PTE22, TPM2 CH0 + {PTE23, PWM_10, 3}, // PTE23, TPM2 CH1 + {PTE24, PWM_1, 3}, // PTE24, TPM0 CH0 + {PTE25, PWM_2, 3}, // PTE25, TPM0 CH1 + {PTE26, PWM_6, 3}, // PTE26, TPM0 CH5 + {PTE29, PWM_3, 3}, // PTE29, TPM0 CH2 + {PTE30, PWM_4, 3}, // PTE30, TPM0 CH3 + {PTE31, PWM_5, 3}, // PTE31, TPM0 CH4 + {NC , NC, 0} +}; diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/PinNames.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/PinNames.h new file mode 100644 index 0000000000..89ebb11aec --- /dev/null +++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/PinNames.h @@ -0,0 +1,254 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PORT_SHIFT 12 + +typedef enum { + PTA0 = 0x0, + PTA1 = 0x4, + PTA2 = 0x8, + PTA3 = 0xc, + PTA4 = 0x10, + PTA5 = 0x14, + PTA6 = 0x18, + PTA7 = 0x1c, + PTA8 = 0x20, + PTA9 = 0x24, + PTA10 = 0x28, + PTA11 = 0x2c, + PTA12 = 0x30, + PTA13 = 0x34, + PTA14 = 0x38, + PTA15 = 0x3c, + PTA16 = 0x40, + PTA17 = 0x44, + PTA18 = 0x48, + PTA19 = 0x4c, + PTA20 = 0x50, + PTA21 = 0x54, + PTA22 = 0x58, + PTA23 = 0x5c, + PTA24 = 0x60, + PTA25 = 0x64, + PTA26 = 0x68, + PTA27 = 0x6c, + PTA28 = 0x70, + PTA29 = 0x74, + PTA30 = 0x78, + PTA31 = 0x7c, + PTB0 = 0x1000, + PTB1 = 0x1004, + PTB2 = 0x1008, + PTB3 = 0x100c, + PTB4 = 0x1010, + PTB5 = 0x1014, + PTB6 = 0x1018, + PTB7 = 0x101c, + PTB8 = 0x1020, + PTB9 = 0x1024, + PTB10 = 0x1028, + PTB11 = 0x102c, + PTB12 = 0x1030, + PTB13 = 0x1034, + PTB14 = 0x1038, + PTB15 = 0x103c, + PTB16 = 0x1040, + PTB17 = 0x1044, + PTB18 = 0x1048, + PTB19 = 0x104c, + PTB20 = 0x1050, + PTB21 = 0x1054, + PTB22 = 0x1058, + PTB23 = 0x105c, + PTB24 = 0x1060, + PTB25 = 0x1064, + PTB26 = 0x1068, + PTB27 = 0x106c, + PTB28 = 0x1070, + PTB29 = 0x1074, + PTB30 = 0x1078, + PTB31 = 0x107c, + PTC0 = 0x2000, + PTC1 = 0x2004, + PTC2 = 0x2008, + PTC3 = 0x200c, + PTC4 = 0x2010, + PTC5 = 0x2014, + PTC6 = 0x2018, + PTC7 = 0x201c, + PTC8 = 0x2020, + PTC9 = 0x2024, + PTC10 = 0x2028, + PTC11 = 0x202c, + PTC12 = 0x2030, + PTC13 = 0x2034, + PTC14 = 0x2038, + PTC15 = 0x203c, + PTC16 = 0x2040, + PTC17 = 0x2044, + PTC18 = 0x2048, + PTC19 = 0x204c, + PTC20 = 0x2050, + PTC21 = 0x2054, + PTC22 = 0x2058, + PTC23 = 0x205c, + PTC24 = 0x2060, + PTC25 = 0x2064, + PTC26 = 0x2068, + PTC27 = 0x206c, + PTC28 = 0x2070, + PTC29 = 0x2074, + PTC30 = 0x2078, + PTC31 = 0x207c, + PTD0 = 0x3000, + PTD1 = 0x3004, + PTD2 = 0x3008, + PTD3 = 0x300c, + PTD4 = 0x3010, + PTD5 = 0x3014, + PTD6 = 0x3018, + PTD7 = 0x301c, + PTD8 = 0x3020, + PTD9 = 0x3024, + PTD10 = 0x3028, + PTD11 = 0x302c, + PTD12 = 0x3030, + PTD13 = 0x3034, + PTD14 = 0x3038, + PTD15 = 0x303c, + PTD16 = 0x3040, + PTD17 = 0x3044, + PTD18 = 0x3048, + PTD19 = 0x304c, + PTD20 = 0x3050, + PTD21 = 0x3054, + PTD22 = 0x3058, + PTD23 = 0x305c, + PTD24 = 0x3060, + PTD25 = 0x3064, + PTD26 = 0x3068, + PTD27 = 0x306c, + PTD28 = 0x3070, + PTD29 = 0x3074, + PTD30 = 0x3078, + PTD31 = 0x307c, + PTE0 = 0x4000, + PTE1 = 0x4004, + PTE2 = 0x4008, + PTE3 = 0x400c, + PTE4 = 0x4010, + PTE5 = 0x4014, + PTE6 = 0x4018, + PTE7 = 0x401c, + PTE8 = 0x4020, + PTE9 = 0x4024, + PTE10 = 0x4028, + PTE11 = 0x402c, + PTE12 = 0x4030, + PTE13 = 0x4034, + PTE14 = 0x4038, + PTE15 = 0x403c, + PTE16 = 0x4040, + PTE17 = 0x4044, + PTE18 = 0x4048, + PTE19 = 0x404c, + PTE20 = 0x4050, + PTE21 = 0x4054, + PTE22 = 0x4058, + PTE23 = 0x405c, + PTE24 = 0x4060, + PTE25 = 0x4064, + PTE26 = 0x4068, + PTE27 = 0x406c, + PTE28 = 0x4070, + PTE29 = 0x4074, + PTE30 = 0x4078, + PTE31 = 0x407c, + + LED_RED = PTB18, + LED_GREEN = PTB19, + LED_BLUE = PTD1, + + // mbed original LED naming + LED1 = LED_RED, + LED2 = LED_GREEN, + LED3 = LED_BLUE, + LED4 = LED_BLUE, + + // USB Pins + USBTX = PTA2, + USBRX = PTA1, + + // Arduino Headers + D0 = PTA1, + D1 = PTA2, + D2 = PTD4, + D3 = PTA12, + D4 = PTA4, + D5 = PTA5, + D6 = PTC8, + D7 = PTC9, + D8 = PTA13, + D9 = PTD5, + D10 = PTD0, + D11 = PTD2, + D12 = PTD3, + D13 = PTD1, + D14 = PTE0, + D15 = PTE1, + + A0 = PTB0, + A1 = PTB1, + A2 = PTB2, + A3 = PTB3, + A4 = PTC2, + A5 = PTC1, + + I2C_SCL = D15, + I2C_SDA = D14, + + TSI_ELEC0 = PTB16, + TSI_ELEC1 = PTB17, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +/* PullDown not available for KL25 */ +typedef enum { + PullNone = 0, + PullUp = 2, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device.h new file mode 100644 index 0000000000..ef2d8260d3 --- /dev/null +++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device.h @@ -0,0 +1,58 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 1 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 1 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 1 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 1 + +#include "objects.h" + +#endif diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/gpio_irq_api.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/gpio_irq_api.c new file mode 100644 index 0000000000..844007d7c2 --- /dev/null +++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/gpio_irq_api.c @@ -0,0 +1,170 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include <stddef.h> +#include "cmsis.h" + +#include "gpio_irq_api.h" +#include "gpio_api.h" +#include "mbed_error.h" + +#define CHANNEL_NUM 64 + +static uint32_t channel_ids[CHANNEL_NUM] = {0}; +static gpio_irq_handler irq_handler; + +#define IRQ_DISABLED (0) +#define IRQ_RAISING_EDGE PORT_PCR_IRQC(9) +#define IRQ_FALLING_EDGE PORT_PCR_IRQC(10) +#define IRQ_EITHER_EDGE PORT_PCR_IRQC(11) + +const uint32_t search_bits[] = {0x0000FFFF, 0x000000FF, 0x0000000F, 0x00000003, 0x00000001}; + +static void handle_interrupt_in(PORT_Type *port, int ch_base) { + uint32_t isfr; + uint8_t location; + + while((isfr = port->ISFR) != 0) { + location = 0; + for (int i = 0; i < 5; i++) { + if (!(isfr & (search_bits[i] << location))) + location += 1 << (4 - i); + } + + uint32_t id = channel_ids[ch_base + location]; + if (id == 0) { + continue; + } + + FGPIO_Type *gpio; + gpio_irq_event event = IRQ_NONE; + switch (port->PCR[location] & PORT_PCR_IRQC_MASK) { + case IRQ_RAISING_EDGE: + event = IRQ_RISE; + break; + + case IRQ_FALLING_EDGE: + event = IRQ_FALL; + break; + + case IRQ_EITHER_EDGE: + gpio = (port == PORTA) ? (FPTA) : (FPTD); + event = (gpio->PDIR & (1 << location)) ? (IRQ_RISE) : (IRQ_FALL); + break; + } + if (event != IRQ_NONE) { + irq_handler(id, event); + } + port->ISFR = 1 << location; + } +} + +void gpio_irqA(void) {handle_interrupt_in(PORTA, 0);} +void gpio_irqD(void) {handle_interrupt_in(PORTD, 32);} + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { + if (pin == NC) return -1; + + irq_handler = handler; + + obj->port = pin >> PORT_SHIFT; + obj->pin = (pin & 0x7F) >> 2; + + uint32_t ch_base, vector; + IRQn_Type irq_n; + switch (obj->port) { + case PortA: + ch_base = 0; irq_n = PORTA_IRQn; vector = (uint32_t)gpio_irqA; + break; + + case PortD: + ch_base = 32; irq_n = PORTD_IRQn; vector = (uint32_t)gpio_irqD; + break; + + default: + error("gpio_irq only supported on port A and D"); + break; + } + NVIC_SetVector(irq_n, vector); + NVIC_EnableIRQ(irq_n); + + obj->ch = ch_base + obj->pin; + channel_ids[obj->ch] = id; + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) { + channel_ids[obj->ch] = 0; +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { + PORT_Type *port = (PORT_Type *)(PORTA_BASE + 0x1000 * obj->port); + + uint32_t irq_settings = IRQ_DISABLED; + + switch (port->PCR[obj->pin] & PORT_PCR_IRQC_MASK) { + case IRQ_DISABLED: + if (enable) { + irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_FALLING_EDGE); + } + break; + + case IRQ_RAISING_EDGE: + if (enable) { + irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_EITHER_EDGE); + } else { + if (event == IRQ_FALL) + irq_settings = IRQ_RAISING_EDGE; + } + break; + + case IRQ_FALLING_EDGE: + if (enable) { + irq_settings = (event == IRQ_FALL) ? (IRQ_FALLING_EDGE) : (IRQ_EITHER_EDGE); + } else { + if (event == IRQ_RISE) + irq_settings = IRQ_FALLING_EDGE; + } + break; + + case IRQ_EITHER_EDGE: + if (enable) { + irq_settings = IRQ_EITHER_EDGE; + } else { + irq_settings = (event == IRQ_RISE) ? (IRQ_FALLING_EDGE) : (IRQ_RAISING_EDGE); + } + break; + } + + // Interrupt configuration and clear interrupt + port->PCR[obj->pin] = (port->PCR[obj->pin] & ~PORT_PCR_IRQC_MASK) | irq_settings | PORT_PCR_ISF_MASK; +} + +void gpio_irq_enable(gpio_irq_t *obj) { + if (obj->port == PortA) { + NVIC_EnableIRQ(PORTA_IRQn); + } else if (obj->port == PortD) { + NVIC_EnableIRQ(PORTD_IRQn); + } +} + +void gpio_irq_disable(gpio_irq_t *obj) { + if (obj->port == PortA) { + NVIC_DisableIRQ(PORTA_IRQn); + } else if (obj->port == PortD) { + NVIC_DisableIRQ(PORTD_IRQn); + } +} diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/mbed_overrides.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/mbed_overrides.c new file mode 100644 index 0000000000..b590bb0ebc --- /dev/null +++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/mbed_overrides.c @@ -0,0 +1,32 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_api.h" + +// called before main - implement here if board needs it ortherwise, let +// the application override this if necessary +//void mbed_sdk_init() +//{ +// +//} + +// Change the NMI pin to an input. This allows NMI pin to +// be used as a low power mode wakeup. The application will +// need to change the pin back to NMI_b or wakeup only occurs once! +void NMI_Handler(void) +{ + gpio_t gpio; + gpio_init_in(&gpio, PTA4); +} diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/serial_api.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/serial_api.c new file mode 100644 index 0000000000..6c3b01815a --- /dev/null +++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/serial_api.c @@ -0,0 +1,295 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "serial_api.h" + +// math.h required for floating point operations for baud rate calculation +#include <math.h> + +#include <string.h> + +#include "cmsis.h" +#include "pinmap.h" +#include "clk_freqs.h" +#include "PeripheralPins.h" + +//Devices either user UART0 or UARTLP +#ifndef UARTLP_BASES + #define UARTLP_C2_RE_MASK UART0_C2_RE_MASK + #define UARTLP_C2_TE_MASK UART0_C2_TE_MASK + #define UARTLP_BDH_SBNS_MASK UART0_BDH_SBNS_MASK + #define UARTLP_BDH_SBNS_SHIFT UART0_BDH_SBNS_SHIFT + #define UARTLP_S1_TDRE_MASK UART0_S1_TDRE_MASK + #define UARTLP_S1_OR_MASK UART0_S1_OR_MASK + #define UARTLP_C2_RIE_MASK UART0_C2_RIE_MASK + #define UARTLP_C2_TIE_MASK UART0_C2_TIE_MASK + #define UARTLP_C2_SBK_MASK UART0_C2_SBK_MASK + #define UARTLP_S1_RDRF_MASK UART0_S1_RDRF_MASK +#endif + +#ifdef UART2 + #define UART_NUM 3 +#else + #define UART_NUM 1 +#endif + +/****************************************************************************** + * INITIALIZATION + ******************************************************************************/ + +static uint32_t serial_irq_ids[UART_NUM] = {0}; +static uart_irq_handler irq_handler; + +int stdio_uart_inited = 0; +serial_t stdio_uart; + +void serial_init(serial_t *obj, PinName tx, PinName rx) { + // determine the UART to use + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); + UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT((int)uart != NC); + + obj->uart = (UARTLP_Type *)uart; + // enable clk + switch (uart) { + case UART_0: if (mcgpllfll_frequency() != 0) //PLL/FLL is selected + SIM->SOPT2 |= (1<<SIM_SOPT2_UART0SRC_SHIFT); + else + SIM->SOPT2 |= (2<<SIM_SOPT2_UART0SRC_SHIFT); + SIM->SCGC4 |= SIM_SCGC4_UART0_MASK; break; + #if UART_NUM > 1 + case UART_1: SIM->SCGC4 |= SIM_SCGC4_UART1_MASK; break; + case UART_2: SIM->SCGC4 |= SIM_SCGC4_UART2_MASK; break; + #endif + } + // Disable UART before changing registers + obj->uart->C2 &= ~(UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK); + + switch (uart) { + case UART_0: obj->index = 0; break; + #if UART_NUM > 1 + case UART_1: obj->index = 1; break; + case UART_2: obj->index = 2; break; + #endif + } + + // set default baud rate and format + serial_baud (obj, 9600); + serial_format(obj, 8, ParityNone, 1); + + // pinout the chosen uart + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + // set rx/tx pins in PullUp mode + if (tx != NC) { + pin_mode(tx, PullUp); + } + if (rx != NC) { + pin_mode(rx, PullUp); + } + + obj->uart->C2 |= (UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK); + + if (uart == STDIO_UART) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +void serial_free(serial_t *obj) { + serial_irq_ids[obj->index] = 0; +} + +// serial_baud +// +// set the baud rate, taking in to account the current SystemFrequency +void serial_baud(serial_t *obj, int baudrate) { + + // save C2 state + uint8_t c2_state = (obj->uart->C2 & (UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK)); + + // Disable UART before changing registers + obj->uart->C2 &= ~(UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK); + + uint32_t PCLK; + if (obj->uart == UART0) { + if (mcgpllfll_frequency() != 0) + PCLK = mcgpllfll_frequency(); + else + PCLK = extosc_frequency(); + } else + PCLK = bus_frequency(); + + // First we check to see if the basic divide with no DivAddVal/MulVal + // ratio gives us an integer result. If it does, we set DivAddVal = 0, + // MulVal = 1. Otherwise, we search the valid ratio value range to find + // the closest match. This could be more elegant, using search methods + // and/or lookup tables, but the brute force method is not that much + // slower, and is more maintainable. + uint16_t DL = PCLK / (16 * baudrate); + + // set BDH and BDL + obj->uart->BDH = (obj->uart->BDH & ~(0x1f)) | ((DL >> 8) & 0x1f); + obj->uart->BDL = (obj->uart->BDL & ~(0xff)) | ((DL >> 0) & 0xff); + + // restore C2 state + obj->uart->C2 |= c2_state; +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { + MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); + MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven)); + MBED_ASSERT(data_bits == 8); // TODO: Support other number of data bits (also in the write method!) + + // save C2 state + uint8_t c2_state = (obj->uart->C2 & (UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK)); + + // Disable UART before changing registers + obj->uart->C2 &= ~(UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK); + + + uint8_t parity_enable, parity_select; + switch (parity) { + case ParityNone: parity_enable = 0; parity_select = 0; break; + case ParityOdd : parity_enable = 1; parity_select = 1; data_bits++; break; + case ParityEven: parity_enable = 1; parity_select = 0; data_bits++; break; + default: + break; + } + + stop_bits -= 1; + + // data bits, parity and parity mode + obj->uart->C1 = ((parity_enable << 1) + | (parity_select << 0)); + + // stop bits + obj->uart->BDH &= ~UARTLP_BDH_SBNS_MASK; + obj->uart->BDH |= (stop_bits << UARTLP_BDH_SBNS_SHIFT); + + // restore C2 state + obj->uart->C2 |= c2_state; +} + +/****************************************************************************** + * INTERRUPTS HANDLING + ******************************************************************************/ +static inline void uart_irq(uint8_t status, uint32_t index) { + if (serial_irq_ids[index] != 0) { + if (status & UARTLP_S1_TDRE_MASK) + irq_handler(serial_irq_ids[index], TxIrq); + + if (status & UARTLP_S1_RDRF_MASK) + irq_handler(serial_irq_ids[index], RxIrq); + } +} + +void uart0_irq() { + uart_irq(UART0->S1, 0); + if (UART0->S1 & UARTLP_S1_OR_MASK) + UART0->S1 |= UARTLP_S1_OR_MASK; +} +#if UART_NUM > 1 +void uart1_irq() {uart_irq(UART1->S1, 1);} +void uart2_irq() {uart_irq(UART2->S1, 2);} +#endif + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { + irq_handler = handler; + serial_irq_ids[obj->index] = id; +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { + IRQn_Type irq_n = (IRQn_Type)0; + uint32_t vector = 0; + switch ((int)obj->uart) { + case UART_0: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break; + #if UART_NUM > 1 + case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break; + case UART_2: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break; + #endif + } + + if (enable) { + switch (irq) { + case RxIrq: obj->uart->C2 |= (UARTLP_C2_RIE_MASK); break; + case TxIrq: obj->uart->C2 |= (UARTLP_C2_TIE_MASK); break; + } + NVIC_SetVector(irq_n, vector); + NVIC_EnableIRQ(irq_n); + + } else { // disable + int all_disabled = 0; + SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); + switch (irq) { + case RxIrq: obj->uart->C2 &= ~(UARTLP_C2_RIE_MASK); break; + case TxIrq: obj->uart->C2 &= ~(UARTLP_C2_TIE_MASK); break; + } + switch (other_irq) { + case RxIrq: all_disabled = (obj->uart->C2 & (UARTLP_C2_RIE_MASK)) == 0; break; + case TxIrq: all_disabled = (obj->uart->C2 & (UARTLP_C2_TIE_MASK)) == 0; break; + } + if (all_disabled) + NVIC_DisableIRQ(irq_n); + } +} + +/****************************************************************************** + * READ/WRITE + ******************************************************************************/ +int serial_getc(serial_t *obj) { + while (!serial_readable(obj)); + return obj->uart->D; +} + +void serial_putc(serial_t *obj, int c) { + while (!serial_writable(obj)); + obj->uart->D = c; +} + +int serial_readable(serial_t *obj) { + // check overrun + if (obj->uart->S1 & UARTLP_S1_OR_MASK) { + obj->uart->S1 |= UARTLP_S1_OR_MASK; + } + return (obj->uart->S1 & UARTLP_S1_RDRF_MASK); +} + +int serial_writable(serial_t *obj) { + // check overrun + if (obj->uart->S1 & UARTLP_S1_OR_MASK) { + obj->uart->S1 |= UARTLP_S1_OR_MASK; + } + return (obj->uart->S1 & UARTLP_S1_TDRE_MASK); +} + +void serial_clear(serial_t *obj) { +} + +void serial_pinout_tx(PinName tx) { + pinmap_pinout(tx, PinMap_UART_TX); +} + +void serial_break_set(serial_t *obj) { + obj->uart->C2 |= UARTLP_C2_SBK_MASK; +} + +void serial_break_clear(serial_t *obj) { + obj->uart->C2 &= ~UARTLP_C2_SBK_MASK; +} + diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/spi_api.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/spi_api.c new file mode 100644 index 0000000000..e9f13ecbf1 --- /dev/null +++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/spi_api.c @@ -0,0 +1,142 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "spi_api.h" + +#include <math.h> + +#include "cmsis.h" +#include "pinmap.h" +#include "clk_freqs.h" +#include "PeripheralPins.h" + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { + // determine the SPI to use + SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); + SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); + SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); + SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); + SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); + SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); + + obj->spi = (SPI_Type*)pinmap_merge(spi_data, spi_cntl); + MBED_ASSERT((int)obj->spi != NC); + + // enable power and clocking + switch ((int)obj->spi) { + case SPI_0: SIM->SCGC5 |= 1 << 11; SIM->SCGC4 |= 1 << 22; break; + case SPI_1: SIM->SCGC5 |= 1 << 13; SIM->SCGC4 |= 1 << 23; break; + } + + // set default format and frequency + if (ssel == NC) { + spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master + } else { + spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave + } + spi_frequency(obj, 1000000); + + // enable SPI + obj->spi->C1 |= SPI_C1_SPE_MASK; + + // pin out the spi pins + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + if (ssel != NC) { + pinmap_pinout(ssel, PinMap_SPI_SSEL); + } +} + +void spi_free(spi_t *obj) { + // [TODO] +} +void spi_format(spi_t *obj, int bits, int mode, int slave) { + MBED_ASSERT(bits == 8); + MBED_ASSERT((mode >= 0) && (mode <= 3)); + + uint8_t polarity = (mode & 0x2) ? 1 : 0; + uint8_t phase = (mode & 0x1) ? 1 : 0; + uint8_t c1_data = ((!slave) << 4) | (polarity << 3) | (phase << 2); + + // clear MSTR, CPOL and CPHA bits + obj->spi->C1 &= ~(0x7 << 2); + + // write new value + obj->spi->C1 |= c1_data; +} + +void spi_frequency(spi_t *obj, int hz) { + uint32_t error = 0; + uint32_t p_error = 0xffffffff; + uint32_t ref = 0; + uint8_t spr = 0; + uint8_t ref_spr = 0; + uint8_t ref_prescaler = 0; + + // bus clk + uint32_t PCLK = bus_frequency(); + uint8_t prescaler = 1; + uint8_t divisor = 2; + + for (prescaler = 1; prescaler <= 8; prescaler++) { + divisor = 2; + for (spr = 0; spr <= 8; spr++, divisor *= 2) { + ref = PCLK / (prescaler*divisor); + if (ref > (uint32_t)hz) + continue; + error = hz - ref; + if (error < p_error) { + ref_spr = spr; + ref_prescaler = prescaler - 1; + p_error = error; + } + } + } + + // set SPPR and SPR + obj->spi->BR = ((ref_prescaler & 0x7) << 4) | (ref_spr & 0xf); +} + +static inline int spi_writeable(spi_t * obj) { + return (obj->spi->S & SPI_S_SPTEF_MASK) ? 1 : 0; +} + +static inline int spi_readable(spi_t * obj) { + return (obj->spi->S & SPI_S_SPRF_MASK) ? 1 : 0; +} + +int spi_master_write(spi_t *obj, int value) { + // wait tx buffer empty + while(!spi_writeable(obj)); + obj->spi->D = (value & 0xff); + + // wait rx buffer full + while (!spi_readable(obj)); + return obj->spi->D & 0xff; +} + +int spi_slave_receive(spi_t *obj) { + return spi_readable(obj); +} + +int spi_slave_read(spi_t *obj) { + return obj->spi->D; +} + +void spi_slave_write(spi_t *obj, int value) { + while (!spi_writeable(obj)); + obj->spi->D = value; +} |