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Diffstat (limited to 'tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB')
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/TOOLCHAIN_GCC_ARM/STM32F100.ld156
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/TOOLCHAIN_GCC_ARM/startup_stm32f100xb.s423
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis.h38
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis_nvic.c55
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis_nvic.h54
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/hal_tick.c145
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/hal_tick.h60
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/stm32f100xb.h4073
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/stm32f1xx.h238
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.c603
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.h116
11 files changed, 5961 insertions, 0 deletions
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/TOOLCHAIN_GCC_ARM/STM32F100.ld b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/TOOLCHAIN_GCC_ARM/STM32F100.ld
new file mode 100644
index 0000000000..cc4103d434
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/TOOLCHAIN_GCC_ARM/STM32F100.ld
@@ -0,0 +1,156 @@
+/* Linker script for STM32F407 */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128k
+ RAM (rwx) : ORIGIN = 0x200001D0, LENGTH = 8K - 0x1D0
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/TOOLCHAIN_GCC_ARM/startup_stm32f100xb.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/TOOLCHAIN_GCC_ARM/startup_stm32f100xb.s
new file mode 100644
index 0000000000..c1bf0b23a6
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/TOOLCHAIN_GCC_ARM/startup_stm32f100xb.s
@@ -0,0 +1,423 @@
+/**
+ *************** (C) COPYRIGHT 2014 STMicroelectronics ************************
+ * @file startup_stm32f100xb.s
+ * @author MCD Application Team
+ * @version V4.0.0
+ * @date 16-December-2014
+ * @brief STM32F100xB Devices vector table for Atollic toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF108F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+/* bl __libc_init_array */
+/* Call the application's entry point.*/
+/* bl main */
+ bl _start
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_IRQHandler
+ .word RTC_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_TIM15_IRQHandler
+ .word TIM1_UP_TIM16_IRQHandler
+ .word TIM1_TRG_COM_TIM17_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTC_Alarm_IRQHandler
+ .word CEC_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word TIM6_DAC_IRQHandler
+ .word TIM7_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x01CC. This is for boot in RAM mode for
+ STM32F10xB Value Line devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM15_IRQHandler
+ .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM16_IRQHandler
+ .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM17_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis.h
new file mode 100644
index 0000000000..8bd1a4d1c5
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis.h
@@ -0,0 +1,38 @@
+/* mbed Microcontroller Library
+ * A generic CMSIS include header
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "stm32f1xx.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis_nvic.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis_nvic.c
new file mode 100644
index 0000000000..2da63fc9af
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis_nvic.c
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis_nvic.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis_nvic.h
new file mode 100644
index 0000000000..1410b207e1
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis_nvic.h
@@ -0,0 +1,54 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// CORE: 16 vectors (= 64 bytes from 0x00 to 0x3F)
+// MCU Peripherals: 100 vectors (= 400 bytes from 0x40 to 0x1CC)
+// Total: 464 bytes to be reserved in RAM (see scatter file)
+#define NVIC_NUM_VECTORS (16 + 100)
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/hal_tick.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/hal_tick.c
new file mode 100644
index 0000000000..9e42da7a4e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/hal_tick.c
@@ -0,0 +1,145 @@
+/**
+ ******************************************************************************
+ * @file hal_tick.c
+ * @author MCD Application Team
+ * @brief Initialization of HAL tick
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#include "hal_tick.h"
+
+TIM_HandleTypeDef TimMasterHandle;
+uint32_t PreviousVal = 0;
+
+void us_ticker_irq_handler(void);
+void set_compare(uint16_t count);
+
+extern volatile uint32_t SlaveCounter;
+extern volatile uint32_t oc_int_part;
+extern volatile uint16_t oc_rem_part;
+
+void timer_irq_handler(void) {
+ uint16_t cval = TIM_MST->CNT;
+
+ TimMasterHandle.Instance = TIM_MST;
+
+ // Clear Update interrupt flag
+ if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_UPDATE) == SET) {
+ __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_UPDATE);
+ SlaveCounter++;
+ }
+
+ // Channel 1 for mbed timeout
+ if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) {
+ __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1);
+ if (oc_rem_part > 0) {
+ set_compare(oc_rem_part); // Finish the remaining time left
+ oc_rem_part = 0;
+ } else {
+ if (oc_int_part > 0) {
+ set_compare(0xFFFF);
+ oc_rem_part = cval; // To finish the counter loop the next time
+ oc_int_part--;
+ } else {
+ us_ticker_irq_handler();
+ }
+ }
+ }
+
+ // Channel 2 for HAL tick
+ if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC2) == SET) {
+ __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC2);
+ uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle);
+ if ((val - PreviousVal) >= HAL_TICK_DELAY) {
+ // Increment HAL variable
+ HAL_IncTick();
+ // Prepare next interrupt
+ __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY);
+ PreviousVal = val;
+ }
+ }
+}
+
+// Reconfigure the HAL tick using a standard timer instead of systick.
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
+ // Enable timer clock
+ TIM_MST_RCC;
+
+ // Reset timer
+ TIM_MST_RESET_ON;
+ TIM_MST_RESET_OFF;
+
+ // Update the SystemCoreClock variable
+ SystemCoreClockUpdate();
+
+ // Configure time base
+ TimMasterHandle.Instance = TIM_MST;
+ TimMasterHandle.Init.Period = 0xFFFFFFFF;
+ TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 us tick
+ TimMasterHandle.Init.ClockDivision = 0;
+ TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
+ HAL_TIM_Base_Init(&TimMasterHandle);
+
+ // Configure output compare channel 1 for mbed timeout (enabled later when used)
+ HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
+
+ // Configure output compare channel 2 for HAL tick
+ HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
+ PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle);
+ __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
+
+ // Configure interrupts
+ // Update interrupt used for 32-bit counter
+ // Output compare channel 1 interrupt for mbed timeout
+ // Output compare channel 2 interrupt for HAL tick
+ NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
+ NVIC_EnableIRQ(TIM_MST_IRQ);
+
+ // Enable interrupts
+ __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_UPDATE); // For 32-bit counter
+ __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); // For HAL tick
+
+ // Enable timer
+ HAL_TIM_Base_Start(&TimMasterHandle);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/hal_tick.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/hal_tick.h
new file mode 100644
index 0000000000..09c66b92ce
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/hal_tick.h
@@ -0,0 +1,60 @@
+/**
+ ******************************************************************************
+ * @file hal_tick.h
+ * @author MCD Application Team
+ * @brief Initialization of HAL tick
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HAL_TICK_H
+#define __HAL_TICK_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f1xx.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST TIM4
+#define TIM_MST_IRQ TIM4_IRQn
+#define TIM_MST_RCC __TIM4_CLK_ENABLE()
+
+#define TIM_MST_RESET_ON __TIM4_FORCE_RESET()
+#define TIM_MST_RESET_OFF __TIM4_RELEASE_RESET()
+
+#define HAL_TICK_DELAY (1000) // 1 ms
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __HAL_TICK_H
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/stm32f100xb.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/stm32f100xb.h
new file mode 100644
index 0000000000..41a76df4dd
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/stm32f100xb.h
@@ -0,0 +1,4073 @@
+/**
+ ******************************************************************************
+ * @file stm32f100xb.h
+ * @author MCD Application Team
+ * @version V4.0.0
+ * @date 16-December-2014
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for STM32F1xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f100xb
+ * @{
+ */
+
+#ifndef __STM32F100xB_H
+#define __STM32F100xB_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+ #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
+#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
+#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F10x Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+ /*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** STM32 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_IRQn = 2, /*!< Tamper Interrupt */
+ RTC_IRQn = 3, /*!< RTC global Interrupt */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+} IRQn_Type;
+
+
+/**
+ * @}
+ */
+
+#include "core_cm3.h"
+#include "system_stm32f1xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR;
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SMPR1;
+ __IO uint32_t SMPR2;
+ __IO uint32_t JOFR1;
+ __IO uint32_t JOFR2;
+ __IO uint32_t JOFR3;
+ __IO uint32_t JOFR4;
+ __IO uint32_t HTR;
+ __IO uint32_t LTR;
+ __IO uint32_t SQR1;
+ __IO uint32_t SQR2;
+ __IO uint32_t SQR3;
+ __IO uint32_t JSQR;
+ __IO uint32_t JDR1;
+ __IO uint32_t JDR2;
+ __IO uint32_t JDR3;
+ __IO uint32_t JDR4;
+ __IO uint32_t DR;
+} ADC_TypeDef;
+
+/**
+ * @brief Backup Registers
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0;
+ __IO uint32_t DR1;
+ __IO uint32_t DR2;
+ __IO uint32_t DR3;
+ __IO uint32_t DR4;
+ __IO uint32_t DR5;
+ __IO uint32_t DR6;
+ __IO uint32_t DR7;
+ __IO uint32_t DR8;
+ __IO uint32_t DR9;
+ __IO uint32_t DR10;
+ __IO uint32_t RTCCR;
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} BKP_TypeDef;
+
+
+/**
+ * @brief Consumer Electronics Control (CEC)
+ */
+typedef struct
+{
+ __IO uint32_t CFGR;
+ __IO uint32_t OAR;
+ __IO uint32_t PRES;
+ __IO uint32_t ESR;
+ __IO uint32_t CSR;
+ __IO uint32_t TXD;
+ __IO uint32_t RXD;
+} CEC_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t SWTRIGR;
+ __IO uint32_t DHR12R1;
+ __IO uint32_t DHR12L1;
+ __IO uint32_t DHR8R1;
+ __IO uint32_t DHR12R2;
+ __IO uint32_t DHR12L2;
+ __IO uint32_t DHR8R2;
+ __IO uint32_t DHR12RD;
+ __IO uint32_t DHR12LD;
+ __IO uint32_t DHR8RD;
+ __IO uint32_t DOR1;
+ __IO uint32_t DOR2;
+ __IO uint32_t SR;
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE;
+ __IO uint32_t CR;
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR;
+ __IO uint32_t CNDTR;
+ __IO uint32_t CPAR;
+ __IO uint32_t CMAR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR;
+ __IO uint32_t IFCR;
+} DMA_TypeDef;
+
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR;
+ __IO uint32_t EMR;
+ __IO uint32_t RTSR;
+ __IO uint32_t FTSR;
+ __IO uint32_t SWIER;
+ __IO uint32_t PR;
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR;
+ __IO uint32_t KEYR;
+ __IO uint32_t OPTKEYR;
+ __IO uint32_t SR;
+ __IO uint32_t CR;
+ __IO uint32_t AR;
+ __IO uint32_t RESERVED;
+ __IO uint32_t OBR;
+ __IO uint32_t WRPR;
+} FLASH_TypeDef;
+
+/**
+ * @brief Option Bytes Registers
+ */
+
+typedef struct
+{
+ __IO uint16_t RDP;
+ __IO uint16_t USER;
+ __IO uint16_t Data0;
+ __IO uint16_t Data1;
+ __IO uint16_t WRP0;
+ __IO uint16_t WRP1;
+ __IO uint16_t WRP2;
+ __IO uint16_t WRP3;
+} OB_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t CRL;
+ __IO uint32_t CRH;
+ __IO uint32_t IDR;
+ __IO uint32_t ODR;
+ __IO uint32_t BSRR;
+ __IO uint32_t BRR;
+ __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/**
+ * @brief Alternate Function I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t EVCR;
+ __IO uint32_t MAPR;
+ __IO uint32_t EXTICR[4];
+ uint32_t RESERVED0;
+ __IO uint32_t MAPR2;
+} AFIO_TypeDef;
+/**
+ * @brief Inter Integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t OAR1;
+ __IO uint32_t OAR2;
+ __IO uint32_t DR;
+ __IO uint32_t SR1;
+ __IO uint32_t SR2;
+ __IO uint32_t CCR;
+ __IO uint32_t TRISE;
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CFGR;
+ __IO uint32_t CIR;
+ __IO uint32_t APB2RSTR;
+ __IO uint32_t APB1RSTR;
+ __IO uint32_t AHBENR;
+ __IO uint32_t APB2ENR;
+ __IO uint32_t APB1ENR;
+ __IO uint32_t BDCR;
+ __IO uint32_t CSR;
+
+
+ uint32_t RESERVED0;
+ __IO uint32_t CFGR2;
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t CRH;
+ __IO uint32_t CRL;
+ __IO uint32_t PRLH;
+ __IO uint32_t PRLL;
+ __IO uint32_t DIVH;
+ __IO uint32_t DIVL;
+ __IO uint32_t CNTH;
+ __IO uint32_t CNTL;
+ __IO uint32_t ALRH;
+ __IO uint32_t ALRL;
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER;
+ __IO uint32_t CLKCR;
+ __IO uint32_t ARG;
+ __IO uint32_t CMD;
+ __I uint32_t RESPCMD;
+ __I uint32_t RESP1;
+ __I uint32_t RESP2;
+ __I uint32_t RESP3;
+ __I uint32_t RESP4;
+ __IO uint32_t DTIMER;
+ __IO uint32_t DLEN;
+ __IO uint32_t DCTRL;
+ __I uint32_t DCOUNT;
+ __I uint32_t STA;
+ __IO uint32_t ICR;
+ __IO uint32_t MASK;
+ uint32_t RESERVED0[2];
+ __I uint32_t FIFOCNT;
+ uint32_t RESERVED1[13];
+ __IO uint32_t FIFO;
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SR;
+ __IO uint32_t DR;
+ __IO uint32_t CRCPR;
+ __IO uint32_t RXCRCR;
+ __IO uint32_t TXCRCR;
+} SPI_TypeDef;
+
+/**
+ * @brief TIM Timers
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+}TIM_TypeDef;
+
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+#define CEC_BASE (APB1PERIPH_BASE + 0x7800)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+#define TIM15_BASE (APB2PERIPH_BASE + 0x4000)
+#define TIM16_BASE (APB2PERIPH_BASE + 0x4400)
+#define TIM17_BASE (APB2PERIPH_BASE + 0x4800)
+
+#define SDIO_BASE (PERIPH_BASE + 0x18000)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
+#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+
+
+
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define BKP ((BKP_TypeDef *) BKP_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define CEC ((CEC_TypeDef *) CEC_BASE)
+#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
+#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
+#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
+#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
+#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
+#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
+#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
+#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
+#define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
+
+/******************************************************************************/
+/* */
+/* Backup registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for BKP_DR1 register ********************/
+#define BKP_DR1_D ((uint32_t)0x0000FFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR2 register ********************/
+#define BKP_DR2_D ((uint32_t)0x0000FFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR3 register ********************/
+#define BKP_DR3_D ((uint32_t)0x0000FFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR4 register ********************/
+#define BKP_DR4_D ((uint32_t)0x0000FFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR5 register ********************/
+#define BKP_DR5_D ((uint32_t)0x0000FFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR6 register ********************/
+#define BKP_DR6_D ((uint32_t)0x0000FFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR7 register ********************/
+#define BKP_DR7_D ((uint32_t)0x0000FFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR8 register ********************/
+#define BKP_DR8_D ((uint32_t)0x0000FFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR9 register ********************/
+#define BKP_DR9_D ((uint32_t)0x0000FFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR10 register *******************/
+#define BKP_DR10_D ((uint32_t)0x0000FFFF) /*!< Backup data */
+
+#define RTC_BKP_NUMBER 10
+
+/****************** Bit definition for BKP_RTCCR register *******************/
+#define BKP_RTCCR_CAL ((uint32_t)0x0000007F) /*!< Calibration value */
+#define BKP_RTCCR_CCO ((uint32_t)0x00000080) /*!< Calibration Clock Output */
+#define BKP_RTCCR_ASOE ((uint32_t)0x00000100) /*!< Alarm or Second Output Enable */
+#define BKP_RTCCR_ASOS ((uint32_t)0x00000200) /*!< Alarm or Second Output Selection */
+
+/******************** Bit definition for BKP_CR register ********************/
+#define BKP_CR_TPE ((uint32_t)0x00000001) /*!< TAMPER pin enable */
+#define BKP_CR_TPAL ((uint32_t)0x00000002) /*!< TAMPER pin active level */
+
+/******************* Bit definition for BKP_CSR register ********************/
+#define BKP_CSR_CTE ((uint32_t)0x00000001) /*!< Clear Tamper event */
+#define BKP_CSR_CTI ((uint32_t)0x00000002) /*!< Clear Tamper Interrupt */
+#define BKP_CSR_TPIE ((uint32_t)0x00000004) /*!< TAMPER Pin interrupt enable */
+#define BKP_CSR_TEF ((uint32_t)0x00000100) /*!< Tamper Event Flag */
+#define BKP_CSR_TIF ((uint32_t)0x00000200) /*!< Tamper Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
+#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
+#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
+
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */
+#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+
+#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+
+#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+
+ #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
+ #define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+ #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+ #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
+ #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
+ #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
+ #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
+ #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
+ #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
+ #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
+ #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
+ #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
+ #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
+ #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
+ #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
+ #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
+ #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
+
+/*!< MCO configuration */
+ #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+ #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+ #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+ #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+ #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+ #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+ #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+ #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+ #define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+
+/*!<****************** Bit definition for RCC_CIR register ********************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
+
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */
+#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */
+#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */
+#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */
+#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */
+#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */
+
+
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
+
+#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */
+#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */
+#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */
+
+#define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */
+
+
+
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
+
+
+#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
+
+#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
+#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
+
+
+
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
+#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
+#define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */
+
+
+
+#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
+
+/****************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
+#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
+
+
+
+
+/****************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */
+#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */
+#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */
+#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */
+#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */
+#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */
+
+
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
+
+#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */
+#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */
+#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */
+
+#define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */
+
+
+
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
+
+
+#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
+
+#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */
+#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
+
+
+
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
+#define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */
+
+
+
+#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
+
+/******************* Bit definition for RCC_BDCR register *******************/
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< RTC congiguration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CSR register ********************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
+
+
+/******************* Bit definition for RCC_CFGR2 register ******************/
+/*!< PREDIV1 configuration */
+ #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */
+ #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+ #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+ #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+ #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+ #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
+ #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */
+ #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */
+ #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */
+ #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */
+ #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */
+ #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */
+ #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */
+ #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */
+ #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */
+ #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */
+ #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */
+ #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */
+ #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */
+ #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */
+ #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */
+
+/******************************************************************************/
+/* */
+/* General Purpose and Alternate Function I/O */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for GPIO_CRL register *******************/
+#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
+
+#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
+
+#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */
+#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */
+
+/******************* Bit definition for GPIO_CRH register *******************/
+#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
+
+#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
+
+#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */
+#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */
+
+/*!<****************** Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR0 ((uint32_t)0x0001) /*!< Port input data, bit 0 */
+#define GPIO_IDR_IDR1 ((uint32_t)0x0002) /*!< Port input data, bit 1 */
+#define GPIO_IDR_IDR2 ((uint32_t)0x0004) /*!< Port input data, bit 2 */
+#define GPIO_IDR_IDR3 ((uint32_t)0x0008) /*!< Port input data, bit 3 */
+#define GPIO_IDR_IDR4 ((uint32_t)0x0010) /*!< Port input data, bit 4 */
+#define GPIO_IDR_IDR5 ((uint32_t)0x0020) /*!< Port input data, bit 5 */
+#define GPIO_IDR_IDR6 ((uint32_t)0x0040) /*!< Port input data, bit 6 */
+#define GPIO_IDR_IDR7 ((uint32_t)0x0080) /*!< Port input data, bit 7 */
+#define GPIO_IDR_IDR8 ((uint32_t)0x0100) /*!< Port input data, bit 8 */
+#define GPIO_IDR_IDR9 ((uint32_t)0x0200) /*!< Port input data, bit 9 */
+#define GPIO_IDR_IDR10 ((uint32_t)0x0400) /*!< Port input data, bit 10 */
+#define GPIO_IDR_IDR11 ((uint32_t)0x0800) /*!< Port input data, bit 11 */
+#define GPIO_IDR_IDR12 ((uint32_t)0x1000) /*!< Port input data, bit 12 */
+#define GPIO_IDR_IDR13 ((uint32_t)0x2000) /*!< Port input data, bit 13 */
+#define GPIO_IDR_IDR14 ((uint32_t)0x4000) /*!< Port input data, bit 14 */
+#define GPIO_IDR_IDR15 ((uint32_t)0x8000) /*!< Port input data, bit 15 */
+
+/******************* Bit definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR0 ((uint32_t)0x0001) /*!< Port output data, bit 0 */
+#define GPIO_ODR_ODR1 ((uint32_t)0x0002) /*!< Port output data, bit 1 */
+#define GPIO_ODR_ODR2 ((uint32_t)0x0004) /*!< Port output data, bit 2 */
+#define GPIO_ODR_ODR3 ((uint32_t)0x0008) /*!< Port output data, bit 3 */
+#define GPIO_ODR_ODR4 ((uint32_t)0x0010) /*!< Port output data, bit 4 */
+#define GPIO_ODR_ODR5 ((uint32_t)0x0020) /*!< Port output data, bit 5 */
+#define GPIO_ODR_ODR6 ((uint32_t)0x0040) /*!< Port output data, bit 6 */
+#define GPIO_ODR_ODR7 ((uint32_t)0x0080) /*!< Port output data, bit 7 */
+#define GPIO_ODR_ODR8 ((uint32_t)0x0100) /*!< Port output data, bit 8 */
+#define GPIO_ODR_ODR9 ((uint32_t)0x0200) /*!< Port output data, bit 9 */
+#define GPIO_ODR_ODR10 ((uint32_t)0x0400) /*!< Port output data, bit 10 */
+#define GPIO_ODR_ODR11 ((uint32_t)0x0800) /*!< Port output data, bit 11 */
+#define GPIO_ODR_ODR12 ((uint32_t)0x1000) /*!< Port output data, bit 12 */
+#define GPIO_ODR_ODR13 ((uint32_t)0x2000) /*!< Port output data, bit 13 */
+#define GPIO_ODR_ODR14 ((uint32_t)0x4000) /*!< Port output data, bit 14 */
+#define GPIO_ODR_ODR15 ((uint32_t)0x8000) /*!< Port output data, bit 15 */
+
+/****************** Bit definition for GPIO_BSRR register *******************/
+#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */
+#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */
+#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */
+#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */
+#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */
+#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */
+#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */
+#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */
+#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */
+#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */
+#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */
+#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */
+#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */
+#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */
+#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */
+#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */
+
+#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */
+#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */
+#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */
+#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */
+#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */
+#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */
+#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */
+#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */
+#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */
+#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */
+#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */
+#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */
+#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */
+#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */
+#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */
+#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */
+
+/******************* Bit definition for GPIO_BRR register *******************/
+#define GPIO_BRR_BR0 ((uint32_t)0x0001) /*!< Port x Reset bit 0 */
+#define GPIO_BRR_BR1 ((uint32_t)0x0002) /*!< Port x Reset bit 1 */
+#define GPIO_BRR_BR2 ((uint32_t)0x0004) /*!< Port x Reset bit 2 */
+#define GPIO_BRR_BR3 ((uint32_t)0x0008) /*!< Port x Reset bit 3 */
+#define GPIO_BRR_BR4 ((uint32_t)0x0010) /*!< Port x Reset bit 4 */
+#define GPIO_BRR_BR5 ((uint32_t)0x0020) /*!< Port x Reset bit 5 */
+#define GPIO_BRR_BR6 ((uint32_t)0x0040) /*!< Port x Reset bit 6 */
+#define GPIO_BRR_BR7 ((uint32_t)0x0080) /*!< Port x Reset bit 7 */
+#define GPIO_BRR_BR8 ((uint32_t)0x0100) /*!< Port x Reset bit 8 */
+#define GPIO_BRR_BR9 ((uint32_t)0x0200) /*!< Port x Reset bit 9 */
+#define GPIO_BRR_BR10 ((uint32_t)0x0400) /*!< Port x Reset bit 10 */
+#define GPIO_BRR_BR11 ((uint32_t)0x0800) /*!< Port x Reset bit 11 */
+#define GPIO_BRR_BR12 ((uint32_t)0x1000) /*!< Port x Reset bit 12 */
+#define GPIO_BRR_BR13 ((uint32_t)0x2000) /*!< Port x Reset bit 13 */
+#define GPIO_BRR_BR14 ((uint32_t)0x4000) /*!< Port x Reset bit 14 */
+#define GPIO_BRR_BR15 ((uint32_t)0x8000) /*!< Port x Reset bit 15 */
+
+/****************** Bit definition for GPIO_LCKR register *******************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for AFIO_EVCR register *******************/
+#define AFIO_EVCR_PIN ((uint32_t)0x0000000F) /*!< PIN[3:0] bits (Pin selection) */
+#define AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+/*!< PIN configuration */
+#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) /*!< Pin 1 selected */
+#define AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) /*!< Pin 2 selected */
+#define AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) /*!< Pin 3 selected */
+#define AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) /*!< Pin 4 selected */
+#define AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) /*!< Pin 5 selected */
+#define AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) /*!< Pin 6 selected */
+#define AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) /*!< Pin 7 selected */
+#define AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) /*!< Pin 8 selected */
+#define AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) /*!< Pin 9 selected */
+#define AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) /*!< Pin 10 selected */
+#define AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) /*!< Pin 11 selected */
+#define AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) /*!< Pin 12 selected */
+#define AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) /*!< Pin 13 selected */
+#define AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) /*!< Pin 14 selected */
+#define AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) /*!< Pin 15 selected */
+
+#define AFIO_EVCR_PORT ((uint32_t)0x00000070) /*!< PORT[2:0] bits (Port selection) */
+#define AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+
+/*!< PORT configuration */
+#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) /*!< Port B selected */
+#define AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) /*!< Port C selected */
+#define AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) /*!< Port D selected */
+#define AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) /*!< Port E selected */
+
+#define AFIO_EVCR_EVOE ((uint32_t)0x00000080) /*!< Event Output Enable */
+
+/****************** Bit definition for AFIO_MAPR register *******************/
+#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */
+#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */
+#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */
+#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */
+
+#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
+#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+/* USART3_REMAP configuration */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+
+#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+/*!< TIM1_REMAP configuration */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< TIM2_REMAP configuration */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+/*!< TIM3_REMAP configuration */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */
+
+
+#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+
+/*!< SWJ_CFG configuration */
+#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */
+
+
+/***************** Bit definition for AFIO_EXTICR1 register *****************/
+#define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
+#define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
+#define AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!< PG[0] pin */
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
+#define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
+#define AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!< PG[1] pin */
+
+/*!< EXTI2 configuration */
+#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
+#define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
+#define AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!< PG[2] pin */
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
+#define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */
+#define AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!< PG[3] pin */
+
+/***************** Bit definition for AFIO_EXTICR2 register *****************/
+#define AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
+#define AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
+#define AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!< PG[4] pin */
+
+/* EXTI5 configuration */
+#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
+#define AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
+#define AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!< PG[5] pin */
+
+/*!< EXTI6 configuration */
+#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
+#define AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
+#define AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!< PG[6] pin */
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
+#define AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
+#define AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!< PG[7] pin */
+
+/***************** Bit definition for AFIO_EXTICR3 register *****************/
+#define AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
+#define AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!< PF[8] pin */
+#define AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!< PG[8] pin */
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
+#define AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
+#define AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!< PG[9] pin */
+
+/*!< EXTI10 configuration */
+#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PE[10] pin */
+#define AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
+#define AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!< PG[10] pin */
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
+#define AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!< PF[11] pin */
+#define AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!< PG[11] pin */
+
+/***************** Bit definition for AFIO_EXTICR4 register *****************/
+#define AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
+
+/* EXTI12 configuration */
+#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
+#define AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!< PF[12] pin */
+#define AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!< PG[12] pin */
+
+/* EXTI13 configuration */
+#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
+#define AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!< PF[13] pin */
+#define AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!< PG[13] pin */
+
+/*!< EXTI14 configuration */
+#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
+#define AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!< PF[14] pin */
+#define AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!< PG[14] pin */
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
+#define AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!< PF[15] pin */
+#define AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!< PG[15] pin */
+
+/****************** Bit definition for AFIO_MAPR2 register ******************/
+#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */
+#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */
+#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */
+#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */
+#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */
+
+#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */
+
+
+/******************************************************************************/
+/* */
+/* SystemTick */
+/* */
+/******************************************************************************/
+
+/***************** Bit definition for SysTick_CTRL register *****************/
+#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
+#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
+
+/***************** Bit definition for SysTick_LOAD register *****************/
+#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/***************** Bit definition for SysTick_VAL register ******************/
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
+
+/***************** Bit definition for SysTick_CALIB register ****************/
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
+#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/* */
+/* Nested Vectored Interrupt Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for NVIC_ISER register *******************/
+#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
+#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ICER register *******************/
+#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
+#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ISPR register *******************/
+#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
+#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ICPR register *******************/
+#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
+#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_IABR register *******************/
+#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
+#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_PRI0 register *******************/
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
+
+/****************** Bit definition for NVIC_PRI1 register *******************/
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
+
+/****************** Bit definition for NVIC_PRI2 register *******************/
+#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
+#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
+
+/****************** Bit definition for NVIC_PRI3 register *******************/
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
+
+/****************** Bit definition for NVIC_PRI4 register *******************/
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
+
+/****************** Bit definition for NVIC_PRI5 register *******************/
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
+
+/****************** Bit definition for NVIC_PRI6 register *******************/
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
+
+/****************** Bit definition for NVIC_PRI7 register *******************/
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
+
+/****************** Bit definition for SCB_CPUID register *******************/
+#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
+#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
+#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
+#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
+
+/******************* Bit definition for SCB_ICSR register *******************/
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
+#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
+#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
+#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
+#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
+#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
+#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
+
+/******************* Bit definition for SCB_VTOR register *******************/
+#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
+
+/*!<***************** Bit definition for SCB_AIRCR register *******************/
+#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
+#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
+
+#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+/* prority group configuration */
+#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
+#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/******************* Bit definition for SCB_SCR register ********************/
+#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
+#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
+#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
+
+/******************** Bit definition for SCB_CCR register *******************/
+#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
+#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
+#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
+#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/******************* Bit definition for SCB_SHPR register ********************/
+#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/****************** Bit definition for SCB_SHCSR register *******************/
+#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
+#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
+#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
+#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
+#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
+#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
+#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
+#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
+#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
+#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
+#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
+
+/******************* Bit definition for SCB_CFSR register *******************/
+/*!< MFSR */
+#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */
+#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */
+#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
+#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */
+#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/******************* Bit definition for SCB_HFSR register *******************/
+#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
+#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
+
+/******************* Bit definition for SCB_DFSR register *******************/
+#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
+#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
+#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
+#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
+#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
+
+/******************* Bit definition for SCB_MMFAR register ******************/
+#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */
+
+/******************* Bit definition for SCB_BFAR register *******************/
+#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */
+
+/******************* Bit definition for SCB_afsr register *******************/
+#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register *******************/
+#define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
+#define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
+#define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
+#define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
+#define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level) */
+#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register ******************/
+#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register *******************/
+#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register *******************/
+#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */
+#define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */
+#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */
+#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */
+#define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */
+#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */
+#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */
+#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */
+#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */
+
+#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+
+#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
+
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */
+#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */
+#define ADC_CR2_CAL ((uint32_t)0x00000004) /*!< A/D Calibration */
+#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!< Reset Calibration */
+#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */
+#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */
+
+#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!< JEXTSEL[2:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */
+
+#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+
+#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */
+#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */
+#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */
+#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */
+#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */
+#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */
+#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */
+#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */
+#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */
+#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
+#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
+
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
+
+ #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun interrupt enable */
+ #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun interrupt enable */
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!< DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!< DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!< DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!< DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* CEC */
+/* */
+/******************************************************************************/
+/******************** Bit definition for CEC_CFGR register ******************/
+#define CEC_CFGR_PE ((uint32_t)0x00000001) /*!< Peripheral Enable */
+#define CEC_CFGR_IE ((uint32_t)0x00000002) /*!< Interrupt Enable */
+#define CEC_CFGR_BTEM ((uint32_t)0x00000004) /*!< Bit Timing Error Mode */
+#define CEC_CFGR_BPEM ((uint32_t)0x00000008) /*!< Bit Period Error Mode */
+
+/******************** Bit definition for CEC_OAR register ******************/
+#define CEC_OAR_OA ((uint32_t)0x0000000F) /*!< OA[3:0]: Own Address */
+#define CEC_OAR_OA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define CEC_OAR_OA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define CEC_OAR_OA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define CEC_OAR_OA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+/******************** Bit definition for CEC_PRES register ******************/
+#define CEC_PRES_PRES ((uint32_t)0x00003FFF) /*!< Prescaler Counter Value */
+
+/******************** Bit definition for CEC_ESR register ******************/
+#define CEC_ESR_BTE ((uint32_t)0x00000001) /*!< Bit Timing Error */
+#define CEC_ESR_BPE ((uint32_t)0x00000002) /*!< Bit Period Error */
+#define CEC_ESR_RBTFE ((uint32_t)0x00000004) /*!< Rx Block Transfer Finished Error */
+#define CEC_ESR_SBE ((uint32_t)0x00000008) /*!< Start Bit Error */
+#define CEC_ESR_ACKE ((uint32_t)0x00000010) /*!< Block Acknowledge Error */
+#define CEC_ESR_LINE ((uint32_t)0x00000020) /*!< Line Error */
+#define CEC_ESR_TBTFE ((uint32_t)0x00000040) /*!< Tx Block Transfer Finished Error */
+
+/******************** Bit definition for CEC_CSR register ******************/
+#define CEC_CSR_TSOM ((uint32_t)0x00000001) /*!< Tx Start Of Message */
+#define CEC_CSR_TEOM ((uint32_t)0x00000002) /*!< Tx End Of Message */
+#define CEC_CSR_TERR ((uint32_t)0x00000004) /*!< Tx Error */
+#define CEC_CSR_TBTRF ((uint32_t)0x00000008) /*!< Tx Byte Transfer Request or Block Transfer Finished */
+#define CEC_CSR_RSOM ((uint32_t)0x00000010) /*!< Rx Start Of Message */
+#define CEC_CSR_REOM ((uint32_t)0x00000020) /*!< Rx End Of Message */
+#define CEC_CSR_RERR ((uint32_t)0x00000040) /*!< Rx Error */
+#define CEC_CSR_RBTF ((uint32_t)0x00000080) /*!< Rx Block Transfer Finished */
+
+/******************** Bit definition for CEC_TXD register ******************/
+#define CEC_TXD_TXD ((uint32_t)0x000000FF) /*!< Tx Data register */
+
+/******************** Bit definition for CEC_RXD register ******************/
+#define CEC_RXD_RXD ((uint32_t)0x000000FF) /*!< Rx Data register */
+
+/*****************************************************************************/
+/* */
+/* Timers (TIM) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for TIM_CR1 register *******************/
+#define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
+#define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
+#define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register *******************/
+#define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
+#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register ******************/
+#define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+
+#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register ******************/
+#define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
+#define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
+#define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
+#define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register *******************/
+#define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
+#define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register *******************/
+#define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
+#define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register ******************/
+#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register ******************/
+#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register ******************/
+#define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register *******************/
+#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register *******************/
+#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register *******************/
+#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register *******************/
+#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register ******************/
+#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register ******************/
+#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register ******************/
+#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register ******************/
+#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register ******************/
+#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
+#define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
+#define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
+#define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register *******************/
+#define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register ******************/
+#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register ********************/
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for RTC_CRH register ********************/
+#define RTC_CRH_SECIE ((uint32_t)0x00000001) /*!< Second Interrupt Enable */
+#define RTC_CRH_ALRIE ((uint32_t)0x00000002) /*!< Alarm Interrupt Enable */
+#define RTC_CRH_OWIE ((uint32_t)0x00000004) /*!< OverfloW Interrupt Enable */
+
+/******************* Bit definition for RTC_CRL register ********************/
+#define RTC_CRL_SECF ((uint32_t)0x00000001) /*!< Second Flag */
+#define RTC_CRL_ALRF ((uint32_t)0x00000002) /*!< Alarm Flag */
+#define RTC_CRL_OWF ((uint32_t)0x00000004) /*!< OverfloW Flag */
+#define RTC_CRL_RSF ((uint32_t)0x00000008) /*!< Registers Synchronized Flag */
+#define RTC_CRL_CNF ((uint32_t)0x00000010) /*!< Configuration Flag */
+#define RTC_CRL_RTOFF ((uint32_t)0x00000020) /*!< RTC operation OFF */
+
+/******************* Bit definition for RTC_PRLH register *******************/
+#define RTC_PRLH_PRL ((uint32_t)0x0000000F) /*!< RTC Prescaler Reload Value High */
+
+/******************* Bit definition for RTC_PRLL register *******************/
+#define RTC_PRLL_PRL ((uint32_t)0x0000FFFF) /*!< RTC Prescaler Reload Value Low */
+
+/******************* Bit definition for RTC_DIVH register *******************/
+#define RTC_DIVH_RTC_DIV ((uint32_t)0x0000000F) /*!< RTC Clock Divider High */
+
+/******************* Bit definition for RTC_DIVL register *******************/
+#define RTC_DIVL_RTC_DIV ((uint32_t)0x0000FFFF) /*!< RTC Clock Divider Low */
+
+/******************* Bit definition for RTC_CNTH register *******************/
+#define RTC_CNTH_RTC_CNT ((uint32_t)0x0000FFFF) /*!< RTC Counter High */
+
+/******************* Bit definition for RTC_CNTL register *******************/
+#define RTC_CNTL_RTC_CNT ((uint32_t)0x0000FFFF) /*!< RTC Counter Low */
+
+/******************* Bit definition for RTC_ALRH register *******************/
+#define RTC_ALRH_RTC_ALR ((uint32_t)0x0000FFFF) /*!< RTC Alarm High */
+
+/******************* Bit definition for RTC_ALRL register *******************/
+#define RTC_ALRL_RTC_ALR ((uint32_t)0x0000FFFF) /*!< RTC Alarm Low */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR ((uint32_t)0x00000007) /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint32_t)0x0000007F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define WWDG_CR_T1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define WWDG_CR_T2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define WWDG_CR_T3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define WWDG_CR_T4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define WWDG_CR_T5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define WWDG_CR_T6 ((uint32_t)0x00000040) /*!< Bit 6 */
+
+#define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint32_t)0x0000007F) /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define WWDG_CFR_W1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define WWDG_CFR_W2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define WWDG_CFR_W3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define WWDG_CFR_W4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define WWDG_CFR_W5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define WWDG_CFR_W6 ((uint32_t)0x00000040) /*!< Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /*!< Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /*!< Bit 1 */
+
+#define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!< Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!< PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!< Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!< Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!< Clock divide factor */
+#define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!< Clock enable bit */
+#define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!< Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!< Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!< Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!< Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!< SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!< HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!< Command Index */
+
+#define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!< CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!< Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!< SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!< Enable CMD completion */
+#define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!< Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!< CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!< Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!< Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!< Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!< Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!< Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!< DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!< DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!< Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!< Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!< Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!< Bit 3 */
+
+#define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!< Read wait start */
+#define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!< Read wait stop */
+#define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!< Read wait mode */
+#define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!< SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!< Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!< Command response timeout */
+#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!< Data timeout */
+#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!< Received FIFO overrun error */
+#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */
+#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!< Command transfer in progress */
+#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!< Data transmit in progress */
+#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!< Data receive in progress */
+#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */
+#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */
+#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */
+#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */
+#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!< SDIO interrupt received */
+#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!< DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!< CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!< DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!< TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!< RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!< DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!< STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!< DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!< SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!< CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */
+
+
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
+#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
+#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
+
+#define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
+#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
+#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
+#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
+#define SPI_CR1_DFF ((uint32_t)0x00000800) /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
+#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
+#define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
+#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
+#define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
+#define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
+#define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!< Tx CRC Register */
+
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral Enable */
+#define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!< SMBus Mode */
+#define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!< SMBus Type */
+#define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!< ARP Enable */
+#define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!< PEC Enable */
+#define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!< General Call Enable */
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START ((uint32_t)0x00000100) /*!< Start Generation */
+#define I2C_CR1_STOP ((uint32_t)0x00000200) /*!< Stop Generation */
+#define I2C_CR1_ACK ((uint32_t)0x00000400) /*!< Acknowledge Enable */
+#define I2C_CR1_POS ((uint32_t)0x00000800) /*!< Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC ((uint32_t)0x00001000) /*!< Packet Error Checking */
+#define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!< SMBus Alert */
+#define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!< Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+
+#define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!< Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!< Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!< Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!< DMA Requests Enable */
+#define I2C_CR2_LAST ((uint32_t)0x00001000) /*!< DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+
+#define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!< Bit 9 */
+
+#define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!< Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!< Dual addressing mode enable */
+#define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!< Interface address */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB ((uint32_t)0x00000001) /*!< Start Bit (Master mode) */
+#define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF ((uint32_t)0x00000004) /*!< Byte Transfer Finished */
+#define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!< 10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!< Stop detection (Slave mode) */
+#define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!< Data Register not Empty (receivers) */
+#define I2C_SR1_TXE ((uint32_t)0x00000080) /*!< Data Register Empty (transmitters) */
+#define I2C_SR1_BERR ((uint32_t)0x00000100) /*!< Bus Error */
+#define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!< Arbitration Lost (master mode) */
+#define I2C_SR1_AF ((uint32_t)0x00000400) /*!< Acknowledge Failure */
+#define I2C_SR1_OVR ((uint32_t)0x00000800) /*!< Overrun/Underrun */
+#define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!< PEC Error in reception */
+#define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!< Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!< SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL ((uint32_t)0x00000001) /*!< Master/Slave */
+#define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!< Bus Busy */
+#define I2C_SR2_TRA ((uint32_t)0x00000004) /*!< Transmitter/Receiver */
+#define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!< General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!< SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!< SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!< Dual Flag (Slave mode) */
+#define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!< Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!< Fast Mode Duty Cycle */
+#define I2C_CCR_FS ((uint32_t)0x00008000) /*!< I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE ((uint32_t)0x00000001) /*!< Parity Error */
+#define USART_SR_FE ((uint32_t)0x00000002) /*!< Framing Error */
+#define USART_SR_NE ((uint32_t)0x00000004) /*!< Noise Error Flag */
+#define USART_SR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
+#define USART_SR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
+#define USART_SR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
+#define USART_SR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
+#define USART_SR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
+#define USART_SR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
+#define USART_SR_CTS ((uint32_t)0x00000200) /*!< CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR ((uint32_t)0x000001FF) /*!< Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK ((uint32_t)0x00000001) /*!< Send Break */
+#define USART_CR1_RWU ((uint32_t)0x00000002) /*!< Receiver wakeup */
+#define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
+#define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< PE Interrupt Enable */
+#define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
+#define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
+#define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
+#define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Wakeup method */
+#define USART_CR1_M ((uint32_t)0x00001000) /*!< Word length */
+#define USART_CR1_UE ((uint32_t)0x00002000) /*!< USART Enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD ((uint32_t)0x0000000F) /*!< Address of the USART node */
+#define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
+#define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
+#define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
+
+#define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
+#define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
+#define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
+#define USART_CR3_NACK ((uint32_t)0x00000010) /*!< Smartcard NACK enable */
+#define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< Smartcard mode enable */
+#define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
+#define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
+#define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define USART_GTPR_PSC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define USART_GTPR_PSC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define USART_GTPR_PSC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define USART_GTPR_PSC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define USART_GTPR_PSC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define USART_GTPR_PSC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define USART_GTPR_PSC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< Guard time value */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
+#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
+#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
+#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
+#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
+#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */
+
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!< Debug TIM15 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!< Debug TIM16 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!< Debug TIM17 stopped when Core is halted */
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_HLFCYA ((uint32_t)0x00000008) /*!< Flash Half Cycle Access Enable */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
+
+#define RDP_KEY ((uint32_t)0x000000A5) /*!< RDP Key */
+#define FLASH_KEY1 ((uint32_t)0x45670123) /*!< FPEC Key1 */
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< FPEC Key2 */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
+
+#define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
+#define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
+
+/****************** Bit definition for FLASH_SR register ********************/
+#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
+#define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
+#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
+#define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
+#define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
+#define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
+#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
+#define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
+#define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
+#define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
+#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT ((uint32_t)0x00000002) /*!< Read protection */
+
+#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000004) /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000008) /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000010) /*!< nRST_STDBY */
+#define FLASH_OBR_USER ((uint32_t)0x0000001C) /*!< User Option Bytes */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for FLASH_RDP register *******************/
+#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
+#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
+
+/****************** Bit definition for FLASH_USER register ******************/
+#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
+#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
+
+/****************** Bit definition for FLASH_Data0 register *****************/
+#define FLASH_DATA0_DATA0 ((uint32_t)0x000000FF) /*!< User data storage option byte */
+#define FLASH_DATA0_nDATA0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_Data1 register *****************/
+#define FLASH_DATA1_DATA1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */
+#define FLASH_DATA1_nDATA1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_WRP0 register ******************/
+#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP1 register ******************/
+#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP2 register ******************/
+#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP3 register ******************/
+#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+
+
+/**
+ * @}
+*/
+
+/**
+ * @}
+*/
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
+
+#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/****************************** CEC Instances *********************************/
+#define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/****************************** DAC Instances *********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/****************************** DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE))
+
+/**************************** GPIO Alternate Function Instances ***************/
+#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2))
+
+/****************************** START TIM Instances ***************************/
+/****************************** TIM Instances *********************************/
+#define IS_TIM_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ ((CHANNEL) == TIM_CHANNEL_1)))
+
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/****************************** END TIM Instances *****************************/
+
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/***************** UART Instances : Multi-Processor mode **********************/
+#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/***************** UART Instances : DMA mode available **********************/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/**************************** WWDG Instances *****************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+
+
+
+
+/**
+ * @}
+*/
+/******************************************************************************/
+/* For a painless codes migration between the STM32F1xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F1 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_2_IRQn ADC1_IRQn
+
+
+
+#define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn
+#define TIM9_IRQn TIM1_BRK_TIM15_IRQn
+#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
+
+#define TIM1_UP_TIM10_IRQn TIM1_UP_TIM16_IRQn
+#define TIM10_IRQn TIM1_UP_TIM16_IRQn
+#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn
+
+#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
+
+
+
+#define OTG_FS_WKUP_IRQn CEC_IRQn
+#define USBWakeUp_IRQn CEC_IRQn
+
+
+
+#define TIM6_IRQn TIM6_DAC_IRQn
+
+
+/* Aliases for __IRQHandler */
+#define ADC1_2_IRQHandler ADC1_IRQHandler
+
+
+
+#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
+#define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
+#define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler
+
+#define TIM1_UP_TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
+#define TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
+#define TIM1_UP_IRQHandler TIM1_UP_TIM16_IRQHandler
+
+#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+
+
+
+#define OTG_FS_WKUP_IRQHandler CEC_IRQHandler
+#define USBWakeUp_IRQHandler CEC_IRQHandler
+
+
+
+#define TIM6_IRQHandler TIM6_DAC_IRQHandler
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+ }
+#endif /* __cplusplus */
+
+#endif /* __STM32F100xB_H */
+
+
+
+ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/stm32f1xx.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/stm32f1xx.h
new file mode 100644
index 0000000000..7609aa728e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/stm32f1xx.h
@@ -0,0 +1,238 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx.h
+ * @author MCD Application Team
+ * @version V4.0.0
+ * @date 16-December-2014
+ * @brief CMSIS STM32F1xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F1xx device used in the target application
+ * - To use or not the peripheral’s drivers in application code(i.e.
+ * code will be based on direct access to peripheral’s registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f1xx
+ * @{
+ */
+
+#ifndef __STM32F1XX_H
+#define __STM32F1XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F1)
+#define STM32F1
+#endif /* STM32F1 */
+
+/* Uncomment the line below according to the target STM32L device used in your
+ application
+ */
+
+#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \
+ !defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \
+ !defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC)
+#define STM32F100xB /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */
+ /* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */
+ /* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */
+ /* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */
+ /* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */
+ /* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */
+ /* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */
+ /* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */
+ /* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */
+ /* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */
+ /* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */
+ /* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */
+ /* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */
+ /* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+#define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS Device version number V4.0.0
+ */
+#define __STM32F1xx_CMSIS_DEVICE_VERSION_MAIN (0x04) /*!< [31:24] main version */
+#define __STM32F1xx_CMSIS_DEVICE_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
+#define __STM32F1xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F1xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F1xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
+ |(__CMSIS_DEVICE_HAL_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F100xB)
+ #include "stm32f100xb.h"
+#elif defined(STM32F100xE)
+ #include "stm32f100xe.h"
+#elif defined(STM32F101x6)
+ #include "stm32f101x6.h"
+#elif defined(STM32F101xB)
+ #include "stm32f101xb.h"
+#elif defined(STM32F101xE)
+ #include "stm32f101xe.h"
+#elif defined(STM32F101xG)
+ #include "stm32f101xg.h"
+#elif defined(STM32F102x6)
+ #include "stm32f102x6.h"
+#elif defined(STM32F102xB)
+ #include "stm32f102xb.h"
+#elif defined(STM32F103x6)
+ #include "stm32f103x6.h"
+#elif defined(STM32F103xB)
+ #include "stm32f103xb.h"
+#elif defined(STM32F103xE)
+ #include "stm32f103xe.h"
+#elif defined(STM32F103xG)
+ #include "stm32f103xg.h"
+#elif defined(STM32F105xC)
+ #include "stm32f105xc.h"
+#elif defined(STM32F107xC)
+ #include "stm32f107xc.h"
+#else
+ #error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f1xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F1xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.c
new file mode 100644
index 0000000000..abbe81c0f0
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.c
@@ -0,0 +1,603 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f1xx.c
+ * @author MCD Application Team
+ * @version V4.0.0
+ * @date 16-December-2014
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+ *
+ * 1. This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+ * factors, AHB/APBx prescalers and Flash settings).
+ * This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f1xx_xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
+ * the product used), refer to "HSE_VALUE".
+ * When HSE is used as system clock source, directly or through PLL, and you
+ * are using different crystal you have to adapt the HSE value to your own
+ * configuration.
+ *
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
+ * | (external 8 MHz clock) | (internal 8 MHz)
+ * | 2- PLL_HSE_XTAL |
+ * | (external 8 MHz xtal) |
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 24 | 24
+ *-----------------------------------------------------------------------------
+ * AHBCLK (MHz) | 24 | 24
+ *-----------------------------------------------------------------------------
+ * APB1CLK (MHz) | 24 | 24
+ *-----------------------------------------------------------------------------
+ * APB2CLK (MHz) | 24 | 24
+ *-----------------------------------------------------------------------------
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f1xx_system
+ * @{
+ */
+
+/** @addtogroup STM32F1xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32f1xx.h"
+#include "hal_tick.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F1xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F1xx_System_Private_Defines
+ * @{
+ */
+
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
+ This value can be provided and adapted by the user application. */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
+ This value can be provided and adapted by the user application. */
+#endif /* HSI_VALUE */
+
+/*!< Uncomment the following line if you need to use external SRAM */
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+/* #define DATA_IN_ExtSRAM */
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F1xx_System_Private_Macros
+ * @{
+ */
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (0) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F1xx_System_Private_Variables
+ * @{
+ */
+
+/*******************************************************************************
+* Clock Definitions
+*******************************************************************************/
+#if defined(STM32F100xB) ||defined(STM32F100xE)
+ uint32_t SystemCoreClock = 24000000; /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+ uint32_t SystemCoreClock = 72000000; /*!< System Clock Frequency (Core Clock) */
+#endif
+
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+#ifdef DATA_IN_ExtSRAM
+ static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F1xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the Embedded Flash Interface, the PLL and update the
+ * SystemCoreClock variable.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+void SystemInit (void)
+{
+ /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#if !defined(STM32F105xC) && !defined(STM32F107xC)
+ RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+ RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F105xC */
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ /* Reset PLL2ON and PLL3ON bits */
+ RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x00FF0000;
+
+ /* Reset CFGR2 register */
+ RCC->CFGR2 = 0x00000000;
+#elif defined(STM32F100xB) || defined(STM32F100xE)
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x009F0000;
+
+ /* Reset CFGR2 register */
+ RCC->CFGR2 = 0x00000000;
+#else
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x009F0000;
+#endif /* STM32F105xC */
+
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+ #ifdef DATA_IN_ExtSRAM
+ SystemInit_ExtMemCtl();
+ #endif /* DATA_IN_ExtSRAM */
+#endif
+
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+
+ /* Configure the Cube driver */
+ SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
+ HAL_Init();
+
+ /* Configure the System clock source, PLL Multiplier and Divider factors,
+ AHB/APBx prescalers and Flash settings */
+ SetSysClock();
+
+ /* Reset the timer to avoid issues after the RAM initialization */
+ TIM_MST_RESET_ON;
+ TIM_MST_RESET_OFF;
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+ * 8 MHz or 25 MHz, depending on the product used), user has to ensure
+ * that HSE_VALUE is same as the real frequency of the crystal used.
+ * Otherwise, this function may have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F105xC */
+
+#if defined(STM32F100xB) || defined(STM32F100xE)
+ uint32_t prediv1factor = 0;
+#endif /* STM32F100xB or STM32F100xE */
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x08: /* PLL used as system clock */
+
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+
+#if !defined(STM32F105xC) && !defined(STM32F107xC)
+ pllmull = ( pllmull >> 18) + 2;
+
+ if (pllsource == 0x00)
+ {
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ #if defined(STM32F100xB) || defined(STM32F100xE)
+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
+ #else
+ /* HSE selected as PLL clock entry */
+ if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+ {/* HSE oscillator clock divided by 2 */
+ SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ SystemCoreClock = HSE_VALUE * pllmull;
+ }
+ #endif
+ }
+#else
+ pllmull = pllmull >> 18;
+
+ if (pllmull != 0x0D)
+ {
+ pllmull += 2;
+ }
+ else
+ { /* PLL multiplication factor = PLL input clock * 6.5 */
+ pllmull = 13 / 2;
+ }
+
+ if (pllsource == 0x00)
+ {
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {/* PREDIV1 selected as PLL clock entry */
+
+ /* Get PREDIV1 clock source and division factor */
+ prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+
+ if (prediv1source == 0)
+ {
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
+ }
+ else
+ {/* PLL2 clock selected as PREDIV1 clock entry */
+
+ /* Get PREDIV2 division factor and PLL2 multiplication factor */
+ prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
+ pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
+ SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
+ }
+ }
+#endif /* STM32F105xC */
+ break;
+
+ default:
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+
+ /* Compute HCLK clock frequency ----------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+/**
+ * @brief Setup the external memory controller. Called in startup_stm32f1xx.s
+ * before jump to __main
+ * @param None
+ * @retval None
+ */
+#ifdef DATA_IN_ExtSRAM
+/**
+ * @brief Setup the external memory controller.
+ * Called in startup_stm32f1xx_xx.s/.c before jump to main.
+ * This function configures the external SRAM mounted on STM3210E-EVAL
+ * board (STM32 High density devices). This SRAM will be used as program
+ * data memory (including heap and stack).
+ * @param None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void)
+{
+ __IO uint32_t tmpreg;
+ /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
+ required, then adjust the Register Addresses */
+
+ /* Enable FSMC clock */
+ RCC->AHBENR = 0x00000114;
+
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
+
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
+ RCC->APB2ENR = 0x000001E0;
+
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
+
+ (void)(tmpreg);
+
+/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
+/*---------------- SRAM Address lines configuration -------------------------*/
+/*---------------- NOE and NWE configuration --------------------------------*/
+/*---------------- NE3 configuration ----------------------------------------*/
+/*---------------- NBL0, NBL1 configuration ---------------------------------*/
+
+ GPIOD->CRL = 0x44BB44BB;
+ GPIOD->CRH = 0xBBBBBBBB;
+
+ GPIOE->CRL = 0xB44444BB;
+ GPIOE->CRH = 0xBBBBBBBB;
+
+ GPIOF->CRL = 0x44BBBBBB;
+ GPIOF->CRH = 0xBBBB4444;
+
+ GPIOG->CRL = 0x44BBBBBB;
+ GPIOG->CRH = 0x444B4B44;
+
+/*---------------- FSMC Configuration ---------------------------------------*/
+/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
+
+ FSMC_Bank1->BTCR[4] = 0x00001091;
+ FSMC_Bank1->BTCR[5] = 0x00110212;
+}
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+void SetSysClock(void)
+{
+ /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+ /* 2- If fail try to start with HSE and external xtal */
+ #if USE_PLL_HSE_XTAL != 0
+ if (SetSysClock_PLL_HSE(0) == 0)
+ #endif
+ {
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+ {
+ while(1)
+ {
+ // [TODO] Put something here to tell the user that a problem occured...
+ }
+ }
+ }
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); // 24 MHz
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ /* Enable HSE oscillator and activate PLL with HSE as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0)
+ {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+ }
+ else
+ {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+ }
+ RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV2;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6; // 24 MHz (4 MHz * 6)
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 24 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 24 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 24 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 24 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
+ {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+
+ return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ /* Enable HSI oscillator and activate PLL with HSI as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6; // 24 MHz (8 MHz/2 * 6)
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 24 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 24 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 24 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 24 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
+ {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 8 MHz
+
+ return 1; // OK
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.h
new file mode 100644
index 0000000000..e344021f31
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.h
@@ -0,0 +1,116 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f10x.h
+ * @author MCD Application Team
+ * @version V4.0.0
+ * @date 16-December-2014
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f10x_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F10X_H
+#define __SYSTEM_STM32F10X_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F10x_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F10x_System_Exported_types
+ * @{
+ */
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F10X_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/