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Diffstat (limited to 'tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X')
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/LPC82x.h1308
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_ARM_MICRO/LPC824.sct14
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s218
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_ARM/LPC824.ld152
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_ARM/startup_LPC824.s228
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_CR/LPC824.ld199
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_CR/startup_LPC824_CR.cpp351
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_IAR/LPC824.icf36
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_IAR/startup_LPC8xx.s216
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/system_LPC8xx.c389
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_ARM_MICRO/LPC824.sct14
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s218
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_GCC_ARM/LPC824.ld152
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_GCC_ARM/startup_LPC824.s228
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/system_LPC8xx.c389
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TOOLCHAIN_ARM_MICRO/sys.cpp31
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis.h13
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis_nvic.c55
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis_nvic.h51
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/system_LPC82x.h63
20 files changed, 4325 insertions, 0 deletions
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/LPC82x.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/LPC82x.h
new file mode 100644
index 0000000000..fee91c063a
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/LPC82x.h
@@ -0,0 +1,1308 @@
+
+/****************************************************************************************************//**
+ * @file LPC82x.h
+ *
+ * @brief CMSIS Cortex-M0PLUS Peripheral Access Layer Header File for
+ * LPC82x from .
+ *
+ * @version V0.4
+ * @date 17. June 2014
+ *
+ * @note Generated with SVDConv V2.80
+ * from CMSIS SVD File 'LPC82x.svd' Version 0.4,
+ *******************************************************************************************************/
+
+
+
+/** @addtogroup (null)
+ * @{
+ */
+
+/** @addtogroup LPC82x
+ * @{
+ */
+
+#ifndef LPC82X_H
+#define LPC82X_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum {
+/* ----------------- Cortex-M0PLUS Processor Exceptions Numbers ----------------- */
+ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
+ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
+ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< 15 System Tick Timer */
+/* ---------------------- LPC82x Specific Interrupt Numbers --------------------- */
+ SPI0_IRQn = 0, /*!< 0 SPI0 */
+ SPI1_IRQn = 1, /*!< 1 SPI1 */
+ UART0_IRQn = 3, /*!< 3 UART0 */
+ UART1_IRQn = 4, /*!< 4 UART1 */
+ UART2_IRQn = 5, /*!< 5 UART2 */
+ I2C1_IRQn = 7, /*!< 7 I2C1 */
+ I2C0_IRQn = 8, /*!< 8 I2C0 */
+ SCT_IRQn = 9, /*!< 9 SCT */
+ MRT_IRQn = 10, /*!< 10 MRT */
+ CMP_IRQn = 11, /*!< 11 CMP */
+ WDT_IRQn = 12, /*!< 12 WDT */
+ BOD_IRQn = 13, /*!< 13 BOD */
+ FLASH_IRQn = 14, /*!< 14 FLASH */
+ WKT_IRQn = 15, /*!< 15 WKT */
+ ADC_SEQA_IRQn = 16, /*!< 16 ADC_SEQA */
+ ADC_SEQB_IRQn = 17, /*!< 17 ADC_SEQB */
+ ADC_THCMP_IRQn = 18, /*!< 18 ADC_THCMP */
+ ADC_OVR_IRQn = 19, /*!< 19 ADC_OVR */
+ DMA_IRQn = 20, /*!< 20 DMA */
+ I2C2_IRQn = 21, /*!< 21 I2C2 */
+ I2C3_IRQn = 22, /*!< 22 I2C3 */
+ PIN_INT0_IRQn = 24, /*!< 24 PIN_INT0 */
+ PIN_INT1_IRQn = 25, /*!< 25 PIN_INT1 */
+ PIN_INT2_IRQn = 26, /*!< 26 PIN_INT2 */
+ PIN_INT3_IRQn = 27, /*!< 27 PIN_INT3 */
+ PIN_INT4_IRQn = 28, /*!< 28 PIN_INT4 */
+ PIN_INT5_IRQn = 29, /*!< 29 PIN_INT5 */
+ PIN_INT6_IRQn = 30, /*!< 30 PIN_INT6 */
+ PIN_INT7_IRQn = 31 /*!< 31 PIN_INT7 */
+} IRQn_Type;
+
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+
+/* ----------------Configuration of the Cortex-M0PLUS Processor and Core Peripherals---------------- */
+#define __CM0PLUS_REV 0x0001 /*!< Cortex-M0PLUS Core Revision */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm0plus.h" /*!< Cortex-M0PLUS processor and core peripherals */
+#include "system_LPC82x.h" /*!< LPC82x System */
+
+
+/* ================================================================================ */
+/* ================ Device Specific Peripheral Section ================ */
+/* ================================================================================ */
+
+
+/** @addtogroup Device_Peripheral_Registers
+ * @{
+ */
+
+
+/* ------------------- Start of section using anonymous unions ------------------ */
+#if defined(__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__ICCARM__)
+ #pragma language=extended
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning 586
+#else
+ #warning Not supported compiler type
+#endif
+
+
+
+/* ================================================================================ */
+/* ================ WWDT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Windowed Watchdog Timer (WWDT) (WWDT)
+ */
+
+typedef struct { /*!< (@ 0x40000000) WWDT Structure */
+ __IO uint32_t MOD; /*!< (@ 0x40000000) Watchdog mode register. This register contains
+ the basic mode and status of the Watchdog Timer. */
+ __IO uint32_t TC; /*!< (@ 0x40000004) Watchdog timer constant register. This 24-bit
+ register determines the time-out value. */
+ __O uint32_t FEED; /*!< (@ 0x40000008) Watchdog feed sequence register. Writing 0xAA
+ followed by 0x55 to this register reloads the Watchdog timer
+ with the value contained in WDTC. */
+ __I uint32_t TV; /*!< (@ 0x4000000C) Watchdog timer value register. This 24-bit register
+ reads out the current value of the Watchdog timer. */
+ __I uint32_t RESERVED0;
+ __IO uint32_t WARNINT; /*!< (@ 0x40000014) Watchdog Warning Interrupt compare value. */
+ __IO uint32_t WINDOW; /*!< (@ 0x40000018) Watchdog Window compare value. */
+} LPC_WWDT_Type;
+
+
+/* ================================================================================ */
+/* ================ MRT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Multi-Rate Timer (MRT) (MRT)
+ */
+
+typedef struct { /*!< (@ 0x40004000) MRT Structure */
+ __IO uint32_t INTVAL0; /*!< (@ 0x40004000) MRT0 Time interval value register. This value
+ is loaded into the TIMER0 register. */
+ __I uint32_t TIMER0; /*!< (@ 0x40004004) MRT0 Timer register. This register reads the
+ value of the down-counter. */
+ __IO uint32_t CTRL0; /*!< (@ 0x40004008) MRT0 Control register. This register controls
+ the MRT0 modes. */
+ __IO uint32_t STAT0; /*!< (@ 0x4000400C) MRT0 Status register. */
+ __IO uint32_t INTVAL1; /*!< (@ 0x40004010) MRT0 Time interval value register. This value
+ is loaded into the TIMER0 register. */
+ __I uint32_t TIMER1; /*!< (@ 0x40004014) MRT0 Timer register. This register reads the
+ value of the down-counter. */
+ __IO uint32_t CTRL1; /*!< (@ 0x40004018) MRT0 Control register. This register controls
+ the MRT0 modes. */
+ __IO uint32_t STAT1; /*!< (@ 0x4000401C) MRT0 Status register. */
+ __IO uint32_t INTVAL2; /*!< (@ 0x40004020) MRT0 Time interval value register. This value
+ is loaded into the TIMER0 register. */
+ __I uint32_t TIMER2; /*!< (@ 0x40004024) MRT0 Timer register. This register reads the
+ value of the down-counter. */
+ __IO uint32_t CTRL2; /*!< (@ 0x40004028) MRT0 Control register. This register controls
+ the MRT0 modes. */
+ __IO uint32_t STAT2; /*!< (@ 0x4000402C) MRT0 Status register. */
+ __IO uint32_t INTVAL3; /*!< (@ 0x40004030) MRT0 Time interval value register. This value
+ is loaded into the TIMER0 register. */
+ __I uint32_t TIMER3; /*!< (@ 0x40004034) MRT0 Timer register. This register reads the
+ value of the down-counter. */
+ __IO uint32_t CTRL3; /*!< (@ 0x40004038) MRT0 Control register. This register controls
+ the MRT0 modes. */
+ __IO uint32_t STAT3; /*!< (@ 0x4000403C) MRT0 Status register. */
+ __I uint32_t RESERVED0[45];
+ __I uint32_t IDLE_CH; /*!< (@ 0x400040F4) Idle channel register. This register returns
+ the number of the first idle channel. */
+ __IO uint32_t IRQ_FLAG; /*!< (@ 0x400040F8) Global interrupt flag register */
+} LPC_MRT_Type;
+
+
+/* ================================================================================ */
+/* ================ WKT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Self wake-up timer (WKT) (WKT)
+ */
+
+typedef struct { /*!< (@ 0x40008000) WKT Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x40008000) Self wake-up timer control register. */
+ __I uint32_t RESERVED0[2];
+ __IO uint32_t COUNT; /*!< (@ 0x4000800C) Counter register. */
+} LPC_WKT_Type;
+
+
+/* ================================================================================ */
+/* ================ SWM ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Switch matrix (SWM) (SWM)
+ */
+
+typedef struct { /*!< (@ 0x4000C000) SWM Structure */
+ union {
+ __IO uint32_t PINASSIGN[12];
+ struct {
+ __IO uint32_t PINASSIGN0; /*!< (@ 0x4000C000) Pin assign register 0. Assign movable functions
+ U0_TXD, U0_RXD, U0_RTS, U0_CTS. */
+ __IO uint32_t PINASSIGN1; /*!< (@ 0x4000C004) Pin assign register 1. Assign movable functions
+ U0_SCLK, U1_TXD, U1_RXD, U1_RTS. */
+ __IO uint32_t PINASSIGN2; /*!< (@ 0x4000C008) Pin assign register 2. Assign movable functions
+ U1_CTS, U1_SCLK, U2_TXD, U2_RXD. */
+ __IO uint32_t PINASSIGN3; /*!< (@ 0x4000C00C) Pin assign register 3. Assign movable function
+ U2_RTS, U2_CTS, U2_SCLK, SPI0_SCK. */
+ __IO uint32_t PINASSIGN4; /*!< (@ 0x4000C010) Pin assign register 4. Assign movable functions
+ SPI0_MOSI, SPI0_MISO, SPI0_SSEL0, SPI0_SSEL1. */
+ __IO uint32_t PINASSIGN5; /*!< (@ 0x4000C014) Pin assign register 5. Assign movable functions
+ SPI0_SSEL2, SPI0_SSEL3, SPI1_SCK, SPI1_MOSI */
+ __IO uint32_t PINASSIGN6; /*!< (@ 0x4000C018) Pin assign register 6. Assign movable functions
+ SPI1_MISO, SPI1_SSEL0, SPI1_SSEL1, SCT0_IN0. */
+ __IO uint32_t PINASSIGN7; /*!< (@ 0x4000C01C) Pin assign register 7. Assign movable functions
+ SCT_IN1, SCT_IN2, SCT_IN3, SCT_OUT0. */
+ __IO uint32_t PINASSIGN8; /*!< (@ 0x4000C020) Pin assign register 8. Assign movable functions
+ SCT_OUT1, SCT_OUT2, SCT_OUT3, SCT_OUT4. */
+ __IO uint32_t PINASSIGN9; /*!< (@ 0x4000C024) Pin assign register 9. Assign movable functions
+ SCT_OUT5, I2C1_SDA, I2C1_SCL, I2C2_SDA. */
+ __IO uint32_t PINASSIGN10; /*!< (@ 0x4000C028) Pin assign register 10. Assign movable functions
+ I2C2_SCL, I2C3_SDA, I2C3_SCL, ADC_PINTRIG0. */
+ __IO uint32_t PINASSIGN11; /*!< (@ 0x4000C02C) Pin assign register 11. Assign movable functions
+ ADC_PINTRIG1, ACMP_O, CLKOUT, GPIO_INT_BMAT */
+ };
+ };
+ __I uint32_t RESERVED0[100];
+ __IO uint32_t PINENABLE0; /*!< (@ 0x4000C1C0) Pin enable register 0. Enables fixed-pin functions
+ ACMP_I0, ACMP_I1, SWCLK, SWDIO, XTALIN, XTALOUT, RESET, CLKIN,
+ VDDCMP. */
+} LPC_SWM_Type;
+
+
+/* ================================================================================ */
+/* ================ ADC ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief 12-bit Analog-to-Digital Converter (ADC) (ADC)
+ */
+
+typedef struct { /*!< (@ 0x4001C000) ADC Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x4001C000) A/D Control Register. Contains the clock divide
+ value, enable bits for each sequence and the A/D power-down
+ bit. */
+ __I uint32_t RESERVED0;
+ __IO uint32_t SEQA_CTRL; /*!< (@ 0x4001C008) A/D Conversion Sequence-A control Register: Controls
+ triggering and channel selection for conversion sequence-A.
+ Also specifies interrupt mode for sequence-A. */
+ __IO uint32_t SEQB_CTRL; /*!< (@ 0x4001C00C) A/D Conversion Sequence-B Control Register: Controls
+ triggering and channel selection for conversion sequence-B.
+ Also specifies interrupt mode for sequence-B. */
+ __IO uint32_t SEQA_GDAT; /*!< (@ 0x4001C010) A/D Sequence-A Global Data Register. This register
+ contains the result of the most recent A/D conversion performed
+ under sequence-A */
+ __IO uint32_t SEQB_GDAT; /*!< (@ 0x4001C014) A/D Sequence-B Global Data Register. This register
+ contains the result of the most recent A/D conversion performed
+ under sequence-B */
+ __I uint32_t RESERVED1[2];
+ __I uint32_t DAT0; /*!< (@ 0x4001C020) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT1; /*!< (@ 0x4001C024) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT2; /*!< (@ 0x4001C028) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT3; /*!< (@ 0x4001C02C) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT4; /*!< (@ 0x4001C030) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT5; /*!< (@ 0x4001C034) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT6; /*!< (@ 0x4001C038) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT7; /*!< (@ 0x4001C03C) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT8; /*!< (@ 0x4001C040) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT9; /*!< (@ 0x4001C044) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT10; /*!< (@ 0x4001C048) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT11; /*!< (@ 0x4001C04C) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __IO uint32_t THR0_LOW; /*!< (@ 0x4001C050) A/D Low Compare Threshold Register 0 : Contains
+ the lower threshold level for automatic threshold comparison
+ for any channels linked to threshold pair 0. */
+ __IO uint32_t THR1_LOW; /*!< (@ 0x4001C054) A/D Low Compare Threshold Register 1: Contains
+ the lower threshold level for automatic threshold comparison
+ for any channels linked to threshold pair 1. */
+ __IO uint32_t THR0_HIGH; /*!< (@ 0x4001C058) A/D High Compare Threshold Register 0: Contains
+ the upper threshold level for automatic threshold comparison
+ for any channels linked to threshold pair 0. */
+ __IO uint32_t THR1_HIGH; /*!< (@ 0x4001C05C) A/D High Compare Threshold Register 1: Contains
+ the upper threshold level for automatic threshold comparison
+ for any channels linked to threshold pair 1. */
+ __IO uint32_t CHAN_THRSEL; /*!< (@ 0x4001C060) A/D Channel-Threshold Select Register. Specifies
+ which set of threshold compare registers are to be used for
+ each channel */
+ __IO uint32_t INTEN; /*!< (@ 0x4001C064) A/D Interrupt Enable Register. This register
+ contains enable bits that enable the sequence-A, sequence-B,
+ threshold compare and data overrun interrupts to be generated. */
+ __IO uint32_t FLAGS; /*!< (@ 0x4001C068) A/D Flags Register. Contains the four interrupt
+ request flags and the individual component overrun and threshold-compare
+ flags. (The overrun bits replicate information stored in the
+ result registers). */
+ __IO uint32_t TRM; /*!< (@ 0x4001C06C) ADC trim register. */
+} LPC_ADC_Type;
+
+
+/* ================================================================================ */
+/* ================ PMU ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Power Management Unit (PMU) (PMU)
+ */
+
+typedef struct { /*!< (@ 0x40020000) PMU Structure */
+ __IO uint32_t PCON; /*!< (@ 0x40020000) Power control register */
+ __IO uint32_t GPREG0; /*!< (@ 0x40020004) General purpose register 0 */
+ __IO uint32_t GPREG1; /*!< (@ 0x40020008) General purpose register 0 */
+ __IO uint32_t GPREG2; /*!< (@ 0x4002000C) General purpose register 0 */
+ __IO uint32_t GPREG3; /*!< (@ 0x40020010) General purpose register 0 */
+ __IO uint32_t DPDCTRL; /*!< (@ 0x40020014) Deep power-down control register. Also includes
+ bits for general purpose storage. */
+} LPC_PMU_Type;
+
+
+/* ================================================================================ */
+/* ================ CMP ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Analog comparator (CMP)
+ */
+
+typedef struct { /*!< (@ 0x40024000) CMP Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x40024000) Comparator control register */
+ __IO uint32_t LAD; /*!< (@ 0x40024004) Voltage ladder register */
+} LPC_CMP_Type;
+
+
+/* ================================================================================ */
+/* ================ DMATRIGMUX ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief DMA trigger mux (DMATRIGMUX)
+ */
+
+typedef struct { /*!< (@ 0x40028000) DMATRIGMUX Structure */
+ __IO uint32_t DMA_ITRIG_INMUX0; /*!< (@ 0x40028000) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX1; /*!< (@ 0x40028004) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX2; /*!< (@ 0x40028008) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX3; /*!< (@ 0x4002800C) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX4; /*!< (@ 0x40028010) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX5; /*!< (@ 0x40028014) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX6; /*!< (@ 0x40028018) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX7; /*!< (@ 0x4002801C) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX8; /*!< (@ 0x40028020) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX9; /*!< (@ 0x40028024) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX10; /*!< (@ 0x40028028) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX11; /*!< (@ 0x4002802C) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX12; /*!< (@ 0x40028030) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX13; /*!< (@ 0x40028034) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX14; /*!< (@ 0x40028038) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX15; /*!< (@ 0x4002803C) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX16; /*!< (@ 0x40028040) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX17; /*!< (@ 0x40028044) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+} LPC_DMATRIGMUX_Type;
+
+
+/* ================================================================================ */
+/* ================ INPUTMUX ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Input multiplexing (INPUTMUX)
+ */
+
+typedef struct { /*!< (@ 0x4002C000) INPUTMUX Structure */
+ __IO uint32_t DMA_INMUX_INMUX0; /*!< (@ 0x4002C000) Input mux register for DMA trigger input 20.
+ Selects from 18 DMA trigger outputs. */
+ __IO uint32_t DMA_INMUX_INMUX1; /*!< (@ 0x4002C004) Input mux register for DMA trigger input 20.
+ Selects from 18 DMA trigger outputs. */
+ __I uint32_t RESERVED0[6];
+ __IO uint32_t SCT0_INMUX0; /*!< (@ 0x4002C020) Input mux register for SCT input 0 */
+ __IO uint32_t SCT0_INMUX1; /*!< (@ 0x4002C024) Input mux register for SCT input 0 */
+ __IO uint32_t SCT0_INMUX2; /*!< (@ 0x4002C028) Input mux register for SCT input 0 */
+ __IO uint32_t SCT0_INMUX3; /*!< (@ 0x4002C02C) Input mux register for SCT input 0 */
+} LPC_INPUTMUX_Type;
+
+
+/* ================================================================================ */
+/* ================ FLASHCTRL ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Flash controller (FLASHCTRL)
+ */
+
+typedef struct { /*!< (@ 0x40040000) FLASHCTRL Structure */
+ __I uint32_t RESERVED0[4];
+ __IO uint32_t FLASHCFG; /*!< (@ 0x40040010) Flash configuration register */
+ __I uint32_t RESERVED1[3];
+ __IO uint32_t FMSSTART; /*!< (@ 0x40040020) Signature start address register */
+ __IO uint32_t FMSSTOP; /*!< (@ 0x40040024) Signature stop-address register */
+ __I uint32_t RESERVED2;
+ __I uint32_t FMSW0; /*!< (@ 0x4004002C) Signature Word */
+} LPC_FLASHCTRL_Type;
+
+
+/* ================================================================================ */
+/* ================ IOCON ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief I/O configuration (IOCON) (IOCON)
+ */
+
+typedef struct { /*!< (@ 0x40044000) IOCON Structure */
+ __IO uint32_t PIO0_17; /*!< (@ 0x40044000) I/O configuration for pin PIO0_17 */
+ __IO uint32_t PIO0_13; /*!< (@ 0x40044004) I/O configuration for pin PIO0_13 */
+ __IO uint32_t PIO0_12; /*!< (@ 0x40044008) I/O configuration for pin PIO0_12 */
+ __IO uint32_t PIO0_5; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_5/RESET */
+ __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4 */
+ __IO uint32_t PIO0_3; /*!< (@ 0x40044014) I/O configuration for pin PIO0_3/SWCLK */
+ __IO uint32_t PIO0_2; /*!< (@ 0x40044018) I/O configuration for pin PIO0_2/SWDIO */
+ __IO uint32_t PIO0_11; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11. This is the
+ pin configuration for the true open-drain pin. */
+ __IO uint32_t PIO0_10; /*!< (@ 0x40044020) I/O configuration for pin PIO0_10. This is the
+ pin configuration for the true open-drain pin. */
+ __IO uint32_t PIO0_16; /*!< (@ 0x40044024) I/O configuration for pin PIO0_16 */
+ __IO uint32_t PIO0_15; /*!< (@ 0x40044028) I/O configuration for pin PIO0_15 */
+ __IO uint32_t PIO0_1; /*!< (@ 0x4004402C) I/O configuration for pin PIO0_17 */
+ __I uint32_t RESERVED0;
+ __IO uint32_t PIO0_9; /*!< (@ 0x40044034) I/O configuration for pin PIO0_9/XTALOUT */
+ __IO uint32_t PIO0_8; /*!< (@ 0x40044038) I/O configuration for pin PIO0_8/XTALIN */
+ __IO uint32_t PIO0_7; /*!< (@ 0x4004403C) I/O configuration for pin PIO0_7 */
+ __IO uint32_t PIO0_6; /*!< (@ 0x40044040) I/O configuration for pin PIO0_6/VDDCMP */
+ __IO uint32_t PIO0_0; /*!< (@ 0x40044044) I/O configuration for pin PIO0_0/ACMP_I0 */
+ __IO uint32_t PIO0_14; /*!< (@ 0x40044048) I/O configuration for pin PIO0_14 */
+ __I uint32_t RESERVED1;
+ __IO uint32_t PIO0_28; /*!< (@ 0x40044050) I/O configuration for pin PIO0_28 */
+ __IO uint32_t PIO0_27; /*!< (@ 0x40044054) I/O configuration for pin PIO0_27 */
+ __IO uint32_t PIO0_26; /*!< (@ 0x40044058) I/O configuration for pin PIO0_26 */
+ __IO uint32_t PIO0_25; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_25 */
+ __IO uint32_t PIO0_24; /*!< (@ 0x40044060) I/O configuration for pin PIO0_24 */
+ __IO uint32_t PIO0_23; /*!< (@ 0x40044064) I/O configuration for pin PIO0_23/ADC_3 */
+ __IO uint32_t PIO0_22; /*!< (@ 0x40044068) I/O configuration for pin PIO0_22/ADC_4 */
+ __IO uint32_t PIO0_21; /*!< (@ 0x4004406C) I/O configuration for pin PIO0_21/ACMP_I4/ADC_5 */
+ __IO uint32_t PIO0_20; /*!< (@ 0x40044070) I/O configuration for pin PIO0_20/ADC_6 */
+ __IO uint32_t PIO0_19; /*!< (@ 0x40044074) I/O configuration for pin PIO0_19/ADC_7 */
+ __IO uint32_t PIO0_18; /*!< (@ 0x40044078) I/O configuration for pin PIO0_18/ADC_8 */
+} LPC_IOCON_Type;
+
+
+/* ================================================================================ */
+/* ================ SYSCON ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief System configuration (SYSCON) (SYSCON)
+ */
+
+typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
+ __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
+ __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
+ __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
+ __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
+ __I uint32_t RESERVED0[4];
+ __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
+ __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
+ __IO uint32_t IRCCTRL; /*!< (@ 0x40048028) IRC control */
+ __I uint32_t RESERVED1;
+ __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
+ __I uint32_t RESERVED2[3];
+ __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
+ __IO uint32_t SYSPLLCLKUEN; /*!< (@ 0x40048044) System PLL clock source update enable */
+ __I uint32_t RESERVED3[10];
+ __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
+ __IO uint32_t MAINCLKUEN; /*!< (@ 0x40048074) Main clock source update enable */
+ __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
+ __I uint32_t RESERVED4;
+ __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
+ __I uint32_t RESERVED5[4];
+ __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048094) USART clock divider */
+ __I uint32_t RESERVED6[18];
+ __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
+ __IO uint32_t CLKOUTUEN; /*!< (@ 0x400480E4) CLKOUT clock source update enable */
+ __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
+ __I uint32_t RESERVED7;
+ __IO uint32_t UARTFRGDIV; /*!< (@ 0x400480F0) USART1 to USART4 common fractional generator
+ divider value */
+ __IO uint32_t UARTFRGMULT; /*!< (@ 0x400480F4) USART1 to USART4 common fractional generator
+ multiplier value */
+ __I uint32_t RESERVED8;
+ __IO uint32_t EXTTRACECMD; /*!< (@ 0x400480FC) External trace buffer command register */
+ __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
+ __I uint32_t RESERVED9[12];
+ __IO uint32_t IOCONCLKDIV6; /*!< (@ 0x40048134) Peripheral clock 6 to the IOCON block for programmable
+ glitch filter */
+ __I uint32_t RESERVED10[6];
+ __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
+ __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
+ __I uint32_t RESERVED11[6];
+ __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay. Allows trade-off between interrupt
+ latency and determinism. */
+ __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
+ union {
+ __IO uint32_t PINTSEL[8];
+ struct {
+ __IO uint32_t PINTSEL0; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL1; /*!< (@ 0x4004817C) GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL2; /*!< (@ 0x40048180) GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL3; /*!< (@ 0x40048184) GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL4; /*!< (@ 0x40048188) GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL5; /*!< (@ 0x4004818C) GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL6; /*!< (@ 0x40048190) GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL7; /*!< (@ 0x40048194) GPIO Pin Interrupt Select register 0 */
+ };
+ };
+ __I uint32_t RESERVED12[27];
+ __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 pin wake-up enable register */
+ __I uint32_t RESERVED13[3];
+ __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register */
+ __I uint32_t RESERVED14[6];
+ __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
+ __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
+ __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
+ __I uint32_t RESERVED15[111];
+ __I uint32_t DEVICE_ID; /*!< (@ 0x400483F8) Device ID */
+} LPC_SYSCON_Type;
+
+
+/* ================================================================================ */
+/* ================ I2C0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief I2C0-bus interface (I2C0)
+ */
+
+typedef struct { /*!< (@ 0x40050000) I2C0 Structure */
+ __IO uint32_t CFG; /*!< (@ 0x40050000) Configuration for shared functions. */
+ __IO uint32_t STAT; /*!< (@ 0x40050004) Status register for Master, Slave, and Monitor
+ functions. */
+ __IO uint32_t INTENSET; /*!< (@ 0x40050008) Interrupt Enable Set and read register. */
+ __O uint32_t INTENCLR; /*!< (@ 0x4005000C) Interrupt Enable Clear register. */
+ __IO uint32_t TIMEOUT; /*!< (@ 0x40050010) Time-out value register. */
+ __IO uint32_t CLKDIV; /*!< (@ 0x40050014) Clock pre-divider for the entire I2C block. This
+ determines what time increments are used for the MSTTIME and
+ SLVTIME registers. */
+ __I uint32_t INTSTAT; /*!< (@ 0x40050018) Interrupt Status register for Master, Slave,
+ and Monitor functions. */
+ __I uint32_t RESERVED0;
+ __IO uint32_t MSTCTL; /*!< (@ 0x40050020) Master control register. */
+ __IO uint32_t MSTTIME; /*!< (@ 0x40050024) Master timing configuration. */
+ __IO uint32_t MSTDAT; /*!< (@ 0x40050028) Combined Master receiver and transmitter data
+ register. */
+ __I uint32_t RESERVED1[5];
+ __IO uint32_t SLVCTL; /*!< (@ 0x40050040) Slave control register. */
+ __IO uint32_t SLVDAT; /*!< (@ 0x40050044) Combined Slave receiver and transmitter data
+ register. */
+ union {
+ __IO uint32_t SLVADR[4];
+ struct {
+ __IO uint32_t SLVADR0; /*!< (@ 0x40050048) Slave address 0. */
+ __IO uint32_t SLVADR1; /*!< (@ 0x4005004C) Slave address 0. */
+ __IO uint32_t SLVADR2; /*!< (@ 0x40050050) Slave address 0. */
+ __IO uint32_t SLVADR3; /*!< (@ 0x40050054) Slave address 0. */
+ };
+ };
+ __IO uint32_t SLVQUAL0; /*!< (@ 0x40050058) Slave Qualification for address 0. */
+ __I uint32_t RESERVED2[9];
+ __I uint32_t MONRXDAT; /*!< (@ 0x40050080) Monitor receiver data register. */
+} LPC_I2C0_Type;
+
+
+/* ================================================================================ */
+/* ================ SPI0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief SPI0 (SPI0)
+ */
+
+typedef struct { /*!< (@ 0x40058000) SPI0 Structure */
+ __IO uint32_t CFG; /*!< (@ 0x40058000) SPI Configuration register */
+ __IO uint32_t DLY; /*!< (@ 0x40058004) SPI Delay register */
+ __IO uint32_t STAT; /*!< (@ 0x40058008) SPI Status. Some status flags can be cleared
+ by writing a 1 to that bit position */
+ __IO uint32_t INTENSET; /*!< (@ 0x4005800C) SPI Interrupt Enable read and Set. A complete
+ value may be read from this register. Writing a 1 to any implemented
+ bit position causes that bit to be set. */
+ __O uint32_t INTENCLR; /*!< (@ 0x40058010) SPI Interrupt Enable Clear. Writing a 1 to any
+ implemented bit position causes the corresponding bit in INTENSET
+ to be cleared. */
+ __I uint32_t RXDAT; /*!< (@ 0x40058014) SPI Receive Data */
+ __IO uint32_t TXDATCTL; /*!< (@ 0x40058018) SPI Transmit Data with Control */
+ __IO uint32_t TXDAT; /*!< (@ 0x4005801C) SPI Transmit Data */
+ __IO uint32_t TXCTL; /*!< (@ 0x40058020) SPI Transmit Control */
+ __IO uint32_t DIV; /*!< (@ 0x40058024) SPI clock Divider */
+ __I uint32_t INTSTAT; /*!< (@ 0x40058028) SPI Interrupt Status */
+} LPC_SPI0_Type;
+
+
+/* ================================================================================ */
+/* ================ USART0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief USART0 (USART0)
+ */
+
+typedef struct { /*!< (@ 0x40064000) USART0 Structure */
+ __IO uint32_t CFG; /*!< (@ 0x40064000) USART Configuration register. Basic USART configuration
+ settings that typically are not changed during operation. */
+ __IO uint32_t CTL; /*!< (@ 0x40064004) USART Control register. USART control settings
+ that are more likely to change during operation. */
+ __IO uint32_t STAT; /*!< (@ 0x40064008) USART Status register. The complete status value
+ can be read here. Writing ones clears some bits in the register.
+ Some bits can be cleared by writing a 1 to them. */
+ __IO uint32_t INTENSET; /*!< (@ 0x4006400C) Interrupt Enable read and Set register. Contains
+ an individual interrupt enable bit for each potential USART
+ interrupt. A complete value may be read from this register.
+ Writing a 1 to any implemented bit position causes that bit
+ to be set. */
+ __O uint32_t INTENCLR; /*!< (@ 0x40064010) Interrupt Enable Clear register. Allows clearing
+ any combination of bits in the INTENSET register. Writing a
+ 1 to any implemented bit position causes the corresponding bit
+ to be cleared. */
+ __I uint32_t RXDAT; /*!< (@ 0x40064014) Receiver Data register. Contains the last character
+ received. */
+ __I uint32_t RXDATSTAT; /*!< (@ 0x40064018) Receiver Data with Status register. Combines
+ the last character received with the current USART receive status.
+ Allows DMA or software to recover incoming data and status together. */
+ __IO uint32_t TXDAT; /*!< (@ 0x4006401C) Transmit Data register. Data to be transmitted
+ is written here. */
+ __IO uint32_t BRG; /*!< (@ 0x40064020) Baud Rate Generator register. 16-bit integer
+ baud rate divisor value. */
+ __I uint32_t INTSTAT; /*!< (@ 0x40064024) Interrupt status register. Reflects interrupts
+ that are currently enabled. */
+ __IO uint32_t OSR; /*!< (@ 0x40064028) Oversample selection register for asynchronous
+ communication. */
+ __IO uint32_t ADDR; /*!< (@ 0x4006402C) Address register for automatic address matching. */
+} LPC_USART0_Type;
+
+
+/* ================================================================================ */
+/* ================ CRC ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Cyclic Redundancy Check (CRC) engine (CRC)
+ */
+
+typedef struct { /*!< (@ 0x50000000) CRC Structure */
+ __IO uint32_t MODE; /*!< (@ 0x50000000) CRC mode register */
+ __IO uint32_t SEED; /*!< (@ 0x50000004) CRC seed register */
+
+ union {
+ __O uint32_t WR_DATA; /*!< (@ 0x50000008) CRC data register */
+ __I uint32_t SUM; /*!< (@ 0x50000008) CRC checksum register */
+ };
+} LPC_CRC_Type;
+
+
+/* ================================================================================ */
+/* ================ SCT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief State Configurable Timer (SCT) (SCT)
+ */
+
+typedef struct { /*!< (@ 0x50004000) SCT Structure */
+ __IO uint32_t CONFIG; /*!< (@ 0x50004000) SCT configuration register */
+ __IO uint32_t CTRL; /*!< (@ 0x50004004) SCT control register */
+ __IO uint32_t LIMIT; /*!< (@ 0x50004008) SCT limit register */
+ __IO uint32_t HALT; /*!< (@ 0x5000400C) SCT halt condition register */
+ __IO uint32_t STOP; /*!< (@ 0x50004010) SCT stop condition register */
+ __IO uint32_t START; /*!< (@ 0x50004014) SCT start condition register */
+ __I uint32_t RESERVED0[10];
+ __IO uint32_t COUNT; /*!< (@ 0x50004040) SCT counter register */
+ __IO uint32_t STATE; /*!< (@ 0x50004044) SCT state register */
+ __I uint32_t INPUT; /*!< (@ 0x50004048) SCT input register */
+ __IO uint32_t REGMODE; /*!< (@ 0x5000404C) SCT match/capture registers mode register */
+ __IO uint32_t OUTPUT; /*!< (@ 0x50004050) SCT output register */
+ __IO uint32_t OUTPUTDIRCTRL; /*!< (@ 0x50004054) SCT output counter direction control register */
+ __IO uint32_t RES; /*!< (@ 0x50004058) SCT conflict resolution register */
+ __IO uint32_t DMAREQ0; /*!< (@ 0x5000405C) SCT DMA request 0 register */
+ __IO uint32_t DMAREQ1; /*!< (@ 0x50004060) SCT DMA request 1 register */
+ __I uint32_t RESERVED1[35];
+ __IO uint32_t EVEN; /*!< (@ 0x500040F0) SCT event enable register */
+ __IO uint32_t EVFLAG; /*!< (@ 0x500040F4) SCT event flag register */
+ __IO uint32_t CONEN; /*!< (@ 0x500040F8) SCT conflict enable register */
+ __IO uint32_t CONFLAG; /*!< (@ 0x500040FC) SCT conflict flag register */
+
+union {
+ union {
+ __IO uint32_t CAP0; /*!< (@ 0x50004100) SCT capture register of capture channel 0 to
+ 7; REGMOD0 to REGMODE7 = 1 */
+ __IO uint32_t MATCH0; /*!< (@ 0x50004100) SCT match value register of match channels 0
+ to 7; REGMOD0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t CAP1; /*!< (@ 0x50004104) SCT capture register of capture channel 0 to
+ 7; REGMOD0 to REGMODE7 = 1 */
+ __IO uint32_t MATCH1; /*!< (@ 0x50004104) SCT match value register of match channels 0
+ to 7; REGMOD0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t CAP2; /*!< (@ 0x50004108) SCT capture register of capture channel 0 to
+ 7; REGMOD0 to REGMODE7 = 1 */
+ __IO uint32_t MATCH2; /*!< (@ 0x50004108) SCT match value register of match channels 0
+ to 7; REGMOD0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t MATCH3; /*!< (@ 0x5000410C) SCT match value register of match channels 0
+ to 7; REGMOD0 to REGMODE7 = 0 */
+ __IO uint32_t CAP3; /*!< (@ 0x5000410C) SCT capture register of capture channel 0 to
+ 7; REGMOD0 to REGMODE7 = 1 */
+ };
+
+ union {
+ __IO uint32_t CAP4; /*!< (@ 0x50004110) SCT capture register of capture channel 0 to
+ 7; REGMOD0 to REGMODE7 = 1 */
+ __IO uint32_t MATCH4; /*!< (@ 0x50004110) SCT match value register of match channels 0
+ to 7; REGMOD0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t MATCH5; /*!< (@ 0x50004114) SCT match value register of match channels 0
+ to 7; REGMOD0 to REGMODE7 = 0 */
+ __IO uint32_t CAP5; /*!< (@ 0x50004114) SCT capture register of capture channel 0 to
+ 7; REGMOD0 to REGMODE7 = 1 */
+ };
+
+ union {
+ __IO uint32_t CAP6; /*!< (@ 0x50004118) SCT capture register of capture channel 0 to
+ 7; REGMOD0 to REGMODE7 = 1 */
+ __IO uint32_t MATCH6; /*!< (@ 0x50004118) SCT match value register of match channels 0
+ to 7; REGMOD0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t CAP7; /*!< (@ 0x5000411C) SCT capture register of capture channel 0 to
+ 7; REGMOD0 to REGMODE7 = 1 */
+ __IO uint32_t MATCH7; /*!< (@ 0x5000411C) SCT match value register of match channels 0
+ to 7; REGMOD0 to REGMODE7 = 0 */
+ };
+ __IO uint32_t CAP[8];
+ __IO uint32_t MATCH[8];
+};
+ __I uint32_t RESERVED2[56];
+
+ union {
+ struct {
+ union {
+ __IO uint32_t CAPCTRL0; /*!< (@ 0x50004200) SCT capture control register 0 to 7; REGMOD0
+ = 1 to REGMODE7 = 1 */
+ __IO uint32_t MATCHREL0; /*!< (@ 0x50004200) SCT match reload value register 0 to 7; REGMOD0
+ = 0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL1; /*!< (@ 0x50004204) SCT capture control register 0 to 7; REGMOD0
+ = 1 to REGMODE7 = 1 */
+ __IO uint32_t MATCHREL1; /*!< (@ 0x50004204) SCT match reload value register 0 to 7; REGMOD0
+ = 0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL2; /*!< (@ 0x50004208) SCT capture control register 0 to 7; REGMOD0
+ = 1 to REGMODE7 = 1 */
+ __IO uint32_t MATCHREL2; /*!< (@ 0x50004208) SCT match reload value register 0 to 7; REGMOD0
+ = 0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t MATCHREL3; /*!< (@ 0x5000420C) SCT match reload value register 0 to 7; REGMOD0
+ = 0 to REGMODE7 = 0 */
+ __IO uint32_t CAPCTRL3; /*!< (@ 0x5000420C) SCT capture control register 0 to 7; REGMOD0
+ = 1 to REGMODE7 = 1 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL4; /*!< (@ 0x50004210) SCT capture control register 0 to 7; REGMOD0
+ = 1 to REGMODE7 = 1 */
+ __IO uint32_t MATCHREL4; /*!< (@ 0x50004210) SCT match reload value register 0 to 7; REGMOD0
+ = 0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL5; /*!< (@ 0x50004214) SCT capture control register 0 to 7; REGMOD0
+ = 1 to REGMODE7 = 1 */
+ __IO uint32_t MATCHREL5; /*!< (@ 0x50004214) SCT match reload value register 0 to 7; REGMOD0
+ = 0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL6; /*!< (@ 0x50004218) SCT capture control register 0 to 7; REGMOD0
+ = 1 to REGMODE7 = 1 */
+ __IO uint32_t MATCHREL6; /*!< (@ 0x50004218) SCT match reload value register 0 to 7; REGMOD0
+ = 0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL7; /*!< (@ 0x5000421C) SCT capture control register 0 to 7; REGMOD0
+ = 1 to REGMODE7 = 1 */
+ __IO uint32_t MATCHREL7; /*!< (@ 0x5000421C) SCT match reload value register 0 to 7; REGMOD0
+ = 0 to REGMODE7 = 0 */
+ };
+ };
+ __IO uint32_t MATCHREL[8];
+ };
+ __I uint32_t RESERVED3[56];
+
+ union {
+ struct {
+ __IO uint32_t EV0_STATE; /*!< (@ 0x50004300) SCT event state register 0 */
+ __IO uint32_t EV0_CTRL; /*!< (@ 0x50004304) SCT event control register 0 */
+ __IO uint32_t EV1_STATE; /*!< (@ 0x50004308) SCT event state register 0 */
+ __IO uint32_t EV1_CTRL; /*!< (@ 0x5000430C) SCT event control register 0 */
+ __IO uint32_t EV2_STATE; /*!< (@ 0x50004310) SCT event state register 0 */
+ __IO uint32_t EV2_CTRL; /*!< (@ 0x50004314) SCT event control register 0 */
+ __IO uint32_t EV3_STATE; /*!< (@ 0x50004318) SCT event state register 0 */
+ __IO uint32_t EV3_CTRL; /*!< (@ 0x5000431C) SCT event control register 0 */
+ __IO uint32_t EV4_STATE; /*!< (@ 0x50004320) SCT event state register 0 */
+ __IO uint32_t EV4_CTRL; /*!< (@ 0x50004324) SCT event control register 0 */
+ __IO uint32_t EV5_STATE; /*!< (@ 0x50004328) SCT event state register 0 */
+ __IO uint32_t EV5_CTRL; /*!< (@ 0x5000432C) SCT event control register 0 */
+ __IO uint32_t EV6_STATE; /*!< (@ 0x50004330) SCT event state register 0 */
+ __IO uint32_t EV6_CTRL; /*!< (@ 0x50004334) SCT event control register 0 */
+ __IO uint32_t EV7_STATE; /*!< (@ 0x50004338) SCT event state register 0 */
+ __IO uint32_t EV7_CTRL; /*!< (@ 0x5000433C) SCT event control register 0 */
+ };
+ __IO struct {
+ uint32_t STATE;
+ uint32_t CTRL;
+ } EVENT[8];
+ };
+
+ __I uint32_t RESERVED4[112];
+
+ union {
+ struct {
+ __IO uint32_t OUT0_SET; /*!< (@ 0x50004500) SCT output 0 set register */
+ __IO uint32_t OUT0_CLR; /*!< (@ 0x50004504) SCT output 0 clear register */
+ __IO uint32_t OUT1_SET; /*!< (@ 0x50004508) SCT output 0 set register */
+ __IO uint32_t OUT1_CLR; /*!< (@ 0x5000450C) SCT output 0 clear register */
+ __IO uint32_t OUT2_SET; /*!< (@ 0x50004510) SCT output 0 set register */
+ __IO uint32_t OUT2_CLR; /*!< (@ 0x50004514) SCT output 0 clear register */
+ __IO uint32_t OUT3_SET; /*!< (@ 0x50004518) SCT output 0 set register */
+ __IO uint32_t OUT3_CLR; /*!< (@ 0x5000451C) SCT output 0 clear register */
+ __IO uint32_t OUT4_SET; /*!< (@ 0x50004520) SCT output 0 set register */
+ __IO uint32_t OUT4_CLR; /*!< (@ 0x50004524) SCT output 0 clear register */
+ __IO uint32_t OUT5_SET; /*!< (@ 0x50004528) SCT output 0 set register */
+ __IO uint32_t OUT5_CLR; /*!< (@ 0x5000452C) SCT output 0 clear register */
+ };
+ __IO struct {
+ uint32_t SET;
+ uint32_t CLR;
+ } OUT[6];
+};
+
+} LPC_SCT_Type;
+
+
+/* ================================================================================ */
+/* ================ DMA ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief DMA controller (DMA)
+ */
+
+typedef struct { /*!< (@ 0x50008000) DMA Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x50008000) DMA control. */
+ __I uint32_t INTSTAT; /*!< (@ 0x50008004) Interrupt status. */
+ __IO uint32_t SRAMBASE; /*!< (@ 0x50008008) SRAM address of the channel configuration table. */
+ __I uint32_t RESERVED0[5];
+ __IO uint32_t ENABLESET0; /*!< (@ 0x50008020) Channel Enable read and Set for all DMA channels. */
+ __I uint32_t RESERVED1;
+ __O uint32_t ENABLECLR0; /*!< (@ 0x50008028) Channel Enable Clear for all DMA channels. */
+ __I uint32_t RESERVED2;
+ __I uint32_t ACTIVE0; /*!< (@ 0x50008030) Channel Active status for all DMA channels. */
+ __I uint32_t RESERVED3;
+ __I uint32_t BUSY0; /*!< (@ 0x50008038) Channel Busy status for all DMA channels. */
+ __I uint32_t RESERVED4;
+ __IO uint32_t ERRINT0; /*!< (@ 0x50008040) Error Interrupt status for all DMA channels. */
+ __I uint32_t RESERVED5;
+ __IO uint32_t INTENSET0; /*!< (@ 0x50008048) Interrupt Enable read and Set for all DMA channels. */
+ __I uint32_t RESERVED6;
+ __O uint32_t INTENCLR0; /*!< (@ 0x50008050) Interrupt Enable Clear for all DMA channels. */
+ __I uint32_t RESERVED7;
+ __IO uint32_t INTA0; /*!< (@ 0x50008058) Interrupt A status for all DMA channels. */
+ __I uint32_t RESERVED8;
+ __IO uint32_t INTB0; /*!< (@ 0x50008060) Interrupt B status for all DMA channels. */
+ __I uint32_t RESERVED9;
+ __O uint32_t SETVALID0; /*!< (@ 0x50008068) Set ValidPending control bits for all DMA channels. */
+ __I uint32_t RESERVED10;
+ __O uint32_t SETTRIG0; /*!< (@ 0x50008070) Set Trigger control bits for all DMA channels. */
+ __I uint32_t RESERVED11;
+ __O uint32_t ABORT0; /*!< (@ 0x50008078) Channel Abort control for all DMA channels. */
+ __I uint32_t RESERVED12[225];
+ __IO uint32_t CFG0; /*!< (@ 0x50008400) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT0; /*!< (@ 0x50008404) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG0; /*!< (@ 0x50008408) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED13;
+ __IO uint32_t CFG1; /*!< (@ 0x50008410) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT1; /*!< (@ 0x50008414) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG1; /*!< (@ 0x50008418) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED14;
+ __IO uint32_t CFG2; /*!< (@ 0x50008420) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT2; /*!< (@ 0x50008424) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG2; /*!< (@ 0x50008428) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED15;
+ __IO uint32_t CFG3; /*!< (@ 0x50008430) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT3; /*!< (@ 0x50008434) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG3; /*!< (@ 0x50008438) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED16;
+ __IO uint32_t CFG4; /*!< (@ 0x50008440) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT4; /*!< (@ 0x50008444) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG4; /*!< (@ 0x50008448) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED17;
+ __IO uint32_t CFG5; /*!< (@ 0x50008450) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT5; /*!< (@ 0x50008454) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG5; /*!< (@ 0x50008458) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED18;
+ __IO uint32_t CFG6; /*!< (@ 0x50008460) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT6; /*!< (@ 0x50008464) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG6; /*!< (@ 0x50008468) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED19;
+ __IO uint32_t CFG7; /*!< (@ 0x50008470) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT7; /*!< (@ 0x50008474) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG7; /*!< (@ 0x50008478) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED20;
+ __IO uint32_t CFG8; /*!< (@ 0x50008480) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT8; /*!< (@ 0x50008484) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG8; /*!< (@ 0x50008488) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED21;
+ __IO uint32_t CFG9; /*!< (@ 0x50008490) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT9; /*!< (@ 0x50008494) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG9; /*!< (@ 0x50008498) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED22;
+ __IO uint32_t CFG10; /*!< (@ 0x500084A0) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT10; /*!< (@ 0x500084A4) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG10; /*!< (@ 0x500084A8) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED23;
+ __IO uint32_t CFG11; /*!< (@ 0x500084B0) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT11; /*!< (@ 0x500084B4) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG11; /*!< (@ 0x500084B8) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED24;
+ __IO uint32_t CFG12; /*!< (@ 0x500084C0) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT12; /*!< (@ 0x500084C4) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG12; /*!< (@ 0x500084C8) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED25;
+ __IO uint32_t CFG13; /*!< (@ 0x500084D0) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT13; /*!< (@ 0x500084D4) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG13; /*!< (@ 0x500084D8) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED26;
+ __IO uint32_t CFG14; /*!< (@ 0x500084E0) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT14; /*!< (@ 0x500084E4) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG14; /*!< (@ 0x500084E8) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED27;
+ __IO uint32_t CFG15; /*!< (@ 0x500084F0) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT15; /*!< (@ 0x500084F4) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG15; /*!< (@ 0x500084F8) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED28;
+ __IO uint32_t CFG16; /*!< (@ 0x50008500) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT16; /*!< (@ 0x50008504) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG16; /*!< (@ 0x50008508) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED29;
+ __IO uint32_t CFG17; /*!< (@ 0x50008510) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT17; /*!< (@ 0x50008514) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG17; /*!< (@ 0x50008518) Transfer configuration register for DMA channel
+ 0. */
+} LPC_DMA_Type;
+
+
+/* ================================================================================ */
+/* ================ GPIO_PORT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief General Purpose I/O port (GPIO) (GPIO_PORT)
+ */
+
+typedef struct { /*!< (@ 0xA0000000) GPIO_PORT Structure */
+ __IO uint8_t B0; /*!< (@ 0xA0000000) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B1; /*!< (@ 0xA0000001) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B2; /*!< (@ 0xA0000002) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B3; /*!< (@ 0xA0000003) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B4; /*!< (@ 0xA0000004) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B5; /*!< (@ 0xA0000005) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B6; /*!< (@ 0xA0000006) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B7; /*!< (@ 0xA0000007) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B8; /*!< (@ 0xA0000008) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B9; /*!< (@ 0xA0000009) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B10; /*!< (@ 0xA000000A) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B11; /*!< (@ 0xA000000B) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B12; /*!< (@ 0xA000000C) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B13; /*!< (@ 0xA000000D) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B14; /*!< (@ 0xA000000E) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B15; /*!< (@ 0xA000000F) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B16; /*!< (@ 0xA0000010) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B17; /*!< (@ 0xA0000011) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B18; /*!< (@ 0xA0000012) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B19; /*!< (@ 0xA0000013) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B20; /*!< (@ 0xA0000014) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B21; /*!< (@ 0xA0000015) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B22; /*!< (@ 0xA0000016) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B23; /*!< (@ 0xA0000017) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B24; /*!< (@ 0xA0000018) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B25; /*!< (@ 0xA0000019) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B26; /*!< (@ 0xA000001A) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B27; /*!< (@ 0xA000001B) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B28; /*!< (@ 0xA000001C) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __I uint8_t RESERVED0[4067];
+ __IO uint32_t W0; /*!< (@ 0xA0001000) Word pin registers port 0 */
+ __IO uint32_t W1; /*!< (@ 0xA0001004) Word pin registers port 0 */
+ __IO uint32_t W2; /*!< (@ 0xA0001008) Word pin registers port 0 */
+ __IO uint32_t W3; /*!< (@ 0xA000100C) Word pin registers port 0 */
+ __IO uint32_t W4; /*!< (@ 0xA0001010) Word pin registers port 0 */
+ __IO uint32_t W5; /*!< (@ 0xA0001014) Word pin registers port 0 */
+ __IO uint32_t W6; /*!< (@ 0xA0001018) Word pin registers port 0 */
+ __IO uint32_t W7; /*!< (@ 0xA000101C) Word pin registers port 0 */
+ __IO uint32_t W8; /*!< (@ 0xA0001020) Word pin registers port 0 */
+ __IO uint32_t W9; /*!< (@ 0xA0001024) Word pin registers port 0 */
+ __IO uint32_t W10; /*!< (@ 0xA0001028) Word pin registers port 0 */
+ __IO uint32_t W11; /*!< (@ 0xA000102C) Word pin registers port 0 */
+ __IO uint32_t W12; /*!< (@ 0xA0001030) Word pin registers port 0 */
+ __IO uint32_t W13; /*!< (@ 0xA0001034) Word pin registers port 0 */
+ __IO uint32_t W14; /*!< (@ 0xA0001038) Word pin registers port 0 */
+ __IO uint32_t W15; /*!< (@ 0xA000103C) Word pin registers port 0 */
+ __IO uint32_t W16; /*!< (@ 0xA0001040) Word pin registers port 0 */
+ __IO uint32_t W17; /*!< (@ 0xA0001044) Word pin registers port 0 */
+ __IO uint32_t W18; /*!< (@ 0xA0001048) Word pin registers port 0 */
+ __IO uint32_t W19; /*!< (@ 0xA000104C) Word pin registers port 0 */
+ __IO uint32_t W20; /*!< (@ 0xA0001050) Word pin registers port 0 */
+ __IO uint32_t W21; /*!< (@ 0xA0001054) Word pin registers port 0 */
+ __IO uint32_t W22; /*!< (@ 0xA0001058) Word pin registers port 0 */
+ __IO uint32_t W23; /*!< (@ 0xA000105C) Word pin registers port 0 */
+ __IO uint32_t W24; /*!< (@ 0xA0001060) Word pin registers port 0 */
+ __IO uint32_t W25; /*!< (@ 0xA0001064) Word pin registers port 0 */
+ __IO uint32_t W26; /*!< (@ 0xA0001068) Word pin registers port 0 */
+ __IO uint32_t W27; /*!< (@ 0xA000106C) Word pin registers port 0 */
+ __IO uint32_t W28; /*!< (@ 0xA0001070) Word pin registers port 0 */
+ __I uint32_t RESERVED1[995];
+ __IO uint32_t DIR0; /*!< (@ 0xA0002000) Direction registers port 0 */
+ __I uint32_t RESERVED2[31];
+ __IO uint32_t MASK0; /*!< (@ 0xA0002080) Mask register port 0 */
+ __I uint32_t RESERVED3[31];
+ __IO uint32_t PIN0; /*!< (@ 0xA0002100) Port pin register port 0 */
+ __I uint32_t RESERVED4[31];
+ __IO uint32_t MPIN0; /*!< (@ 0xA0002180) Masked port register port 0 */
+ __I uint32_t RESERVED5[31];
+ __IO uint32_t SET0; /*!< (@ 0xA0002200) Write: Set register for port 0 Read: output bits
+ for port 0 */
+ __I uint32_t RESERVED6[31];
+ __O uint32_t CLR0; /*!< (@ 0xA0002280) Clear port 0 */
+ __I uint32_t RESERVED7[31];
+ __O uint32_t NOT0; /*!< (@ 0xA0002300) Toggle port 0 */
+ __I uint32_t RESERVED8[31];
+ __O uint32_t DIRSET0; /*!< (@ 0xA0002380) Set pin direction bits for port 0. */
+ __I uint32_t RESERVED9[31];
+ __O uint32_t DIRCLR0; /*!< (@ 0xA0002400) Clear pin direction bits for port 0. */
+ __I uint32_t RESERVED10[31];
+ __O uint32_t DIRNOT0; /*!< (@ 0xA0002480) Toggle pin direction bits for port 0. */
+} LPC_GPIO_PORT_Type;
+
+
+/* ================================================================================ */
+/* ================ PIN_INT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Pin interrupt and pattern match engine (PIN_INT)
+ */
+
+typedef struct { /*!< (@ 0xA0004000) PIN_INT Structure */
+ __IO uint32_t ISEL; /*!< (@ 0xA0004000) Pin Interrupt Mode register */
+ __IO uint32_t IENR; /*!< (@ 0xA0004004) Pin interrupt level or rising edge interrupt
+ enable register */
+ __O uint32_t SIENR; /*!< (@ 0xA0004008) Pin interrupt level (rising edge) interrupt set
+ register */
+ __O uint32_t CIENR; /*!< (@ 0xA000400C) Pin interrupt level or rising edge interrupt
+ clear register */
+ __IO uint32_t IENF; /*!< (@ 0xA0004010) Pin interrupt active level or falling edge interrupt
+ enable register */
+ __O uint32_t SIENF; /*!< (@ 0xA0004014) Pin interrupt active level or falling edge interrupt
+ set register */
+ __O uint32_t CIENF; /*!< (@ 0xA0004018) Pin interrupt active level (falling edge) interrupt
+ clear register */
+ __IO uint32_t RISE; /*!< (@ 0xA000401C) Pin interrupt rising edge register */
+ __IO uint32_t FALL; /*!< (@ 0xA0004020) Pin interrupt falling edge register */
+ __IO uint32_t IST; /*!< (@ 0xA0004024) Pin interrupt status register */
+ __IO uint32_t PMCTRL; /*!< (@ 0xA0004028) GPIO pattern match interrupt control register */
+ __IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source
+ register */
+ __IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration
+ register */
+} LPC_PIN_INT_Type;
+
+
+/* -------------------- End of section using anonymous unions ------------------- */
+#if defined(__CC_ARM)
+ #pragma pop
+#elif defined(__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning restore
+#else
+ #warning Not supported compiler type
+#endif
+
+
+
+
+/* ================================================================================ */
+/* ================ Peripheral memory map ================ */
+/* ================================================================================ */
+
+#define LPC_WWDT_BASE 0x40000000UL
+#define LPC_MRT_BASE 0x40004000UL
+#define LPC_WKT_BASE 0x40008000UL
+#define LPC_SWM_BASE 0x4000C000UL
+#define LPC_ADC_BASE 0x4001C000UL
+#define LPC_PMU_BASE 0x40020000UL
+#define LPC_CMP_BASE 0x40024000UL
+#define LPC_DMATRIGMUX_BASE 0x40028000UL
+#define LPC_INPUTMUX_BASE 0x4002C000UL
+#define LPC_FLASHCTRL_BASE 0x40040000UL
+#define LPC_IOCON_BASE 0x40044000UL
+#define LPC_SYSCON_BASE 0x40048000UL
+#define LPC_I2C0_BASE 0x40050000UL
+#define LPC_I2C1_BASE 0x40054000UL
+#define LPC_SPI0_BASE 0x40058000UL
+#define LPC_SPI1_BASE 0x4005C000UL
+#define LPC_USART0_BASE 0x40064000UL
+#define LPC_USART1_BASE 0x40068000UL
+#define LPC_USART2_BASE 0x4006C000UL
+#define LPC_I2C2_BASE 0x40070000UL
+#define LPC_I2C3_BASE 0x40074000UL
+#define LPC_CRC_BASE 0x50000000UL
+#define LPC_SCT_BASE 0x50004000UL
+#define LPC_DMA_BASE 0x50008000UL
+#define LPC_GPIO_PORT_BASE 0xA0000000UL
+#define LPC_PIN_INT_BASE 0xA0004000UL
+
+
+/* ================================================================================ */
+/* ================ Peripheral declaration ================ */
+/* ================================================================================ */
+
+#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
+#define LPC_MRT ((LPC_MRT_Type *) LPC_MRT_BASE)
+#define LPC_WKT ((LPC_WKT_Type *) LPC_WKT_BASE)
+#define LPC_SWM ((LPC_SWM_Type *) LPC_SWM_BASE)
+#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
+#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
+#define LPC_CMP ((LPC_CMP_Type *) LPC_CMP_BASE)
+#define LPC_DMATRIGMUX ((LPC_DMATRIGMUX_Type *) LPC_DMATRIGMUX_BASE)
+#define LPC_INPUTMUX ((LPC_INPUTMUX_Type *) LPC_INPUTMUX_BASE)
+#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
+#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
+#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
+#define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
+#define LPC_I2C1 ((LPC_I2C0_Type *) LPC_I2C1_BASE)
+#define LPC_SPI0 ((LPC_SPI0_Type *) LPC_SPI0_BASE)
+#define LPC_SPI1 ((LPC_SPI0_Type *) LPC_SPI1_BASE)
+#define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
+#define LPC_USART1 ((LPC_USART0_Type *) LPC_USART1_BASE)
+#define LPC_USART2 ((LPC_USART0_Type *) LPC_USART2_BASE)
+#define LPC_I2C2 ((LPC_I2C0_Type *) LPC_I2C2_BASE)
+#define LPC_I2C3 ((LPC_I2C0_Type *) LPC_I2C3_BASE)
+#define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
+#define LPC_SCT ((LPC_SCT_Type *) LPC_SCT_BASE)
+#define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
+#define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
+#define LPC_PIN_INT ((LPC_PIN_INT_Type *) LPC_PIN_INT_BASE)
+
+
+/** @} */ /* End of group Device_Peripheral_Registers */
+/** @} */ /* End of group LPC82x */
+/** @} */ /* End of group (null) */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* LPC82x_H */
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_ARM_MICRO/LPC824.sct b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_ARM_MICRO/LPC824.sct
new file mode 100644
index 0000000000..310aa82197
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_ARM_MICRO/LPC824.sct
@@ -0,0 +1,14 @@
+
+LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
+ ER_IROM1 0x00000000 0x8000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0x1F40
+ RW_IRAM1 0x10000000+0xC0 0x2000-0xC0 {
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s
new file mode 100644
index 0000000000..a90d8d290e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s
@@ -0,0 +1,218 @@
+;/*****************************************************************************
+; * @file: startup_LPC8xx.s
+; * @purpose: CMSIS Cortex-M0+ Core Device Startup File
+; * for the NXP LPC8xx Device Series
+; * @version: V1.0
+; * @date: 16. Aug. 2012
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2012 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+__initial_sp EQU 0x10002000
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD SPI0_IRQHandler ; SPI0 controller
+ DCD SPI1_IRQHandler ; SPI1 controller
+ DCD 0 ; Reserved
+ DCD UART0_IRQHandler ; UART0
+ DCD UART1_IRQHandler ; UART1
+ DCD UART2_IRQHandler ; UART2
+ DCD 0 ; Reserved
+ DCD I2C1_IRQHandler ; I2C1 controller
+ DCD I2C0_IRQHandler ; I2C0 controller
+ DCD SCT_IRQHandler ; Smart Counter Timer
+ DCD MRT_IRQHandler ; Multi-Rate Timer
+ DCD CMP_IRQHandler ; Comparator
+ DCD WDT_IRQHandler ; PIO1 (0:11)
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD Flash_IRQHandler ; Flash interrupt
+ DCD WKT_IRQHandler ; Wakeup timer
+ DCD ADC_SEQA_IRQHandler ; ADC sequence A completion
+ DCD ADC_SEQB_IRQHandler ; ADC sequence B completion
+ DCD ADC_THCMP_IRQHandler ; ADC threshold compare
+ DCD ADC_OVR_IRQHandler ; ADC overrun
+ DCD DMA__RQHandler ; DMA interrupt
+ DCD I2C2_IRQHandler ; I2C2 controller
+ DCD I2C3_IRQHandler ; I2C3 controller
+ DCD 0 ; Reserved
+ DCD PININT0_IRQHandler ; PIO INT0
+ DCD PININT1_IRQHandler ; PIO INT1
+ DCD PININT2_IRQHandler ; PIO INT2
+ DCD PININT3_IRQHandler ; PIO INT3
+ DCD PININT4_IRQHandler ; PIO INT4
+ DCD PININT5_IRQHandler ; PIO INT5
+ DCD PININT6_IRQHandler ; PIO INT6
+ DCD PININT7_IRQHandler ; PIO INT7
+
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT NMI_Handler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT SCT_IRQHandler [WEAK]
+ EXPORT MRT_IRQHandler [WEAK]
+ EXPORT CMP_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT Flash_IRQHandler [WEAK]
+ EXPORT WKT_IRQHandler [WEAK]
+ EXPORT ADC_SEQA_IRQHandler [WEAK]
+ EXPORT ADC_SEQB_IRQHandler [WEAK]
+ EXPORT ADC_THCMP_IRQHandler [WEAK]
+ EXPORT ADC_OVR_IRQHandler [WEAK]
+ EXPORT DMA__RQHandler [WEAK]
+ EXPORT I2C2_IRQHandler [WEAK]
+ EXPORT I2C3_IRQHandler [WEAK]
+ EXPORT PININT0_IRQHandler [WEAK]
+ EXPORT PININT1_IRQHandler [WEAK]
+ EXPORT PININT2_IRQHandler [WEAK]
+ EXPORT PININT3_IRQHandler [WEAK]
+ EXPORT PININT4_IRQHandler [WEAK]
+ EXPORT PININT5_IRQHandler [WEAK]
+ EXPORT PININT6_IRQHandler [WEAK]
+ EXPORT PININT7_IRQHandler [WEAK]
+
+NMI_Handler
+SPI0_IRQHandler
+SPI1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+I2C1_IRQHandler
+I2C0_IRQHandler
+SCT_IRQHandler
+MRT_IRQHandler
+CMP_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+Flash_IRQHandler
+WKT_IRQHandler
+ADC_SEQA_IRQHandler
+ADC_SEQB_IRQHandler
+ADC_THCMP_IRQHandler
+ADC_OVR_IRQHandler
+DMA__RQHandler
+I2C2_IRQHandler
+I2C3_IRQHandler
+PININT0_IRQHandler
+PININT1_IRQHandler
+PININT2_IRQHandler
+PININT3_IRQHandler
+PININT4_IRQHandler
+PININT5_IRQHandler
+PININT6_IRQHandler
+PININT7_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_ARM/LPC824.ld b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_ARM/LPC824.ld
new file mode 100644
index 0000000000..be901736a7
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_ARM/LPC824.ld
@@ -0,0 +1,152 @@
+/* Linker script for mbed LPC824-GCC-ARM based on LPC1114-GCC-ARM-LPC1114.ld */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ /* Define each memory region */
+ FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x8000 /* 32K bytes */
+ RAM (rwx) : ORIGIN = 0x10000000+0xC0, LENGTH = 0x2000-0xC0 /* 8K bytes */
+
+
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text.Reset_Handler)
+ *(.text.SystemInit)
+ . = 0x200;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_ARM/startup_LPC824.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_ARM/startup_LPC824.s
new file mode 100644
index 0000000000..c4273d680b
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_ARM/startup_LPC824.s
@@ -0,0 +1,228 @@
+/* File: startup_ARMCM0.S
+ * Purpose: startup file for Cortex-M0 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V1.2
+ * Date: 15 Nov 2011
+ *
+ * Copyright (c) 2011, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of the ARM Limited nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ .syntax unified
+ .arch armv6-m
+
+/* Memory Model
+ The HEAP starts at the end of the DATA section and grows upward.
+
+ The STACK starts at the end of the RAM and grows downward.
+
+ The HEAP and stack STACK are only checked at compile time:
+ (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+
+ This is just a check for the bare minimum for the Heap+Stack area before
+ aborting compilation, it is not the run time limit:
+ Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x80
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x80
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+/* LPC824 interrupts */
+ .long SPI0_IRQHandler // SPI0 controller
+ .long SPI1_IRQHandler // SPI1 controller
+ .long 0 // Reserved
+ .long UART0_IRQHandler // UART0
+ .long UART1_IRQHandler // UART1
+ .long UART2_IRQHandler // UART2
+ .long 0 // Reserved
+ .long I2C1_IRQHandler // I2C ch1 controller
+ .long I2C0_IRQHandler // I2C ch0 controller
+ .long SCT_IRQHandler // Smart Counter Timer
+ .long MRT_IRQHandler // Multi-Rate Timer
+ .long CMP_IRQHandler // Comparator
+ .long WDT_IRQHandler // PIO1 (0:11)
+ .long BOD_IRQHandler // Brown Out Detect
+ .long Flash_IRQHandler // Flash interrupt
+ .long WKT_IRQHandler // Wakeup timer
+ .long ADC_SEQA_IRQHandler // ADC sequence A completion
+ .long ADC_SEQB_IRQHandler // ADC sequence B completion
+ .long ADC_THCMP_IRQHandler // ADC threshold compare
+ .long ADC_OVR_IRQHandler // ADC overrun
+ .long DMA_IRQHandler // DMA interrupt
+ .long I2C2_IRQHandler // I2C2 controller
+ .long I2C3_IRQHandler // I2C3 controller
+ .long 0 // Reserved
+ .long PININT0_IRQHandler // PIO INT0
+ .long PININT1_IRQHandler // PIO INT1
+ .long PININT2_IRQHandler // PIO INT2
+ .long PININT3_IRQHandler // PIO INT3
+ .long PININT4_IRQHandler // PIO INT4
+ .long PININT5_IRQHandler // PIO INT5
+ .long PININT6_IRQHandler // PIO INT6
+ .long PININT7_IRQHandler // PIO INT7
+
+ .size __isr_vector, . - __isr_vector
+
+ .section .text.Reset_Handler
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .Lflash_to_ram_loop_end
+
+ movs r4, 0
+.Lflash_to_ram_loop:
+ ldr r0, [r1,r4]
+ str r0, [r2,r4]
+ adds r4, 4
+ cmp r4, r3
+ blt .Lflash_to_ram_loop
+.Lflash_to_ram_loop_end:
+
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_default_handler SPI0_IRQHandler
+ def_irq_default_handler SPI1_IRQHandler
+ def_irq_default_handler UART0_IRQHandler
+ def_irq_default_handler UART1_IRQHandler
+ def_irq_default_handler UART2_IRQHandler
+ def_irq_default_handler I2C0_IRQHandler
+ def_irq_default_handler I2C1_IRQHandler
+ def_irq_default_handler I2C2_IRQHandler
+ def_irq_default_handler I2C3_IRQHandler
+ def_irq_default_handler SCT_IRQHandler
+ def_irq_default_handler MRT_IRQHandler
+ def_irq_default_handler CMP_IRQHandler
+ def_irq_default_handler WDT_IRQHandler
+ def_irq_default_handler BOD_IRQHandler
+ def_irq_default_handler Flash_IRQHandler
+ def_irq_default_handler WKT_IRQHandler
+ def_irq_default_handler ADC_SEQA_IRQHandler
+ def_irq_default_handler ADC_SEQB_IRQHandler
+ def_irq_default_handler ADC_THCMP_IRQHandler
+ def_irq_default_handler ADC_OVR_IRQHandler
+ def_irq_default_handler DMA_IRQHandler
+ def_irq_default_handler PININT0_IRQHandler
+ def_irq_default_handler PININT1_IRQHandler
+ def_irq_default_handler PININT2_IRQHandler
+ def_irq_default_handler PININT3_IRQHandler
+ def_irq_default_handler PININT4_IRQHandler
+ def_irq_default_handler PININT5_IRQHandler
+ def_irq_default_handler PININT6_IRQHandler
+ def_irq_default_handler PININT7_IRQHandler
+
+ .end
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_CR/LPC824.ld b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_CR/LPC824.ld
new file mode 100644
index 0000000000..8774dea29e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_CR/LPC824.ld
@@ -0,0 +1,199 @@
+/*Based on following file
+ * (c) Code Red Technologies Ltd, 2008-13
+ * (c) NXP Semiconductors 2013-2015
+ * Generated linker script file for LPC824
+ * Created from generic_c.ld (LPCXpresso v7.4 (0 [Build 229] [2014-09-16] ))
+ * By LPCXpresso v7.4.0 [Build 229] [2014-09-16] on Fri Jan 02 03:36:48 JST 2015
+ */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ /* Define each memory region */
+ MFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x8000 /* 32K bytes */
+ RamLoc8 (rwx) : ORIGIN = 0x10000000+0xC0, LENGTH = 0x2000-0xC0 /* 8K bytes */
+
+
+}
+
+ /* Define a symbol for the top of each memory region */
+ __top_MFlash32 = 0x0 + 0x8000;
+ __top_RamLoc8 = 0x10000000 + 0x2000;
+
+GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
+/*GROUP(libcr_nohost.a libcr_c.a libcr_eabihelpers.a libm.a)*/
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(ResetISR)
+
+SECTIONS
+{
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ __vectors_start__ = ABSOLUTE(.) ;
+ KEEP(*(.isr_vector))
+
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data));
+ LONG( SIZEOF(.data));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+
+ *(.after_vectors*)
+ } >MFlash32
+
+ .text : ALIGN(4)
+ {
+ *(.text*)
+ *(.rodata .rodata.* .constdata .constdata.*)
+ . = ALIGN(4);
+
+
+ /* C++ constructors etc */
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ KEEP(*(.fini));
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+
+
+
+ } > MFlash32
+
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash32
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > MFlash32
+ __exidx_end = .;
+
+ _etext = .;
+
+
+ /* MAIN DATA SECTION */
+
+ /* Default MTB section */
+ .mtb_buffer_default (NOLOAD) :
+ {
+ KEEP(*(.mtb*))
+ } > RamLoc8
+
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ . = ALIGN(4) ;
+ _end_uninit_RESERVED = .;
+ } > RamLoc8
+
+
+ /* Main DATA section (RamLoc8) */
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = . ;
+ *(vtable)
+ *(.ramfunc*)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = . ;
+ } > RamLoc8 AT>MFlash32
+
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ } > RamLoc8
+
+
+ /* DEFAULT NOINIT SECTION */
+ .noinit (NOLOAD): ALIGN(4)
+ {
+ _noinit = .;
+ *(.noinit*)
+ . = ALIGN(4) ;
+ _end_noinit = .;
+ } > RamLoc8
+
+ PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
+ PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc8 - 0);
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_CR/startup_LPC824_CR.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_CR/startup_LPC824_CR.cpp
new file mode 100644
index 0000000000..e40d1ada21
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_CR/startup_LPC824_CR.cpp
@@ -0,0 +1,351 @@
+//*****************************************************************************
+// LPC82x Microcontroller Startup code for use with LPCXpresso IDE
+//
+// Version : 140901
+//*****************************************************************************
+//
+// Copyright(C) NXP Semiconductors, 2014
+// All rights reserved.
+//
+// Software that is described herein is for illustrative purposes only
+// which provides customers with programming information regarding the
+// LPC products. This software is supplied "AS IS" without any warranties of
+// any kind, and NXP Semiconductors and its licensor disclaim any and
+// all warranties, express or implied, including all implied warranties of
+// merchantability, fitness for a particular purpose and non-infringement of
+// intellectual property rights. NXP Semiconductors assumes no responsibility
+// or liability for the use of the software, conveys no license or rights under any
+// patent, copyright, mask work right, or any other intellectual property rights in
+// or to any products. NXP Semiconductors reserves the right to make changes
+// in the software without notification. NXP Semiconductors also makes no
+// representation or warranty that such application will be suitable for the
+// specified use without further testing or modification.
+//
+// Permission to use, copy, modify, and distribute this software and its
+// documentation is hereby granted, under NXP Semiconductors' and its
+// licensor's relevant copyrights in the software, without fee, provided that it
+// is used in conjunction with NXP Semiconductors microcontrollers. This
+// copyright, permission, and disclaimer notice must appear in all copies of
+// this code.
+//*****************************************************************************
+
+#if defined (__cplusplus)
+#ifdef __REDLIB__
+#error Redlib does not support C++
+#else
+//*****************************************************************************
+//
+// The entry point for the C++ library startup
+//
+//*****************************************************************************
+extern "C" {
+ extern void __libc_init_array(void);
+}
+#endif
+#endif
+
+#define WEAK __attribute__ ((weak))
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))
+
+//*****************************************************************************
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+//*****************************************************************************
+#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
+// Declaration of external SystemInit function
+extern void SystemInit(void);
+#endif
+
+// Patch the AEABI integer divide functions to use MCU's romdivide library
+#ifdef __USE_ROMDIVIDE
+// Location in memory that holds the address of the ROM Driver table
+#define PTR_ROM_DRIVER_TABLE ((unsigned int *)(0x1FFF1FF8))
+// Variables to store addresses of idiv and udiv functions within MCU ROM
+unsigned int *pDivRom_idiv;
+unsigned int *pDivRom_uidiv;
+#endif
+
+//*****************************************************************************
+//
+// Forward declaration of the default handlers. These are aliased.
+// When the application defines a handler (with the same name), this will
+// automatically take precedence over these weak definitions
+//
+//*****************************************************************************
+ void ResetISR(void);
+WEAK void NMI_Handler(void);
+WEAK void HardFault_Handler(void);
+WEAK void SVC_Handler(void);
+WEAK void PendSV_Handler(void);
+WEAK void SysTick_Handler(void);
+WEAK void IntDefaultHandler(void);
+
+//*****************************************************************************
+//
+// Forward declaration of the specific IRQ handlers. These are aliased
+// to the IntDefaultHandler, which is a 'forever' loop. When the application
+// defines a handler (with the same name), this will automatically take
+// precedence over these weak definitions
+//
+//*****************************************************************************
+void SPI0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SPI1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SCT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void MRT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CMP_IRQHandler(void) ALIAS(IntDefaultHandler);
+void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
+void FLASH_IRQHandler(void) ALIAS(IntDefaultHandler);
+void WKT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC_SEQA_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC_SEQB_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC_THCMP_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC_OVR_IRQHandler(void) ALIAS(IntDefaultHandler);
+void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT4_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT5_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT6_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT7_IRQHandler(void) ALIAS(IntDefaultHandler);
+//*****************************************************************************
+//
+// The entry point for the application.
+// __main() is the entry point for Redlib based applications
+// main() is the entry point for Newlib based applications
+//
+//*****************************************************************************
+#if defined (__REDLIB__)
+extern void __main(void);
+#else
+extern int main(void);
+#endif
+//*****************************************************************************
+//
+// External declaration for the pointer to the stack top from the Linker Script
+//
+//*****************************************************************************
+extern void _vStackTop(void);
+
+//*****************************************************************************
+#if defined (__cplusplus)
+} // extern "C"
+#endif
+//*****************************************************************************
+//
+// The vector table.
+// This relies on the linker script to place at correct location in memory.
+//
+//*****************************************************************************
+extern void (* const g_pfnVectors[])(void);
+__attribute__ ((section(".isr_vector")))
+void (* const g_pfnVectors[])(void) = {
+ // Core Level - CM0plus
+ &_vStackTop, // The initial stack pointer
+ ResetISR, // The reset handler
+ NMI_Handler, // The NMI handler
+ HardFault_Handler, // The hard fault handler
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ SVC_Handler, // SVCall handler
+ 0, // Reserved
+ 0, // Reserved
+ PendSV_Handler, // The PendSV handler
+ SysTick_Handler, // The SysTick handler
+
+ // Chip Level - LPC82x
+ SPI0_IRQHandler, // SPI0 controller
+ SPI1_IRQHandler, // SPI1 controller
+ 0, // Reserved
+ UART0_IRQHandler, // UART0
+ UART1_IRQHandler, // UART1
+ UART2_IRQHandler, // UART2
+ 0, // Reserved
+ I2C1_IRQHandler, // I2C1 controller
+ I2C0_IRQHandler, // I2C0 controller
+ SCT_IRQHandler, // Smart Counter Timer
+ MRT_IRQHandler, // Multi-Rate Timer
+ CMP_IRQHandler, // Comparator
+ WDT_IRQHandler, // Watchdog
+ BOD_IRQHandler, // Brown Out Detect
+ FLASH_IRQHandler, // Flash Interrupt
+ WKT_IRQHandler, // Wakeup timer
+ ADC_SEQA_IRQHandler, // ADC sequence A completion
+ ADC_SEQB_IRQHandler, // ADC sequence B completion
+ ADC_THCMP_IRQHandler, // ADC threshold compare
+ ADC_OVR_IRQHandler, // ADC overrun
+ DMA_IRQHandler, // DMA
+ I2C2_IRQHandler, // I2C2 controller
+ I2C3_IRQHandler, // I2C3 controller
+ 0, // Reserved
+ PIN_INT0_IRQHandler, // PIO INT0
+ PIN_INT1_IRQHandler, // PIO INT1
+ PIN_INT2_IRQHandler, // PIO INT2
+ PIN_INT3_IRQHandler, // PIO INT3
+ PIN_INT4_IRQHandler, // PIO INT4
+ PIN_INT5_IRQHandler, // PIO INT5
+ PIN_INT6_IRQHandler, // PIO INT6
+ PIN_INT7_IRQHandler, // PIO INT7
+}; /* End of g_pfnVectors */
+
+//*****************************************************************************
+// Functions to carry out the initialization of RW and BSS data sections. These
+// are written as separate functions rather than being inlined within the
+// ResetISR() function in order to cope with MCUs with multiple banks of
+// memory.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int *pulSrc = (unsigned int*) romstart;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4)
+ *pulDest++ = *pulSrc++;
+}
+
+__attribute__ ((section(".after_vectors")))
+void bss_init(unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4)
+ *pulDest++ = 0;
+}
+
+//*****************************************************************************
+// The following symbols are constructs generated by the linker, indicating
+// the location of various points in the "Global Section Table". This table is
+// created by the linker via the Code Red managed linker script mechanism. It
+// contains the load address, execution address and length of each RW data
+// section and the execution and length of each BSS (zero initialized) section.
+//*****************************************************************************
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+
+
+//*****************************************************************************
+// Reset entry point for your code.
+// Sets up a simple runtime environment and initializes the C/C++
+// library.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void
+ResetISR(void) {
+
+ //
+ // Copy the data sections from flash to SRAM.
+ //
+ unsigned int LoadAddr, ExeAddr, SectionLen;
+ unsigned int *SectionTableAddr;
+
+ // Load base address of Global Section Table
+ SectionTableAddr = &__data_section_table;
+
+ // Copy the data sections from flash to SRAM.
+ while (SectionTableAddr < &__data_section_table_end) {
+ LoadAddr = *SectionTableAddr++;
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ data_init(LoadAddr, ExeAddr, SectionLen);
+ }
+ // At this point, SectionTableAddr = &__bss_section_table;
+ // Zero fill the bss segment
+ while (SectionTableAddr < &__bss_section_table_end) {
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ bss_init(ExeAddr, SectionLen);
+ }
+
+ // Patch the AEABI integer divide functions to use MCU's romdivide library
+#ifdef __USE_ROMDIVIDE
+ // Get address of Integer division routines function table in ROM
+ unsigned int *div_ptr = (unsigned int *)((unsigned int *)*(PTR_ROM_DRIVER_TABLE))[4];
+ // Get addresses of integer divide routines in ROM
+ // These address are then used by the code in aeabi_romdiv_patch.s
+ pDivRom_idiv = (unsigned int *)div_ptr[0];
+ pDivRom_uidiv = (unsigned int *)div_ptr[1];
+#endif
+
+#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
+ SystemInit();
+#endif
+
+#if defined (__cplusplus)
+ //
+ // Call C++ library initialisation
+ //
+ __libc_init_array();
+#endif
+
+#if defined (__REDLIB__)
+ // Call the Redlib library, which in turn calls main()
+ __main() ;
+#else
+ main();
+#endif
+
+ //
+ // main() shouldn't return, but if it does, we'll just enter an infinite loop
+ //
+ while (1) {
+ ;
+ }
+}
+
+//*****************************************************************************
+// Default exception handlers. Override the ones here by defining your own
+// handler routines in your application code.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void NMI_Handler(void)
+{ while(1) {}
+}
+
+__attribute__ ((section(".after_vectors")))
+void HardFault_Handler(void)
+{ while(1) {}
+}
+
+__attribute__ ((section(".after_vectors")))
+void SVC_Handler(void)
+{ while(1) {}
+}
+
+__attribute__ ((section(".after_vectors")))
+void PendSV_Handler(void)
+{ while(1) {}
+}
+
+__attribute__ ((section(".after_vectors")))
+void SysTick_Handler(void)
+{ while(1) {}
+}
+
+//*****************************************************************************
+//
+// Processor ends up here if an unexpected interrupt occurs or a specific
+// handler is not present in the application code.
+//
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void IntDefaultHandler(void)
+{ while(1) {}
+}
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_IAR/LPC824.icf b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_IAR/LPC824.icf
new file mode 100644
index 0000000000..16aac8518e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_IAR/LPC824.icf
@@ -0,0 +1,36 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x100000BF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x100000C0;
+define symbol __ICFEDIT_region_RAM_end__ = 0x10001FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0xA00;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __CRP_start__ = 0x000002FC;
+define symbol __CRP_end__ = 0x000002FF;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region CRP_region = mem:[from __CRP_start__ to __CRP_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block HEAP, block CSTACK };
+place in CRP_region { section .crp };
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_IAR/startup_LPC8xx.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_IAR/startup_LPC8xx.s
new file mode 100644
index 0000000000..e02868b54d
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_IAR/startup_LPC8xx.s
@@ -0,0 +1,216 @@
+/**************************************************
+ *
+ * Part one of the system initialization code, contains low-level
+ * initialization, plain thumb variant.
+ *
+ * Copyright 2011 IAR Systems. All rights reserved.
+ *
+ * $Revision: 47876 $
+ *
+ **************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD 0
+ DCD 0
+ DCD 0
+__vector_table_0x1c
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD SVC_Handler
+ DCD 0
+ DCD 0
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+
+ ; External Interrupts
+ DCD SPI0_IRQHandler ; SPI0 controller
+ DCD SPI1_IRQHandler ; SPI1 controller
+ DCD 0 ; Reserved
+ DCD UART0_IRQHandler ; UART0
+ DCD UART1_IRQHandler ; UART1
+ DCD UART2_IRQHandler ; UART2
+ DCD 0 ; Reserved
+ DCD I2C1_IRQHandler ; I2C1 controller
+ DCD I2C0_IRQHandler ; I2C0 controller
+ DCD SCT_IRQHandler ; Smart Counter Timer
+ DCD MRT_IRQHandler ; Multi-Rate Timer
+ DCD CMP_IRQHandler ; Comparator
+ DCD WDT_IRQHandler ; PIO1 (0:11)
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD Flash_IRQHandler ; Flash interrupt
+ DCD WKT_IRQHandler ; Wakeup timer
+ DCD ADC_SEQA_IRQHandler ; ADC sequence A completion
+ DCD ADC_SEQB_IRQHandler ; ADC sequence B completion
+ DCD ADC_THCMP_IRQHandler ; ADC threshold compare
+ DCD ADC_OVR_IRQHandler ; ADC overrun
+ DCD DMA__RQHandler ; DMA interrupt
+ DCD I2C2_IRQHandler ; I2C2 controller
+ DCD I2C3_IRQHandler ; I2C3 controller
+ DCD 0 ; Reserved
+ DCD PININT0_IRQHandler ; PIO INT0
+ DCD PININT1_IRQHandler ; PIO INT1
+ DCD PININT2_IRQHandler ; PIO INT2
+ DCD PININT3_IRQHandler ; PIO INT3
+ DCD PININT4_IRQHandler ; PIO INT4
+ DCD PININT5_IRQHandler ; PIO INT5
+ DCD PININT6_IRQHandler ; PIO INT6
+ DCD PININT7_IRQHandler ; PIO INT7
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK SPI0_IRQHandler
+ PUBWEAK SPI1_IRQHandler
+ PUBWEAK UART0_IRQHandler
+ PUBWEAK UART1_IRQHandler
+ PUBWEAK UART2_IRQHandler
+ PUBWEAK I2C1_IRQHandler
+ PUBWEAK I2C0_IRQHandler
+ PUBWEAK SCT_IRQHandler
+ PUBWEAK MRT_IRQHandler
+ PUBWEAK CMP_IRQHandler
+ PUBWEAK WDT_IRQHandler
+ PUBWEAK BOD_IRQHandler
+ PUBWEAK Flash_IRQHandler
+ PUBWEAK WKT_IRQHandler
+ PUBWEAK ADC_SEQA_IRQHandler
+ PUBWEAK ADC_SEQB_IRQHandler
+ PUBWEAK ADC_THCMP_IRQHandler
+ PUBWEAK ADC_OVR_IRQHandler
+ PUBWEAK DMA__RQHandler
+ PUBWEAK I2C2_IRQHandler
+ PUBWEAK I2C3_IRQHandler
+ PUBWEAK PININT0_IRQHandler
+ PUBWEAK PININT1_IRQHandler
+ PUBWEAK PININT2_IRQHandler
+ PUBWEAK PININT3_IRQHandler
+ PUBWEAK PININT4_IRQHandler
+ PUBWEAK PININT5_IRQHandler
+ PUBWEAK PININT6_IRQHandler
+ PUBWEAK PININT7_IRQHandler
+
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ THUMB
+
+NMI_Handler
+HardFault_Handler
+SVC_Handler
+PendSV_Handler
+SysTick_Handler
+SPI0_IRQHandler
+SPI1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+I2C1_IRQHandler
+I2C0_IRQHandler
+SCT_IRQHandler
+MRT_IRQHandler
+CMP_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+Flash_IRQHandler
+WKT_IRQHandler
+ADC_SEQA_IRQHandler
+ADC_SEQB_IRQHandler
+ADC_THCMP_IRQHandler
+ADC_OVR_IRQHandler
+DMA__RQHandler
+I2C2_IRQHandler
+I2C3_IRQHandler
+PININT0_IRQHandler
+PININT1_IRQHandler
+PININT2_IRQHandler
+PININT3_IRQHandler
+PININT4_IRQHandler
+PININT5_IRQHandler
+PININT6_IRQHandler
+PININT7_IRQHandler
+Default_IRQHandler
+ B Default_IRQHandler
+
+ SECTION .crp:CODE:ROOT(2)
+ DATA
+/* Code Read Protection
+NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode
+CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
+ - Copy RAM to flash command can not write to Sector 0.
+ - Erase command can erase Sector 0 only when all sectors
+ are selected for erase.
+ - Compare command is disabled.
+ - Read Memory command is disabled.
+CRP2 0x87654321 - Read Memory is disabled.
+ - Write to RAM is disabled.
+ - "Go" command is disabled.
+ - Copy RAM to flash is disabled.
+ - Compare is disabled.
+CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
+ by pulling PIO0_1 LOW is disabled if a valid user code is
+ present in flash sector 0.
+Caution: If CRP3 is selected, no future factory testing can be
+performed on the device.
+*/
+ DCD 0xFFFFFFFF
+
+ END
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/system_LPC8xx.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/system_LPC8xx.c
new file mode 100644
index 0000000000..3deb912eb7
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/system_LPC8xx.c
@@ -0,0 +1,389 @@
+/******************************************************************************
+ * @file: system_LPC8xx.c
+ * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Source File
+ * for the NXP LPC8xx Device Series
+ * @version: V1.0
+ * @date: 16. Aug. 2012
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2012 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#include <stdint.h>
+#include "LPC82x.h"
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- Clock Configuration ----------------------------------*/
+//
+// <e> Clock Configuration
+#define CLOCK_SETUP 1
+// <h> System Oscillator Control Register (SYSOSCCTRL)
+// <o.0> BYPASS: System Oscillator Bypass Enable
+// <i> If enabled then PLL input (sys_osc_clk) is fed
+// <i> directly from XTALIN and XTALOUT pins.
+// <o.1> FREQRANGE: System Oscillator Frequency Range
+// <i> Determines frequency range for Low-power oscillator.
+// <0=> 1 - 20 MHz
+// <1=> 15 - 25 MHz
+// </h>
+#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
+//
+// <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
+// <o.0..4> DIVSEL: Select Divider for Fclkana
+// <i> wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL))
+// <0-31>
+// <o.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
+// <0=> Undefined
+// <1=> 0.6 MHz
+// <2=> 1.05 MHz
+// <3=> 1.4 MHz
+// <4=> 1.75 MHz
+// <5=> 2.1 MHz
+// <6=> 2.4 MHz
+// <7=> 2.7 MHz
+// <8=> 3.0 MHz
+// <9=> 3.25 MHz
+// <10=> 3.5 MHz
+// <11=> 3.75 MHz
+// <12=> 4.0 MHz
+// <13=> 4.2 MHz
+// <14=> 4.4 MHz
+// <15=> 4.6 MHz
+#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
+// </h>
+// <h> System PLL Control Register (SYSPLLCTRL)
+// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
+// <i> F_clkin must be in the range of 10 MHz to 25 MHz
+// <i> F_CCO must be in the range of 156 MHz to 320 MHz
+// <o.0..4> MSEL: Feedback Divider Selection
+// <i> M = MSEL + 1
+// <0-31>
+// <o.5..6> PSEL: Post Divider Selection
+// <0=> P = 1
+// <1=> P = 2
+// <2=> P = 4
+// <3=> P = 8
+// </h>
+#define SYSPLLCTRL_Val 0x00000024 // Reset: 0x000
+//
+// <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
+// <o.0..1> SEL: System PLL Clock Source
+// <0=> IRC
+// <1=> Crystal Oscillator
+// <2=> Reserved
+// <3=> CLKIN. External clock input.
+// </h>
+#define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000
+//
+// <h> Main Clock Source Select Register (MAINCLKSEL)
+// <o.0..1> SEL: Clock Source for Main Clock
+// <0=> IRC Oscillator
+// <1=> PLL input
+// <2=> Watchdog Oscillator
+// <3=> PLL output
+// </h>
+#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
+// <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
+// <o.0..7> DIV: System AHB Clock Divider
+// <i> Divides main clock to provide system clock to core, memories, and peripherals.
+// <i> 0 = is disabled
+// <0-255>
+// </h>
+#define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001
+// </e>
+
+//#define CLOCK_SETUP 0 // 1 == IRC: 2 == System Oscillator 12Mhz Xtal:
+
+/*
+#if (CLOCK_SETUP == 0)
+ #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
+ #define WDTOSCCTRL_Val 0x00000024 // Reset: 0x000
+ #define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000
+ #define SYSPLLCLKSEL_Val 0x00000003 // Reset: 0x000
+ #define MAINCLKSEL_Val 0x00000000 // Reset: 0x000
+ #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
+#elif (CLOCK_SETUP == 2)
+// #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
+ #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
+ #define SYSPLLCTRL_Val 0x00000040 // Reset: 0x000
+ #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
+ #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
+ #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
+#endif
+*/
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+/*----------------------------------------------------------------------------
+ Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask) (val & mask)
+
+/* Clock Configuration -------------------------------------------------------*/
+#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
+ #error "SYSOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
+ #error "WDTOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
+ #error "SYSPLLCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
+ #error "SYSPLLCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
+ #error "MAINCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
+ #error "SYSAHBCLKDIV: Value out of range!"
+#endif
+
+
+/*----------------------------------------------------------------------------
+ DEFINES
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define __XTAL (12000000UL) /* Oscillator frequency */
+#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
+#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
+#define __CLKIN_CLK (12000000UL) /* CLKIN pin frequency */
+
+
+#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
+#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
+
+#if (CLOCK_SETUP) /* Clock Setup */
+ #if (__FREQSEL == 0)
+ #define __WDT_OSC_CLK ( 0) /* undefined */
+ #elif (__FREQSEL == 1)
+ #define __WDT_OSC_CLK ( 500000 / __DIVSEL)
+ #elif (__FREQSEL == 2)
+ #define __WDT_OSC_CLK ( 800000 / __DIVSEL)
+ #elif (__FREQSEL == 3)
+ #define __WDT_OSC_CLK (1100000 / __DIVSEL)
+ #elif (__FREQSEL == 4)
+ #define __WDT_OSC_CLK (1400000 / __DIVSEL)
+ #elif (__FREQSEL == 5)
+ #define __WDT_OSC_CLK (1600000 / __DIVSEL)
+ #elif (__FREQSEL == 6)
+ #define __WDT_OSC_CLK (1800000 / __DIVSEL)
+ #elif (__FREQSEL == 7)
+ #define __WDT_OSC_CLK (2000000 / __DIVSEL)
+ #elif (__FREQSEL == 8)
+ #define __WDT_OSC_CLK (2200000 / __DIVSEL)
+ #elif (__FREQSEL == 9)
+ #define __WDT_OSC_CLK (2400000 / __DIVSEL)
+ #elif (__FREQSEL == 10)
+ #define __WDT_OSC_CLK (2600000 / __DIVSEL)
+ #elif (__FREQSEL == 11)
+ #define __WDT_OSC_CLK (2700000 / __DIVSEL)
+ #elif (__FREQSEL == 12)
+ #define __WDT_OSC_CLK (2900000 / __DIVSEL)
+ #elif (__FREQSEL == 13)
+ #define __WDT_OSC_CLK (3100000 / __DIVSEL)
+ #elif (__FREQSEL == 14)
+ #define __WDT_OSC_CLK (3200000 / __DIVSEL)
+ #else
+ #define __WDT_OSC_CLK (3400000 / __DIVSEL)
+ #endif
+
+ /* sys_pllclkin calculation */
+ #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
+ #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
+ #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
+ #elif ((SYSPLLCLKSEL_Val & 0x03) == 3)
+ #define __SYS_PLLCLKIN (__CLKIN_CLK)
+ #else
+ #define __SYS_PLLCLKIN (0)
+ #endif
+
+ #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
+
+ /* main clock calculation */
+ #if ((MAINCLKSEL_Val & 0x03) == 0)
+ #define __MAIN_CLOCK (__IRC_OSC_CLK)
+ #elif ((MAINCLKSEL_Val & 0x03) == 1)
+ #define __MAIN_CLOCK (__SYS_PLLCLKIN)
+ #elif ((MAINCLKSEL_Val & 0x03) == 2)
+ #if (__FREQSEL == 0)
+ #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
+ #else
+ #define __MAIN_CLOCK (__WDT_OSC_CLK)
+ #endif
+ #elif ((MAINCLKSEL_Val & 0x03) == 3)
+ #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
+ #else
+ #define __MAIN_CLOCK (0)
+ #endif
+
+ #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
+
+#else
+ #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
+#endif // CLOCK_SETUP
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
+uint32_t MainClock = __MAIN_CLOCK; /*!< Main Clock Frequency */
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+ uint32_t wdt_osc = 0;
+
+ /* Determine clock frequency according to clock register values */
+ switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
+ case 0: wdt_osc = 0; break;
+ case 1: wdt_osc = 500000; break;
+ case 2: wdt_osc = 800000; break;
+ case 3: wdt_osc = 1100000; break;
+ case 4: wdt_osc = 1400000; break;
+ case 5: wdt_osc = 1600000; break;
+ case 6: wdt_osc = 1800000; break;
+ case 7: wdt_osc = 2000000; break;
+ case 8: wdt_osc = 2200000; break;
+ case 9: wdt_osc = 2400000; break;
+ case 10: wdt_osc = 2600000; break;
+ case 11: wdt_osc = 2700000; break;
+ case 12: wdt_osc = 2900000; break;
+ case 13: wdt_osc = 3100000; break;
+ case 14: wdt_osc = 3200000; break;
+ case 15: wdt_osc = 3400000; break;
+ }
+ wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
+
+ switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* Input Clock to System PLL */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* System oscillator */
+ SystemCoreClock = __SYS_OSC_CLK;
+ break;
+ case 2: /* Reserved */
+ SystemCoreClock = 0;
+ break;
+ case 3: /* CLKIN pin */
+ SystemCoreClock = __CLKIN_CLK;
+ break;
+ }
+ break;
+ case 2: /* WDT Oscillator */
+ SystemCoreClock = wdt_osc;
+ break;
+ case 3: /* System PLL Clock Out */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ break;
+ case 1: /* System oscillator */
+ SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ break;
+ case 2: /* Reserved */
+ SystemCoreClock = 0;
+ break;
+ case 3: /* CLKIN pin */
+ SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ break;
+ }
+ break;
+ }
+
+ SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void) {
+
+ /* System clock to the IOCON & the SWM need to be enabled or
+ most of the I/O related peripherals won't work. */
+ LPC_SYSCON->SYSAHBCLKCTRL |= ( (0x1 << 7) | (0x1 << 18) );
+
+#if (CLOCK_SETUP) /* Clock Setup */
+
+#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ volatile uint32_t i;
+ LPC_IOCON->PIO0_8 &= ~(0x3 << 3);
+ LPC_IOCON->PIO0_9 &= ~(0x3 << 3);
+ LPC_SWM->PINENABLE0 &= ~(0x3 << 6); /* XTALIN and XTALOUT */
+ LPC_SYSCON->PDRUNCFG &= ~(0x1 << 5); /* Power-up System Osc */
+ for (i = 0; i < 200; i++) __NOP();
+ LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
+#endif
+
+#if ((SYSPLLCLKSEL_Val & 0x03) == 3)
+ LPC_IOCON->PIO0_1 &= ~(0x3 << 3);
+ LPC_SWM->PINENABLE0 &= ~(0x1 << 9); /* CLKIN */
+ for (i = 0; i < 200; i++) __NOP();
+#endif
+
+ LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up System PLL */
+ LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
+ LPC_SYSCON->SYSPLLCLKUEN = 0;
+ LPC_SYSCON->SYSPLLCLKUEN = 1; /* Update Clock Source */
+ while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
+
+#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
+ LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up SYSPLL */
+ while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
+#endif
+
+#if (((MAINCLKSEL_Val & 0x03) == 2) )
+ LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(0x1 << 6); /* Power-up WDT Clock */
+ for (i = 0; i < 200; i++) __NOP();
+#endif
+
+ LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
+ LPC_SYSCON->MAINCLKUEN = 0;
+ LPC_SYSCON->MAINCLKUEN = 1; /* Update MCLK Clock Source */
+ while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
+
+ LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
+#endif
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_ARM_MICRO/LPC824.sct b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_ARM_MICRO/LPC824.sct
new file mode 100644
index 0000000000..310aa82197
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_ARM_MICRO/LPC824.sct
@@ -0,0 +1,14 @@
+
+LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
+ ER_IROM1 0x00000000 0x8000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0x1F40
+ RW_IRAM1 0x10000000+0xC0 0x2000-0xC0 {
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s
new file mode 100644
index 0000000000..a90d8d290e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s
@@ -0,0 +1,218 @@
+;/*****************************************************************************
+; * @file: startup_LPC8xx.s
+; * @purpose: CMSIS Cortex-M0+ Core Device Startup File
+; * for the NXP LPC8xx Device Series
+; * @version: V1.0
+; * @date: 16. Aug. 2012
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2012 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+__initial_sp EQU 0x10002000
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD SPI0_IRQHandler ; SPI0 controller
+ DCD SPI1_IRQHandler ; SPI1 controller
+ DCD 0 ; Reserved
+ DCD UART0_IRQHandler ; UART0
+ DCD UART1_IRQHandler ; UART1
+ DCD UART2_IRQHandler ; UART2
+ DCD 0 ; Reserved
+ DCD I2C1_IRQHandler ; I2C1 controller
+ DCD I2C0_IRQHandler ; I2C0 controller
+ DCD SCT_IRQHandler ; Smart Counter Timer
+ DCD MRT_IRQHandler ; Multi-Rate Timer
+ DCD CMP_IRQHandler ; Comparator
+ DCD WDT_IRQHandler ; PIO1 (0:11)
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD Flash_IRQHandler ; Flash interrupt
+ DCD WKT_IRQHandler ; Wakeup timer
+ DCD ADC_SEQA_IRQHandler ; ADC sequence A completion
+ DCD ADC_SEQB_IRQHandler ; ADC sequence B completion
+ DCD ADC_THCMP_IRQHandler ; ADC threshold compare
+ DCD ADC_OVR_IRQHandler ; ADC overrun
+ DCD DMA__RQHandler ; DMA interrupt
+ DCD I2C2_IRQHandler ; I2C2 controller
+ DCD I2C3_IRQHandler ; I2C3 controller
+ DCD 0 ; Reserved
+ DCD PININT0_IRQHandler ; PIO INT0
+ DCD PININT1_IRQHandler ; PIO INT1
+ DCD PININT2_IRQHandler ; PIO INT2
+ DCD PININT3_IRQHandler ; PIO INT3
+ DCD PININT4_IRQHandler ; PIO INT4
+ DCD PININT5_IRQHandler ; PIO INT5
+ DCD PININT6_IRQHandler ; PIO INT6
+ DCD PININT7_IRQHandler ; PIO INT7
+
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT NMI_Handler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT SCT_IRQHandler [WEAK]
+ EXPORT MRT_IRQHandler [WEAK]
+ EXPORT CMP_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT Flash_IRQHandler [WEAK]
+ EXPORT WKT_IRQHandler [WEAK]
+ EXPORT ADC_SEQA_IRQHandler [WEAK]
+ EXPORT ADC_SEQB_IRQHandler [WEAK]
+ EXPORT ADC_THCMP_IRQHandler [WEAK]
+ EXPORT ADC_OVR_IRQHandler [WEAK]
+ EXPORT DMA__RQHandler [WEAK]
+ EXPORT I2C2_IRQHandler [WEAK]
+ EXPORT I2C3_IRQHandler [WEAK]
+ EXPORT PININT0_IRQHandler [WEAK]
+ EXPORT PININT1_IRQHandler [WEAK]
+ EXPORT PININT2_IRQHandler [WEAK]
+ EXPORT PININT3_IRQHandler [WEAK]
+ EXPORT PININT4_IRQHandler [WEAK]
+ EXPORT PININT5_IRQHandler [WEAK]
+ EXPORT PININT6_IRQHandler [WEAK]
+ EXPORT PININT7_IRQHandler [WEAK]
+
+NMI_Handler
+SPI0_IRQHandler
+SPI1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+I2C1_IRQHandler
+I2C0_IRQHandler
+SCT_IRQHandler
+MRT_IRQHandler
+CMP_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+Flash_IRQHandler
+WKT_IRQHandler
+ADC_SEQA_IRQHandler
+ADC_SEQB_IRQHandler
+ADC_THCMP_IRQHandler
+ADC_OVR_IRQHandler
+DMA__RQHandler
+I2C2_IRQHandler
+I2C3_IRQHandler
+PININT0_IRQHandler
+PININT1_IRQHandler
+PININT2_IRQHandler
+PININT3_IRQHandler
+PININT4_IRQHandler
+PININT5_IRQHandler
+PININT6_IRQHandler
+PININT7_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_GCC_ARM/LPC824.ld b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_GCC_ARM/LPC824.ld
new file mode 100644
index 0000000000..be901736a7
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_GCC_ARM/LPC824.ld
@@ -0,0 +1,152 @@
+/* Linker script for mbed LPC824-GCC-ARM based on LPC1114-GCC-ARM-LPC1114.ld */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ /* Define each memory region */
+ FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x8000 /* 32K bytes */
+ RAM (rwx) : ORIGIN = 0x10000000+0xC0, LENGTH = 0x2000-0xC0 /* 8K bytes */
+
+
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text.Reset_Handler)
+ *(.text.SystemInit)
+ . = 0x200;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_GCC_ARM/startup_LPC824.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_GCC_ARM/startup_LPC824.s
new file mode 100644
index 0000000000..c4273d680b
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_GCC_ARM/startup_LPC824.s
@@ -0,0 +1,228 @@
+/* File: startup_ARMCM0.S
+ * Purpose: startup file for Cortex-M0 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V1.2
+ * Date: 15 Nov 2011
+ *
+ * Copyright (c) 2011, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of the ARM Limited nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ .syntax unified
+ .arch armv6-m
+
+/* Memory Model
+ The HEAP starts at the end of the DATA section and grows upward.
+
+ The STACK starts at the end of the RAM and grows downward.
+
+ The HEAP and stack STACK are only checked at compile time:
+ (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+
+ This is just a check for the bare minimum for the Heap+Stack area before
+ aborting compilation, it is not the run time limit:
+ Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x80
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x80
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+/* LPC824 interrupts */
+ .long SPI0_IRQHandler // SPI0 controller
+ .long SPI1_IRQHandler // SPI1 controller
+ .long 0 // Reserved
+ .long UART0_IRQHandler // UART0
+ .long UART1_IRQHandler // UART1
+ .long UART2_IRQHandler // UART2
+ .long 0 // Reserved
+ .long I2C1_IRQHandler // I2C ch1 controller
+ .long I2C0_IRQHandler // I2C ch0 controller
+ .long SCT_IRQHandler // Smart Counter Timer
+ .long MRT_IRQHandler // Multi-Rate Timer
+ .long CMP_IRQHandler // Comparator
+ .long WDT_IRQHandler // PIO1 (0:11)
+ .long BOD_IRQHandler // Brown Out Detect
+ .long Flash_IRQHandler // Flash interrupt
+ .long WKT_IRQHandler // Wakeup timer
+ .long ADC_SEQA_IRQHandler // ADC sequence A completion
+ .long ADC_SEQB_IRQHandler // ADC sequence B completion
+ .long ADC_THCMP_IRQHandler // ADC threshold compare
+ .long ADC_OVR_IRQHandler // ADC overrun
+ .long DMA_IRQHandler // DMA interrupt
+ .long I2C2_IRQHandler // I2C2 controller
+ .long I2C3_IRQHandler // I2C3 controller
+ .long 0 // Reserved
+ .long PININT0_IRQHandler // PIO INT0
+ .long PININT1_IRQHandler // PIO INT1
+ .long PININT2_IRQHandler // PIO INT2
+ .long PININT3_IRQHandler // PIO INT3
+ .long PININT4_IRQHandler // PIO INT4
+ .long PININT5_IRQHandler // PIO INT5
+ .long PININT6_IRQHandler // PIO INT6
+ .long PININT7_IRQHandler // PIO INT7
+
+ .size __isr_vector, . - __isr_vector
+
+ .section .text.Reset_Handler
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .Lflash_to_ram_loop_end
+
+ movs r4, 0
+.Lflash_to_ram_loop:
+ ldr r0, [r1,r4]
+ str r0, [r2,r4]
+ adds r4, 4
+ cmp r4, r3
+ blt .Lflash_to_ram_loop
+.Lflash_to_ram_loop_end:
+
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_default_handler SPI0_IRQHandler
+ def_irq_default_handler SPI1_IRQHandler
+ def_irq_default_handler UART0_IRQHandler
+ def_irq_default_handler UART1_IRQHandler
+ def_irq_default_handler UART2_IRQHandler
+ def_irq_default_handler I2C0_IRQHandler
+ def_irq_default_handler I2C1_IRQHandler
+ def_irq_default_handler I2C2_IRQHandler
+ def_irq_default_handler I2C3_IRQHandler
+ def_irq_default_handler SCT_IRQHandler
+ def_irq_default_handler MRT_IRQHandler
+ def_irq_default_handler CMP_IRQHandler
+ def_irq_default_handler WDT_IRQHandler
+ def_irq_default_handler BOD_IRQHandler
+ def_irq_default_handler Flash_IRQHandler
+ def_irq_default_handler WKT_IRQHandler
+ def_irq_default_handler ADC_SEQA_IRQHandler
+ def_irq_default_handler ADC_SEQB_IRQHandler
+ def_irq_default_handler ADC_THCMP_IRQHandler
+ def_irq_default_handler ADC_OVR_IRQHandler
+ def_irq_default_handler DMA_IRQHandler
+ def_irq_default_handler PININT0_IRQHandler
+ def_irq_default_handler PININT1_IRQHandler
+ def_irq_default_handler PININT2_IRQHandler
+ def_irq_default_handler PININT3_IRQHandler
+ def_irq_default_handler PININT4_IRQHandler
+ def_irq_default_handler PININT5_IRQHandler
+ def_irq_default_handler PININT6_IRQHandler
+ def_irq_default_handler PININT7_IRQHandler
+
+ .end
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/system_LPC8xx.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/system_LPC8xx.c
new file mode 100644
index 0000000000..e2b4123499
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/system_LPC8xx.c
@@ -0,0 +1,389 @@
+/******************************************************************************
+ * @file: system_LPC8xx.c
+ * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Source File
+ * for the NXP LPC8xx Device Series
+ * @version: V1.0
+ * @date: 16. Aug. 2012
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2012 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#include <stdint.h>
+#include "LPC82x.h"
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- Clock Configuration ----------------------------------*/
+//
+// <e> Clock Configuration
+#define CLOCK_SETUP 1
+// <h> System Oscillator Control Register (SYSOSCCTRL)
+// <o.0> BYPASS: System Oscillator Bypass Enable
+// <i> If enabled then PLL input (sys_osc_clk) is fed
+// <i> directly from XTALIN and XTALOUT pins.
+// <o.1> FREQRANGE: System Oscillator Frequency Range
+// <i> Determines frequency range for Low-power oscillator.
+// <0=> 1 - 20 MHz
+// <1=> 15 - 25 MHz
+// </h>
+#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
+//
+// <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
+// <o.0..4> DIVSEL: Select Divider for Fclkana
+// <i> wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL))
+// <0-31>
+// <o.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
+// <0=> Undefined
+// <1=> 0.6 MHz
+// <2=> 1.05 MHz
+// <3=> 1.4 MHz
+// <4=> 1.75 MHz
+// <5=> 2.1 MHz
+// <6=> 2.4 MHz
+// <7=> 2.7 MHz
+// <8=> 3.0 MHz
+// <9=> 3.25 MHz
+// <10=> 3.5 MHz
+// <11=> 3.75 MHz
+// <12=> 4.0 MHz
+// <13=> 4.2 MHz
+// <14=> 4.4 MHz
+// <15=> 4.6 MHz
+#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
+// </h>
+// <h> System PLL Control Register (SYSPLLCTRL)
+// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
+// <i> F_clkin must be in the range of 10 MHz to 25 MHz
+// <i> F_CCO must be in the range of 156 MHz to 320 MHz
+// <o.0..4> MSEL: Feedback Divider Selection
+// <i> M = MSEL + 1
+// <0-31>
+// <o.5..6> PSEL: Post Divider Selection
+// <0=> P = 1
+// <1=> P = 2
+// <2=> P = 4
+// <3=> P = 8
+// </h>
+#define SYSPLLCTRL_Val 0x00000024 // Reset: 0x000
+//
+// <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
+// <o.0..1> SEL: System PLL Clock Source
+// <0=> IRC
+// <1=> Crystal Oscillator
+// <2=> Reserved
+// <3=> CLKIN. External clock input.
+// </h>
+#define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
+//
+// <h> Main Clock Source Select Register (MAINCLKSEL)
+// <o.0..1> SEL: Clock Source for Main Clock
+// <0=> IRC Oscillator
+// <1=> PLL input
+// <2=> Watchdog Oscillator
+// <3=> PLL output
+// </h>
+#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
+// <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
+// <o.0..7> DIV: System AHB Clock Divider
+// <i> Divides main clock to provide system clock to core, memories, and peripherals.
+// <i> 0 = is disabled
+// <0-255>
+// </h>
+#define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001
+// </e>
+
+//#define CLOCK_SETUP 0 // 1 == IRC: 2 == System Oscillator 12Mhz Xtal:
+
+/*
+#if (CLOCK_SETUP == 0)
+ #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
+ #define WDTOSCCTRL_Val 0x00000024 // Reset: 0x000
+ #define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000
+ #define SYSPLLCLKSEL_Val 0x00000003 // Reset: 0x000
+ #define MAINCLKSEL_Val 0x00000000 // Reset: 0x000
+ #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
+#elif (CLOCK_SETUP == 2)
+// #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
+ #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
+ #define SYSPLLCTRL_Val 0x00000040 // Reset: 0x000
+ #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
+ #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
+ #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
+#endif
+*/
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+/*----------------------------------------------------------------------------
+ Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask) (val & mask)
+
+/* Clock Configuration -------------------------------------------------------*/
+#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
+ #error "SYSOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
+ #error "WDTOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
+ #error "SYSPLLCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
+ #error "SYSPLLCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
+ #error "MAINCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
+ #error "SYSAHBCLKDIV: Value out of range!"
+#endif
+
+
+/*----------------------------------------------------------------------------
+ DEFINES
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define __XTAL (12000000UL) /* Oscillator frequency */
+#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
+#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
+#define __CLKIN_CLK (12000000UL) /* CLKIN pin frequency */
+
+
+#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
+#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
+
+#if (CLOCK_SETUP) /* Clock Setup */
+ #if (__FREQSEL == 0)
+ #define __WDT_OSC_CLK ( 0) /* undefined */
+ #elif (__FREQSEL == 1)
+ #define __WDT_OSC_CLK ( 500000 / __DIVSEL)
+ #elif (__FREQSEL == 2)
+ #define __WDT_OSC_CLK ( 800000 / __DIVSEL)
+ #elif (__FREQSEL == 3)
+ #define __WDT_OSC_CLK (1100000 / __DIVSEL)
+ #elif (__FREQSEL == 4)
+ #define __WDT_OSC_CLK (1400000 / __DIVSEL)
+ #elif (__FREQSEL == 5)
+ #define __WDT_OSC_CLK (1600000 / __DIVSEL)
+ #elif (__FREQSEL == 6)
+ #define __WDT_OSC_CLK (1800000 / __DIVSEL)
+ #elif (__FREQSEL == 7)
+ #define __WDT_OSC_CLK (2000000 / __DIVSEL)
+ #elif (__FREQSEL == 8)
+ #define __WDT_OSC_CLK (2200000 / __DIVSEL)
+ #elif (__FREQSEL == 9)
+ #define __WDT_OSC_CLK (2400000 / __DIVSEL)
+ #elif (__FREQSEL == 10)
+ #define __WDT_OSC_CLK (2600000 / __DIVSEL)
+ #elif (__FREQSEL == 11)
+ #define __WDT_OSC_CLK (2700000 / __DIVSEL)
+ #elif (__FREQSEL == 12)
+ #define __WDT_OSC_CLK (2900000 / __DIVSEL)
+ #elif (__FREQSEL == 13)
+ #define __WDT_OSC_CLK (3100000 / __DIVSEL)
+ #elif (__FREQSEL == 14)
+ #define __WDT_OSC_CLK (3200000 / __DIVSEL)
+ #else
+ #define __WDT_OSC_CLK (3400000 / __DIVSEL)
+ #endif
+
+ /* sys_pllclkin calculation */
+ #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
+ #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
+ #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
+ #elif ((SYSPLLCLKSEL_Val & 0x03) == 3)
+ #define __SYS_PLLCLKIN (__CLKIN_CLK)
+ #else
+ #define __SYS_PLLCLKIN (0)
+ #endif
+
+ #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
+
+ /* main clock calculation */
+ #if ((MAINCLKSEL_Val & 0x03) == 0)
+ #define __MAIN_CLOCK (__IRC_OSC_CLK)
+ #elif ((MAINCLKSEL_Val & 0x03) == 1)
+ #define __MAIN_CLOCK (__SYS_PLLCLKIN)
+ #elif ((MAINCLKSEL_Val & 0x03) == 2)
+ #if (__FREQSEL == 0)
+ #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
+ #else
+ #define __MAIN_CLOCK (__WDT_OSC_CLK)
+ #endif
+ #elif ((MAINCLKSEL_Val & 0x03) == 3)
+ #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
+ #else
+ #define __MAIN_CLOCK (0)
+ #endif
+
+ #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
+
+#else
+ #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
+#endif // CLOCK_SETUP
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
+uint32_t MainClock = __MAIN_CLOCK; /*!< Main Clock Frequency */
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+ uint32_t wdt_osc = 0;
+
+ /* Determine clock frequency according to clock register values */
+ switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
+ case 0: wdt_osc = 0; break;
+ case 1: wdt_osc = 500000; break;
+ case 2: wdt_osc = 800000; break;
+ case 3: wdt_osc = 1100000; break;
+ case 4: wdt_osc = 1400000; break;
+ case 5: wdt_osc = 1600000; break;
+ case 6: wdt_osc = 1800000; break;
+ case 7: wdt_osc = 2000000; break;
+ case 8: wdt_osc = 2200000; break;
+ case 9: wdt_osc = 2400000; break;
+ case 10: wdt_osc = 2600000; break;
+ case 11: wdt_osc = 2700000; break;
+ case 12: wdt_osc = 2900000; break;
+ case 13: wdt_osc = 3100000; break;
+ case 14: wdt_osc = 3200000; break;
+ case 15: wdt_osc = 3400000; break;
+ }
+ wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
+
+ switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* Input Clock to System PLL */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* System oscillator */
+ SystemCoreClock = __SYS_OSC_CLK;
+ break;
+ case 2: /* Reserved */
+ SystemCoreClock = 0;
+ break;
+ case 3: /* CLKIN pin */
+ SystemCoreClock = __CLKIN_CLK;
+ break;
+ }
+ break;
+ case 2: /* WDT Oscillator */
+ SystemCoreClock = wdt_osc;
+ break;
+ case 3: /* System PLL Clock Out */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ break;
+ case 1: /* System oscillator */
+ SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ break;
+ case 2: /* Reserved */
+ SystemCoreClock = 0;
+ break;
+ case 3: /* CLKIN pin */
+ SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ break;
+ }
+ break;
+ }
+
+ SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void) {
+ volatile uint32_t i;
+
+ /* System clock to the IOCON & the SWM need to be enabled or
+ most of the I/O related peripherals won't work. */
+ LPC_SYSCON->SYSAHBCLKCTRL |= ( (0x1 << 7) | (0x1 << 18) );
+
+#if (CLOCK_SETUP) /* Clock Setup */
+
+#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ LPC_IOCON->PIO0_8 &= ~(0x3 << 3);
+ LPC_IOCON->PIO0_9 &= ~(0x3 << 3);
+ LPC_SWM->PINENABLE0 &= ~(0x3 << 6); /* XTALIN and XTALOUT */
+ LPC_SYSCON->PDRUNCFG &= ~(0x1 << 5); /* Power-up System Osc */
+ for (i = 0; i < 200; i++) __NOP();
+ LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
+#endif
+
+#if ((SYSPLLCLKSEL_Val & 0x03) == 3)
+ LPC_IOCON->PIO0_1 &= ~(0x3 << 3);
+ LPC_SWM->PINENABLE0 &= ~(0x1 << 9); /* CLKIN */
+ for (i = 0; i < 200; i++) __NOP();
+#endif
+
+ LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up System PLL */
+ LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
+ LPC_SYSCON->SYSPLLCLKUEN = 0;
+ LPC_SYSCON->SYSPLLCLKUEN = 1; /* Update Clock Source */
+ while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
+
+#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
+ LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up SYSPLL */
+ while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
+#endif
+
+#if (((MAINCLKSEL_Val & 0x03) == 2) )
+ LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(0x1 << 6); /* Power-up WDT Clock */
+ for (i = 0; i < 200; i++) __NOP();
+#endif
+
+ LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
+ LPC_SYSCON->MAINCLKUEN = 0;
+ LPC_SYSCON->MAINCLKUEN = 1; /* Update MCLK Clock Source */
+ while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
+
+ LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
+#endif
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TOOLCHAIN_ARM_MICRO/sys.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TOOLCHAIN_ARM_MICRO/sys.cpp
new file mode 100644
index 0000000000..2f1024ace8
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TOOLCHAIN_ARM_MICRO/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis.h
new file mode 100644
index 0000000000..dc68e39335
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC8xx specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "LPC82x.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis_nvic.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis_nvic.c
new file mode 100644
index 0000000000..ee0e4a7186
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis_nvic.c
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis_nvic.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis_nvic.h
new file mode 100644
index 0000000000..64f36b3167
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis_nvic.h
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/system_LPC82x.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/system_LPC82x.h
new file mode 100644
index 0000000000..a80f832909
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/system_LPC82x.h
@@ -0,0 +1,63 @@
+/******************************************************************************
+ * @file: system_LPC8xx.h
+ * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Header File
+ * for the NXP LPC8xx Device Series
+ * @version: V1.0
+ * @date: 16. Aug. 2012
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2012 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC8xx_H
+#define __SYSTEM_LPC8xx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+extern uint32_t MainClock; /*!< Main Clock Frequency */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC8xx_H */