diff options
Diffstat (limited to 'tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_CR/LPC43xx.ld')
| -rw-r--r-- | tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_CR/LPC43xx.ld | 281 |
1 files changed, 281 insertions, 0 deletions
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_CR/LPC43xx.ld b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_CR/LPC43xx.ld new file mode 100644 index 0000000000..12d97fa881 --- /dev/null +++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_CR/LPC43xx.ld @@ -0,0 +1,281 @@ +/* mbed - LPC4330_M4 linker script + * Based linker script generated by Code Red Technologies Red Suite 7.0 + */ +GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o) + +MEMORY +{ + /* Define each memory region */ + RamLoc128 (rwx) : ORIGIN = 0x10000118, LENGTH = 0x1FEE8 /* 128K bytes */ + RamLoc72 (rwx) : ORIGIN = 0x10080000, LENGTH = 0x12000 /* 72K bytes */ + RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes */ + RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes */ + RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes */ + SPIFI (rx) : ORIGIN = 0x14000000, LENGTH = 0x400000 /* 4M bytes */ + + +} + /* Define a symbol for the top of each memory region */ + __top_RamLoc128 = 0x10000000 + 0x20000; + __top_RamLoc72 = 0x10080000 + 0x12000; + __top_RamAHB32 = 0x20000000 + 0x8000; + __top_RamAHB16 = 0x20008000 + 0x4000; + __top_RamAHB_ETB16 = 0x2000c000 + 0x4000; + __top_SPIFI = 0x14000000 + 0x400000; + +ENTRY(ResetISR) + +SECTIONS +{ + + /* MAIN TEXT SECTION */ + .text : ALIGN(4) + { + FILL(0xff) + __vectors_start__ = ABSOLUTE(.) ; + KEEP(*(.isr_vector)) + + /* Global Section Table */ + . = ALIGN(4) ; + __section_table_start = .; + __data_section_table = .; + LONG(LOADADDR(.data)); + LONG( ADDR(.data)); + LONG( SIZEOF(.data)); + LONG(LOADADDR(.data_RAM2)); + LONG( ADDR(.data_RAM2)); + LONG( SIZEOF(.data_RAM2)); + LONG(LOADADDR(.data_RAM3)); + LONG( ADDR(.data_RAM3)); + LONG( SIZEOF(.data_RAM3)); + LONG(LOADADDR(.data_RAM4)); + LONG( ADDR(.data_RAM4)); + LONG( SIZEOF(.data_RAM4)); + LONG(LOADADDR(.data_RAM5)); + LONG( ADDR(.data_RAM5)); + LONG( SIZEOF(.data_RAM5)); + __data_section_table_end = .; + __bss_section_table = .; + LONG( ADDR(.bss)); + LONG( SIZEOF(.bss)); + LONG( ADDR(.bss_RAM2)); + LONG( SIZEOF(.bss_RAM2)); + LONG( ADDR(.bss_RAM3)); + LONG( SIZEOF(.bss_RAM3)); + LONG( ADDR(.bss_RAM4)); + LONG( SIZEOF(.bss_RAM4)); + LONG( ADDR(.bss_RAM5)); + LONG( SIZEOF(.bss_RAM5)); + __bss_section_table_end = .; + __section_table_end = . ; + /* End of Global Section Table */ + + + *(.after_vectors*) + + } >SPIFI + + .text : ALIGN(4) + { + *(.text*) + *(.rodata .rodata.* .constdata .constdata.*) + . = ALIGN(4); + + /* C++ constructors etc */ + . = ALIGN(4); + KEEP(*(.init)) + + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + KEEP(*(.fini)); + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + /* End C++ */ + } > SPIFI + + /* + * for exception handling/unwind - some Newlib functions (in common + * with C++ and STDC++) use this. + */ + .ARM.extab : ALIGN(4) + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > SPIFI + __exidx_start = .; + + .ARM.exidx : ALIGN(4) + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > SPIFI + __exidx_end = .; + + _etext = .; + + + /* DATA section for RamLoc72 */ + .data_RAM2 : ALIGN(4) + { + FILL(0xff) + *(.ramfunc.$RAM2) + *(.ramfunc.$RamLoc72) + *(.data.$RAM2*) + *(.data.$RamLoc72*) + . = ALIGN(4) ; + } > RamLoc72 AT>SPIFI + + /* DATA section for RamAHB32 */ + .data_RAM3 : ALIGN(4) + { + FILL(0xff) + *(.ramfunc.$RAM3) + *(.ramfunc.$RamAHB32) + *(.data.$RAM3*) + *(.data.$RamAHB32*) + . = ALIGN(4) ; + } > RamAHB32 AT>SPIFI + + /* DATA section for RamAHB16 */ + .data_RAM4 : ALIGN(4) + { + FILL(0xff) + *(.ramfunc.$RAM4) + *(.ramfunc.$RamAHB16) + *(.data.$RAM4*) + *(.data.$RamAHB16*) + . = ALIGN(4) ; + } > RamAHB16 AT>SPIFI + + /* DATA section for RamAHB_ETB16 */ + .data_RAM5 : ALIGN(4) + { + FILL(0xff) + *(.ramfunc.$RAM5) + *(.ramfunc.$RamAHB_ETB16) + *(.data.$RAM5*) + *(.data.$RamAHB_ETB16*) + . = ALIGN(4) ; + } > RamAHB_ETB16 AT>SPIFI + + /* MAIN DATA SECTION */ + + + .uninit_RESERVED : ALIGN(4) + { + KEEP(*(.bss.$RESERVED*)) + . = ALIGN(4) ; + _end_uninit_RESERVED = .; + } > RamLoc128 + + + /* Main DATA section (RamLoc128) */ + .data : ALIGN(4) + { + FILL(0xff) + _data = . ; + *(vtable) + *(.ramfunc*) + *(.data*) + . = ALIGN(4) ; + _edata = . ; + } > RamLoc128 AT>SPIFI + + /* BSS section for RamLoc72 */ + .bss_RAM2 : ALIGN(4) + { + *(.bss.$RAM2*) + *(.bss.$RamLoc72*) + . = ALIGN(4) ; + } > RamLoc72 + /* BSS section for RamAHB32 */ + .bss_RAM3 : ALIGN(4) + { + *(.bss.$RAM3*) + *(.bss.$RamAHB32*) + . = ALIGN(4) ; + } > RamAHB32 + /* BSS section for RamAHB16 */ + .bss_RAM4 : ALIGN(4) + { + *(.bss.$RAM4*) + *(.bss.$RamAHB16*) + . = ALIGN(4) ; + } > RamAHB16 + /* BSS section for RamAHB_ETB16 */ + .bss_RAM5 : ALIGN(4) + { + *(.bss.$RAM5*) + *(.bss.$RamAHB_ETB16*) + . = ALIGN(4) ; + } > RamAHB_ETB16 + + /* MAIN BSS SECTION */ + .bss : ALIGN(4) + { + _bss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4) ; + _ebss = .; + PROVIDE(end = .); + } > RamLoc128 + + /* NOINIT section for RamLoc72 */ + .noinit_RAM2 (NOLOAD) : ALIGN(4) + { + *(.noinit.$RAM2*) + *(.noinit.$RamLoc72*) + . = ALIGN(4) ; + } > RamLoc72 + /* NOINIT section for RamAHB32 */ + .noinit_RAM3 (NOLOAD) : ALIGN(4) + { + *(.noinit.$RAM3*) + *(.noinit.$RamAHB32*) + . = ALIGN(4) ; + } > RamAHB32 + /* NOINIT section for RamAHB16 */ + .noinit_RAM4 (NOLOAD) : ALIGN(4) + { + *(.noinit.$RAM4*) + *(.noinit.$RamAHB16*) + . = ALIGN(4) ; + } > RamAHB16 + /* NOINIT section for RamAHB_ETB16 */ + .noinit_RAM5 (NOLOAD) : ALIGN(4) + { + *(.noinit.$RAM5*) + *(.noinit.$RamAHB_ETB16*) + . = ALIGN(4) ; + } > RamAHB_ETB16 + + /* DEFAULT NOINIT SECTION */ + .noinit (NOLOAD): ALIGN(4) + { + _noinit = .; + *(.noinit*) + . = ALIGN(4) ; + _end_noinit = .; + } > RamLoc128 + + PROVIDE(_pvHeapStart = .); + PROVIDE(_vStackTop = __top_RamLoc128 - 0); +} |