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| author | tmk <hasu@tmk-kbd.com> | 2015-04-10 01:32:04 +0900 |
|---|---|---|
| committer | tmk <hasu@tmk-kbd.com> | 2015-04-10 01:32:04 +0900 |
| commit | 1a02ebcc612e9a9c0d87e02295c7258de3a70ccc (patch) | |
| tree | e517f3c70bb2d542797e57d13e9023c84af230fb /tmk_core/doc/POWER.txt | |
| parent | 6746e37088ce8ba03529c1226bd216705edb2b1f (diff) | |
| parent | a074364c3731d66b56d988c8a6c960a83ea0e0a1 (diff) | |
Merge commit 'a074364c3731d66b56d988c8a6c960a83ea0e0a1' as 'tmk_core'
Diffstat (limited to 'tmk_core/doc/POWER.txt')
| -rw-r--r-- | tmk_core/doc/POWER.txt | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/tmk_core/doc/POWER.txt b/tmk_core/doc/POWER.txt new file mode 100644 index 0000000000..0abbbe48e8 --- /dev/null +++ b/tmk_core/doc/POWER.txt @@ -0,0 +1,62 @@ +Time to Sleep +============= +USB suspend no activity on USB line for 3ms +No Interaction no user interaction + matrix has no change + matrix has no switch on + + +AVR Power Management +==================== + +V-USB suspend + USB suspend + http://vusb.wikidot.com/examples + +MCUSR MCU Status Register + WDRF Watchdog Reset Flag + BORF + EXTRF + PORF Power-on Reset Flag + +SMCR Sleep Mode Control Register + SE Sleep Enable + SM2:0 + #define set_sleep_mode(mode) \ + #define SLEEP_MODE_IDLE (0) + #define SLEEP_MODE_ADC _BV(SM0) + #define SLEEP_MODE_PWR_DOWN _BV(SM1) + #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1)) + #define SLEEP_MODE_STANDBY (_BV(SM1) | _BV(SM2)) + #define SLEEP_MODE_EXT_STANDBY (_BV(SM0) | _BV(SM1) | _BV(SM2)) + + +ACSR Analog Comparator Control and Status Register + To disable Analog Comparator + ACSR = 0x80; + or + ACSR &= ~_BV(ACIE); + ACSR |= _BV(ACD); + + ACD: Analog Comparator Disable + When this bit is written logic one, the power to the Analog Comparator is + switched off. This bit can be set at any time to turn off the Analog + Comparator. This will reduce power consumption in Active and Idle mode. + When changing the ACD bit, the Analog Comparator Interrupt must be disabled + by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when + the bit is changed. + +DIDR1 Digital Input Disable Register 1 + AIN1D + AIN0D + When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. + + +PRR Power Reduction Register + PRTWI + PRTIM2 + PRTIM0 + PRTIM1 + PRSPI + PRUSART0 + PRADC |