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-rw-r--r--drivers/lcd/hd44780.h4
-rw-r--r--drivers/led/apa102.c26
-rw-r--r--drivers/led/aw20216.c19
-rw-r--r--drivers/painter/comms/qp_comms_spi.c32
-rw-r--r--drivers/painter/comms/qp_comms_spi.h18
-rw-r--r--drivers/painter/gc9a01/qp_gc9a01.c13
-rw-r--r--drivers/painter/generic/qp_rgb565_surface.c18
-rw-r--r--drivers/painter/ili9xxx/qp_ili9163.c14
-rw-r--r--drivers/painter/ili9xxx/qp_ili9341.c14
-rw-r--r--drivers/painter/ili9xxx/qp_ili9488.c14
-rw-r--r--drivers/painter/ssd1351/qp_ssd1351.c14
-rw-r--r--drivers/painter/st77xx/qp_st7735.c16
-rw-r--r--drivers/painter/st77xx/qp_st7789.c16
-rw-r--r--drivers/painter/tft_panel/qp_tft_panel.c12
-rw-r--r--drivers/painter/tft_panel/qp_tft_panel.h10
-rw-r--r--drivers/ps2/ps2_interrupt.c1
-rw-r--r--drivers/sensors/pmw3320.c192
-rw-r--r--drivers/sensors/pmw3320.h119
18 files changed, 464 insertions, 88 deletions
diff --git a/drivers/lcd/hd44780.h b/drivers/lcd/hd44780.h
index 9e43339344..402217a547 100644
--- a/drivers/lcd/hd44780.h
+++ b/drivers/lcd/hd44780.h
@@ -21,9 +21,9 @@ along with this program. If not, see <http://www.gnu.org/licenses/>.
#include <stdbool.h>
/**
- * \defgroup hd44780
+ * \file
*
- * HD44780 Character LCD Driver
+ * \defgroup hd44780 HD44780 Character LCD Driver
* \{
*/
diff --git a/drivers/led/apa102.c b/drivers/led/apa102.c
index f291948975..40fc68e4f1 100644
--- a/drivers/led/apa102.c
+++ b/drivers/led/apa102.c
@@ -27,7 +27,7 @@
# if defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F3XX) || defined(STM32F4XX) || defined(STM32L0XX) || defined(GD32VF103)
# define APA102_NOPS (100 / (1000000000L / (CPU_CLOCK / 4))) // This calculates how many loops of 4 nops to run to delay 100 ns
# else
-# error("APA102_NOPS configuration required")
+# error APA102_NOPS configuration required
# define APA102_NOPS 0 // this just pleases the compile so the above error is easier to spot
# endif
# endif
@@ -43,14 +43,14 @@
} \
} while (0)
-#define APA102_SEND_BIT(byte, bit) \
- do { \
- writePin(RGB_DI_PIN, (byte >> bit) & 1); \
- io_wait; \
- writePinHigh(RGB_CI_PIN); \
- io_wait; \
- writePinLow(RGB_CI_PIN); \
- io_wait; \
+#define APA102_SEND_BIT(byte, bit) \
+ do { \
+ writePin(APA102_DI_PIN, (byte >> bit) & 1); \
+ io_wait; \
+ writePinHigh(APA102_CI_PIN); \
+ io_wait; \
+ writePinLow(APA102_CI_PIN); \
+ io_wait; \
} while (0)
uint8_t apa102_led_brightness = APA102_DEFAULT_BRIGHTNESS;
@@ -77,11 +77,11 @@ void rgblight_call_driver(LED_TYPE *start_led, uint8_t num_leds) {
}
void static apa102_init(void) {
- setPinOutput(RGB_DI_PIN);
- setPinOutput(RGB_CI_PIN);
+ setPinOutput(APA102_DI_PIN);
+ setPinOutput(APA102_CI_PIN);
- writePinLow(RGB_DI_PIN);
- writePinLow(RGB_CI_PIN);
+ writePinLow(APA102_DI_PIN);
+ writePinLow(APA102_CI_PIN);
}
void apa102_set_brightness(uint8_t brightness) {
diff --git a/drivers/led/aw20216.c b/drivers/led/aw20216.c
index cbb0b60774..7895f1497b 100644
--- a/drivers/led/aw20216.c
+++ b/drivers/led/aw20216.c
@@ -1,4 +1,5 @@
/* Copyright 2021 Jasper Chan
+ * 2023 Huckies <https://github.com/Huckies>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -15,6 +16,7 @@
*/
#include "aw20216.h"
+#include "wait.h"
#include "spi_master.h"
/* The AW20216 appears to be somewhat similar to the IS31FL743, although quite
@@ -34,6 +36,8 @@
#define AW_REG_CONFIGURATION 0x00 // PG0
#define AW_REG_GLOBALCURRENT 0x01 // PG0
+#define AW_REG_RESET 0x2F // PG0
+#define AW_REG_MIXFUNCTION 0x46 // PG0
// Default value of AW_REG_CONFIGURATION
// D7:D4 = 1011, SWSEL (SW1~SW12 active)
@@ -41,7 +45,10 @@
// D2:D1 = 00, OSDE (open/short detection enable)
// D0 = 0, CHIPEN (write 1 to enable LEDs when hardware enable pulled high)
#define AW_CONFIG_DEFAULT 0b10110000
+#define AW_MIXCR_DEFAULT 0b00000000
+#define AW_RESET_CMD 0xAE
#define AW_CHIPEN 1
+#define AW_LPEN (0x01 << 1)
#define AW_PWM_REGISTER_COUNT 216
@@ -94,6 +101,10 @@ static inline bool AW20216_write_register(pin_t cs_pin, uint8_t page, uint8_t re
return AW20216_write(cs_pin, page, reg, &value, 1);
}
+void AW20216_soft_reset(pin_t cs_pin) {
+ AW20216_write_register(cs_pin, AW_PAGE_FUNCTION, AW_REG_RESET, AW_RESET_CMD);
+}
+
static void AW20216_init_scaling(pin_t cs_pin) {
// Set constant current to the max, control brightness with PWM
for (uint8_t i = 0; i < AW_PWM_REGISTER_COUNT; i++) {
@@ -111,15 +122,23 @@ static inline void AW20216_soft_enable(pin_t cs_pin) {
AW20216_write_register(cs_pin, AW_PAGE_FUNCTION, AW_REG_CONFIGURATION, AW_CONFIG_DEFAULT | AW_CHIPEN);
}
+static inline void AW20216_auto_lowpower(pin_t cs_pin) {
+ AW20216_write_register(cs_pin, AW_PAGE_FUNCTION, AW_REG_MIXFUNCTION, AW_MIXCR_DEFAULT | AW_LPEN);
+}
+
void AW20216_init(pin_t cs_pin, pin_t en_pin) {
setPinOutput(en_pin);
writePinHigh(en_pin);
+ AW20216_soft_reset(cs_pin);
+ wait_ms(2);
+
// Drivers should start with all scaling and PWM registers as off
AW20216_init_current_limit(cs_pin);
AW20216_init_scaling(cs_pin);
AW20216_soft_enable(cs_pin);
+ AW20216_auto_lowpower(cs_pin);
}
void AW20216_set_color(int index, uint8_t red, uint8_t green, uint8_t blue) {
diff --git a/drivers/painter/comms/qp_comms_spi.c b/drivers/painter/comms/qp_comms_spi.c
index e644ba9f84..7534e844d8 100644
--- a/drivers/painter/comms/qp_comms_spi.c
+++ b/drivers/painter/comms/qp_comms_spi.c
@@ -10,8 +10,8 @@
// Base SPI support
bool qp_comms_spi_init(painter_device_t device) {
- struct painter_driver_t * driver = (struct painter_driver_t *)device;
- struct qp_comms_spi_config_t *comms_config = (struct qp_comms_spi_config_t *)driver->comms_config;
+ painter_driver_t * driver = (painter_driver_t *)device;
+ qp_comms_spi_config_t *comms_config = (qp_comms_spi_config_t *)driver->comms_config;
// Initialize the SPI peripheral
spi_init();
@@ -24,8 +24,8 @@ bool qp_comms_spi_init(painter_device_t device) {
}
bool qp_comms_spi_start(painter_device_t device) {
- struct painter_driver_t * driver = (struct painter_driver_t *)device;
- struct qp_comms_spi_config_t *comms_config = (struct qp_comms_spi_config_t *)driver->comms_config;
+ painter_driver_t * driver = (painter_driver_t *)device;
+ qp_comms_spi_config_t *comms_config = (qp_comms_spi_config_t *)driver->comms_config;
return spi_start(comms_config->chip_select_pin, comms_config->lsb_first, comms_config->mode, comms_config->divisor);
}
@@ -33,8 +33,10 @@ bool qp_comms_spi_start(painter_device_t device) {
uint32_t qp_comms_spi_send_data(painter_device_t device, const void *data, uint32_t byte_count) {
uint32_t bytes_remaining = byte_count;
const uint8_t *p = (const uint8_t *)data;
+ const uint32_t max_msg_length = 1024;
+
while (bytes_remaining > 0) {
- uint32_t bytes_this_loop = bytes_remaining < 1024 ? bytes_remaining : 1024;
+ uint32_t bytes_this_loop = QP_MIN(bytes_remaining, max_msg_length);
spi_transmit(p, bytes_this_loop);
p += bytes_this_loop;
bytes_remaining -= bytes_this_loop;
@@ -44,13 +46,13 @@ uint32_t qp_comms_spi_send_data(painter_device_t device, const void *data, uint3
}
void qp_comms_spi_stop(painter_device_t device) {
- struct painter_driver_t * driver = (struct painter_driver_t *)device;
- struct qp_comms_spi_config_t *comms_config = (struct qp_comms_spi_config_t *)driver->comms_config;
+ painter_driver_t * driver = (painter_driver_t *)device;
+ qp_comms_spi_config_t *comms_config = (qp_comms_spi_config_t *)driver->comms_config;
spi_stop();
writePinHigh(comms_config->chip_select_pin);
}
-const struct painter_comms_vtable_t spi_comms_vtable = {
+const painter_comms_vtable_t spi_comms_vtable = {
.comms_init = qp_comms_spi_init,
.comms_start = qp_comms_spi_start,
.comms_send = qp_comms_spi_send_data,
@@ -67,8 +69,8 @@ bool qp_comms_spi_dc_reset_init(painter_device_t device) {
return false;
}
- struct painter_driver_t * driver = (struct painter_driver_t *)device;
- struct qp_comms_spi_dc_reset_config_t *comms_config = (struct qp_comms_spi_dc_reset_config_t *)driver->comms_config;
+ painter_driver_t * driver = (painter_driver_t *)device;
+ qp_comms_spi_dc_reset_config_t *comms_config = (qp_comms_spi_dc_reset_config_t *)driver->comms_config;
// Set up D/C as output low, if specified
if (comms_config->dc_pin != NO_PIN) {
@@ -89,15 +91,15 @@ bool qp_comms_spi_dc_reset_init(painter_device_t device) {
}
uint32_t qp_comms_spi_dc_reset_send_data(painter_device_t device, const void *data, uint32_t byte_count) {
- struct painter_driver_t * driver = (struct painter_driver_t *)device;
- struct qp_comms_spi_dc_reset_config_t *comms_config = (struct qp_comms_spi_dc_reset_config_t *)driver->comms_config;
+ painter_driver_t * driver = (painter_driver_t *)device;
+ qp_comms_spi_dc_reset_config_t *comms_config = (qp_comms_spi_dc_reset_config_t *)driver->comms_config;
writePinHigh(comms_config->dc_pin);
return qp_comms_spi_send_data(device, data, byte_count);
}
void qp_comms_spi_dc_reset_send_command(painter_device_t device, uint8_t cmd) {
- struct painter_driver_t * driver = (struct painter_driver_t *)device;
- struct qp_comms_spi_dc_reset_config_t *comms_config = (struct qp_comms_spi_dc_reset_config_t *)driver->comms_config;
+ painter_driver_t * driver = (painter_driver_t *)device;
+ qp_comms_spi_dc_reset_config_t *comms_config = (qp_comms_spi_dc_reset_config_t *)driver->comms_config;
writePinLow(comms_config->dc_pin);
spi_write(cmd);
}
@@ -118,7 +120,7 @@ void qp_comms_spi_dc_reset_bulk_command_sequence(painter_device_t device, const
}
}
-const struct painter_comms_with_command_vtable_t spi_comms_with_dc_vtable = {
+const painter_comms_with_command_vtable_t spi_comms_with_dc_vtable = {
.base =
{
.comms_init = qp_comms_spi_dc_reset_init,
diff --git a/drivers/painter/comms/qp_comms_spi.h b/drivers/painter/comms/qp_comms_spi.h
index 9989987327..b3da86d573 100644
--- a/drivers/painter/comms/qp_comms_spi.h
+++ b/drivers/painter/comms/qp_comms_spi.h
@@ -13,36 +13,36 @@
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Base SPI support
-struct qp_comms_spi_config_t {
+typedef struct qp_comms_spi_config_t {
pin_t chip_select_pin;
uint16_t divisor;
bool lsb_first;
int8_t mode;
-};
+} qp_comms_spi_config_t;
bool qp_comms_spi_init(painter_device_t device);
bool qp_comms_spi_start(painter_device_t device);
uint32_t qp_comms_spi_send_data(painter_device_t device, const void* data, uint32_t byte_count);
void qp_comms_spi_stop(painter_device_t device);
-extern const struct painter_comms_vtable_t spi_comms_vtable;
+extern const painter_comms_vtable_t spi_comms_vtable;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// SPI with D/C and RST pins
# ifdef QUANTUM_PAINTER_SPI_DC_RESET_ENABLE
-struct qp_comms_spi_dc_reset_config_t {
- struct qp_comms_spi_config_t spi_config;
- pin_t dc_pin;
- pin_t reset_pin;
-};
+typedef struct qp_comms_spi_dc_reset_config_t {
+ qp_comms_spi_config_t spi_config;
+ pin_t dc_pin;
+ pin_t reset_pin;
+} qp_comms_spi_dc_reset_config_t;
void qp_comms_spi_dc_reset_send_command(painter_device_t device, uint8_t cmd);
uint32_t qp_comms_spi_dc_reset_send_data(painter_device_t device, const void* data, uint32_t byte_count);
void qp_comms_spi_dc_reset_bulk_command_sequence(painter_device_t device, const uint8_t* sequence, size_t sequence_len);
-extern const struct painter_comms_with_command_vtable_t spi_comms_with_dc_vtable;
+extern const painter_comms_with_command_vtable_t spi_comms_with_dc_vtable;
# endif // QUANTUM_PAINTER_SPI_DC_RESET_ENABLE
diff --git a/drivers/painter/gc9a01/qp_gc9a01.c b/drivers/painter/gc9a01/qp_gc9a01.c
index 5d079435c6..a2eb2cf57c 100644
--- a/drivers/painter/gc9a01/qp_gc9a01.c
+++ b/drivers/painter/gc9a01/qp_gc9a01.c
@@ -1,4 +1,5 @@
// Copyright 2021 Paul Cotter (@gr1mr3aver)
+// Copyright 2023 Nick Brassel (@tzarc)
// SPDX-License-Identifier: GPL-2.0-or-later
#include <wait.h>
@@ -93,7 +94,7 @@ __attribute__((weak)) bool qp_gc9a01_init(painter_device_t device, painter_rotat
// Driver vtable
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-const struct tft_panel_dc_reset_painter_driver_vtable_t gc9a01_driver_vtable = {
+const tft_panel_dc_reset_painter_driver_vtable_t gc9a01_driver_vtable = {
.base =
{
.init = qp_gc9a01_init,
@@ -124,8 +125,8 @@ painter_device_t qp_gc9a01_make_spi_device(uint16_t panel_width, uint16_t panel_
for (uint32_t i = 0; i < GC9A01_NUM_DEVICES; ++i) {
tft_panel_dc_reset_painter_device_t *driver = &gc9a01_drivers[i];
if (!driver->base.driver_vtable) {
- driver->base.driver_vtable = (const struct painter_driver_vtable_t *)&gc9a01_driver_vtable;
- driver->base.comms_vtable = (const struct painter_comms_vtable_t *)&spi_comms_with_dc_vtable;
+ driver->base.driver_vtable = (const painter_driver_vtable_t *)&gc9a01_driver_vtable;
+ driver->base.comms_vtable = (const painter_comms_vtable_t *)&spi_comms_with_dc_vtable;
driver->base.native_bits_per_pixel = 16; // RGB565
driver->base.panel_width = panel_width;
driver->base.panel_height = panel_height;
@@ -141,6 +142,12 @@ painter_device_t qp_gc9a01_make_spi_device(uint16_t panel_width, uint16_t panel_
driver->spi_dc_reset_config.spi_config.mode = spi_mode;
driver->spi_dc_reset_config.dc_pin = dc_pin;
driver->spi_dc_reset_config.reset_pin = reset_pin;
+
+ if (!qp_internal_register_device((painter_device_t)driver)) {
+ memset(driver, 0, sizeof(tft_panel_dc_reset_painter_device_t));
+ return NULL;
+ }
+
return (painter_device_t)driver;
}
}
diff --git a/drivers/painter/generic/qp_rgb565_surface.c b/drivers/painter/generic/qp_rgb565_surface.c
index 474c86feec..9c283e0687 100644
--- a/drivers/painter/generic/qp_rgb565_surface.c
+++ b/drivers/painter/generic/qp_rgb565_surface.c
@@ -9,7 +9,7 @@
// Device definition
typedef struct rgb565_surface_painter_device_t {
- struct painter_driver_t base; // must be first, so it can be cast to/from the painter_device_t* type
+ painter_driver_t base; // must be first, so it can be cast to/from the painter_device_t* type
// The target buffer
uint16_t *buffer;
@@ -95,7 +95,7 @@ static inline void stream_pixdata(rgb565_surface_painter_device_t *surface, cons
// Driver vtable
static bool qp_rgb565_surface_init(painter_device_t device, painter_rotation_t rotation) {
- struct painter_driver_t * driver = (struct painter_driver_t *)device;
+ painter_driver_t * driver = (painter_driver_t *)device;
rgb565_surface_painter_device_t *surface = (rgb565_surface_painter_device_t *)driver;
memset(surface->buffer, 0, driver->panel_width * driver->panel_height * driver->native_bits_per_pixel / 8);
return true;
@@ -107,13 +107,13 @@ static bool qp_rgb565_surface_power(painter_device_t device, bool power_on) {
}
static bool qp_rgb565_surface_clear(painter_device_t device) {
- struct painter_driver_t *driver = (struct painter_driver_t *)device;
+ painter_driver_t *driver = (painter_driver_t *)device;
driver->driver_vtable->init(device, driver->rotation); // Re-init the surface
return true;
}
static bool qp_rgb565_surface_flush(painter_device_t device) {
- struct painter_driver_t * driver = (struct painter_driver_t *)device;
+ painter_driver_t * driver = (painter_driver_t *)device;
rgb565_surface_painter_device_t *surface = (rgb565_surface_painter_device_t *)driver;
surface->dirty_l = surface->dirty_t = UINT16_MAX;
surface->dirty_r = surface->dirty_b = 0;
@@ -122,7 +122,7 @@ static bool qp_rgb565_surface_flush(painter_device_t device) {
}
static bool qp_rgb565_surface_viewport(painter_device_t device, uint16_t left, uint16_t top, uint16_t right, uint16_t bottom) {
- struct painter_driver_t * driver = (struct painter_driver_t *)device;
+ painter_driver_t * driver = (painter_driver_t *)device;
rgb565_surface_painter_device_t *surface = (rgb565_surface_painter_device_t *)driver;
// Set the viewport locations
@@ -139,7 +139,7 @@ static bool qp_rgb565_surface_viewport(painter_device_t device, uint16_t left, u
// Stream pixel data to the current write position in GRAM
static bool qp_rgb565_surface_pixdata(painter_device_t device, const void *pixel_data, uint32_t native_pixel_count) {
- struct painter_driver_t * driver = (struct painter_driver_t *)device;
+ painter_driver_t * driver = (painter_driver_t *)device;
rgb565_surface_painter_device_t *surface = (rgb565_surface_painter_device_t *)driver;
stream_pixdata(surface, (const uint16_t *)pixel_data, native_pixel_count);
return true;
@@ -170,7 +170,7 @@ static bool qp_rgb565_surface_append_pixdata(painter_device_t device, uint8_t *t
return true;
}
-const struct painter_driver_vtable_t rgb565_surface_driver_vtable = {
+const painter_driver_vtable_t rgb565_surface_driver_vtable = {
.init = qp_rgb565_surface_init,
.power = qp_rgb565_surface_power,
.clear = qp_rgb565_surface_clear,
@@ -201,7 +201,7 @@ uint32_t qp_rgb565_surface_comms_send(painter_device_t device, const void *data,
return byte_count;
}
-struct painter_comms_vtable_t rgb565_surface_driver_comms_vtable = {
+painter_comms_vtable_t rgb565_surface_driver_comms_vtable = {
// These are all effective no-op's because they're not actually needed.
.comms_init = qp_rgb565_surface_comms_init,
.comms_start = qp_rgb565_surface_comms_start,
@@ -234,7 +234,7 @@ painter_device_t qp_rgb565_make_surface(uint16_t panel_width, uint16_t panel_hei
// Drawing routine to copy out the dirty region and send it to another device
bool qp_rgb565_surface_draw(painter_device_t surface, painter_device_t display, uint16_t x, uint16_t y) {
- struct painter_driver_t * surface_driver = (struct painter_driver_t *)surface;
+ painter_driver_t * surface_driver = (painter_driver_t *)surface;
rgb565_surface_painter_device_t *surface_handle = (rgb565_surface_painter_device_t *)surface_driver;
// If we're not dirty... we're done.
diff --git a/drivers/painter/ili9xxx/qp_ili9163.c b/drivers/painter/ili9xxx/qp_ili9163.c
index af37686631..a75be57904 100644
--- a/drivers/painter/ili9xxx/qp_ili9163.c
+++ b/drivers/painter/ili9xxx/qp_ili9163.c
@@ -1,4 +1,4 @@
-// Copyright 2021 Nick Brassel (@tzarc)
+// Copyright 2021-2023 Nick Brassel (@tzarc)
// SPDX-License-Identifier: GPL-2.0-or-later
#include "qp_internal.h"
@@ -58,7 +58,7 @@ __attribute__((weak)) bool qp_ili9163_init(painter_device_t device, painter_rota
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Driver vtable
-const struct tft_panel_dc_reset_painter_driver_vtable_t ili9163_driver_vtable = {
+const tft_panel_dc_reset_painter_driver_vtable_t ili9163_driver_vtable = {
.base =
{
.init = qp_ili9163_init,
@@ -93,8 +93,8 @@ painter_device_t qp_ili9163_make_spi_device(uint16_t panel_width, uint16_t panel
for (uint32_t i = 0; i < ILI9163_NUM_DEVICES; ++i) {
tft_panel_dc_reset_painter_device_t *driver = &ili9163_drivers[i];
if (!driver->base.driver_vtable) {
- driver->base.driver_vtable = (const struct painter_driver_vtable_t *)&ili9163_driver_vtable;
- driver->base.comms_vtable = (const struct painter_comms_vtable_t *)&spi_comms_with_dc_vtable;
+ driver->base.driver_vtable = (const painter_driver_vtable_t *)&ili9163_driver_vtable;
+ driver->base.comms_vtable = (const painter_comms_vtable_t *)&spi_comms_with_dc_vtable;
driver->base.panel_width = panel_width;
driver->base.panel_height = panel_height;
driver->base.rotation = QP_ROTATION_0;
@@ -110,6 +110,12 @@ painter_device_t qp_ili9163_make_spi_device(uint16_t panel_width, uint16_t panel
driver->spi_dc_reset_config.spi_config.mode = spi_mode;
driver->spi_dc_reset_config.dc_pin = dc_pin;
driver->spi_dc_reset_config.reset_pin = reset_pin;
+
+ if (!qp_internal_register_device((painter_device_t)driver)) {
+ memset(driver, 0, sizeof(tft_panel_dc_reset_painter_device_t));
+ return NULL;
+ }
+
return (painter_device_t)driver;
}
}
diff --git a/drivers/painter/ili9xxx/qp_ili9341.c b/drivers/painter/ili9xxx/qp_ili9341.c
index aca3809912..4130271f71 100644
--- a/drivers/painter/ili9xxx/qp_ili9341.c
+++ b/drivers/painter/ili9xxx/qp_ili9341.c
@@ -1,4 +1,4 @@
-// Copyright 2021 Nick Brassel (@tzarc)
+// Copyright 2021-2023 Nick Brassel (@tzarc)
// SPDX-License-Identifier: GPL-2.0-or-later
#include "qp_internal.h"
@@ -65,7 +65,7 @@ __attribute__((weak)) bool qp_ili9341_init(painter_device_t device, painter_rota
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Driver vtable
-const struct tft_panel_dc_reset_painter_driver_vtable_t ili9341_driver_vtable = {
+const tft_panel_dc_reset_painter_driver_vtable_t ili9341_driver_vtable = {
.base =
{
.init = qp_ili9341_init,
@@ -100,8 +100,8 @@ painter_device_t qp_ili9341_make_spi_device(uint16_t panel_width, uint16_t panel
for (uint32_t i = 0; i < ILI9341_NUM_DEVICES; ++i) {
tft_panel_dc_reset_painter_device_t *driver = &ili9341_drivers[i];
if (!driver->base.driver_vtable) {
- driver->base.driver_vtable = (const struct painter_driver_vtable_t *)&ili9341_driver_vtable;
- driver->base.comms_vtable = (const struct painter_comms_vtable_t *)&spi_comms_with_dc_vtable;
+ driver->base.driver_vtable = (const painter_driver_vtable_t *)&ili9341_driver_vtable;
+ driver->base.comms_vtable = (const painter_comms_vtable_t *)&spi_comms_with_dc_vtable;
driver->base.native_bits_per_pixel = 16; // RGB565
driver->base.panel_width = panel_width;
driver->base.panel_height = panel_height;
@@ -117,6 +117,12 @@ painter_device_t qp_ili9341_make_spi_device(uint16_t panel_width, uint16_t panel
driver->spi_dc_reset_config.spi_config.mode = spi_mode;
driver->spi_dc_reset_config.dc_pin = dc_pin;
driver->spi_dc_reset_config.reset_pin = reset_pin;
+
+ if (!qp_internal_register_device((painter_device_t)driver)) {
+ memset(driver, 0, sizeof(tft_panel_dc_reset_painter_device_t));
+ return NULL;
+ }
+
return (painter_device_t)driver;
}
}
diff --git a/drivers/painter/ili9xxx/qp_ili9488.c b/drivers/painter/ili9xxx/qp_ili9488.c
index e51f0e1d51..a8da52132e 100644
--- a/drivers/painter/ili9xxx/qp_ili9488.c
+++ b/drivers/painter/ili9xxx/qp_ili9488.c
@@ -1,4 +1,4 @@
-// Copyright 2021 Nick Brassel (@tzarc)
+// Copyright 2021-2023 Nick Brassel (@tzarc)
// SPDX-License-Identifier: GPL-2.0-or-later
#include "qp_internal.h"
@@ -58,7 +58,7 @@ __attribute__((weak)) bool qp_ili9488_init(painter_device_t device, painter_rota
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Driver vtable
-const struct tft_panel_dc_reset_painter_driver_vtable_t ili9488_driver_vtable = {
+const tft_panel_dc_reset_painter_driver_vtable_t ili9488_driver_vtable = {
.base =
{
.init = qp_ili9488_init,
@@ -93,8 +93,8 @@ painter_device_t qp_ili9488_make_spi_device(uint16_t panel_width, uint16_t panel
for (uint32_t i = 0; i < ILI9488_NUM_DEVICES; ++i) {
tft_panel_dc_reset_painter_device_t *driver = &ili9488_drivers[i];
if (!driver->base.driver_vtable) {
- driver->base.driver_vtable = (const struct painter_driver_vtable_t *)&ili9488_driver_vtable;
- driver->base.comms_vtable = (const struct painter_comms_vtable_t *)&spi_comms_with_dc_vtable;
+ driver->base.driver_vtable = (const painter_driver_vtable_t *)&ili9488_driver_vtable;
+ driver->base.comms_vtable = (const painter_comms_vtable_t *)&spi_comms_with_dc_vtable;
driver->base.native_bits_per_pixel = 24; // RGB888
driver->base.panel_width = panel_width;
driver->base.panel_height = panel_height;
@@ -110,6 +110,12 @@ painter_device_t qp_ili9488_make_spi_device(uint16_t panel_width, uint16_t panel
driver->spi_dc_reset_config.spi_config.mode = spi_mode;
driver->spi_dc_reset_config.dc_pin = dc_pin;
driver->spi_dc_reset_config.reset_pin = reset_pin;
+
+ if (!qp_internal_register_device((painter_device_t)driver)) {
+ memset(driver, 0, sizeof(tft_panel_dc_reset_painter_device_t));
+ return NULL;
+ }
+
return (painter_device_t)driver;
}
}
diff --git a/drivers/painter/ssd1351/qp_ssd1351.c b/drivers/painter/ssd1351/qp_ssd1351.c
index 548785a1bd..434b7f0327 100644
--- a/drivers/painter/ssd1351/qp_ssd1351.c
+++ b/drivers/painter/ssd1351/qp_ssd1351.c
@@ -1,4 +1,4 @@
-// Copyright 2021 Nick Brassel (@tzarc)
+// Copyright 2021-2023 Nick Brassel (@tzarc)
// SPDX-License-Identifier: GPL-2.0-or-later
#include "qp_internal.h"
@@ -62,7 +62,7 @@ __attribute__((weak)) bool qp_ssd1351_init(painter_device_t device, painter_rota
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Driver vtable
-const struct tft_panel_dc_reset_painter_driver_vtable_t ssd1351_driver_vtable = {
+const tft_panel_dc_reset_painter_driver_vtable_t ssd1351_driver_vtable = {
.base =
{
.init = qp_ssd1351_init,
@@ -97,8 +97,8 @@ painter_device_t qp_ssd1351_make_spi_device(uint16_t panel_width, uint16_t panel
for (uint32_t i = 0; i < SSD1351_NUM_DEVICES; ++i) {
tft_panel_dc_reset_painter_device_t *driver = &ssd1351_drivers[i];
if (!driver->base.driver_vtable) {
- driver->base.driver_vtable = (const struct painter_driver_vtable_t *)&ssd1351_driver_vtable;
- driver->base.comms_vtable = (const struct painter_comms_vtable_t *)&spi_comms_with_dc_vtable;
+ driver->base.driver_vtable = (const painter_driver_vtable_t *)&ssd1351_driver_vtable;
+ driver->base.comms_vtable = (const painter_comms_vtable_t *)&spi_comms_with_dc_vtable;
driver->base.panel_width = panel_width;
driver->base.panel_height = panel_height;
driver->base.rotation = QP_ROTATION_0;
@@ -114,6 +114,12 @@ painter_device_t qp_ssd1351_make_spi_device(uint16_t panel_width, uint16_t panel
driver->spi_dc_reset_config.spi_config.mode = spi_mode;
driver->spi_dc_reset_config.dc_pin = dc_pin;
driver->spi_dc_reset_config.reset_pin = reset_pin;
+
+ if (!qp_internal_register_device((painter_device_t)driver)) {
+ memset(driver, 0, sizeof(tft_panel_dc_reset_painter_device_t));
+ return NULL;
+ }
+
return (painter_device_t)driver;
}
}
diff --git a/drivers/painter/st77xx/qp_st7735.c b/drivers/painter/st77xx/qp_st7735.c
index 7ee5a6b562..98baf400ab 100644
--- a/drivers/painter/st77xx/qp_st7735.c
+++ b/drivers/painter/st77xx/qp_st7735.c
@@ -1,5 +1,5 @@
// Copyright 2021 Paul Cotter (@gr1mr3aver)
-// Copyright 2021 Nick Brassel (@tzarc)
+// Copyright 2021-2023 Nick Brassel (@tzarc)
// Copyright 2022 David Hoelscher (@customMK)
// SPDX-License-Identifier: GPL-2.0-or-later
@@ -25,7 +25,7 @@ tft_panel_dc_reset_painter_device_t st7735_drivers[ST7735_NUM_DEVICES] = {0};
#ifndef ST7735_NO_AUTOMATIC_OFFSETS
static inline void st7735_automatic_viewport_offsets(painter_device_t device, painter_rotation_t rotation) {
- struct painter_driver_t *driver = (struct painter_driver_t *)device;
+ painter_driver_t *driver = (painter_driver_t *)device;
// clang-format off
const struct {
@@ -82,7 +82,7 @@ __attribute__((weak)) bool qp_st7735_init(painter_device_t device, painter_rotat
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Driver vtable
-const struct tft_panel_dc_reset_painter_driver_vtable_t st7735_driver_vtable = {
+const tft_panel_dc_reset_painter_driver_vtable_t st7735_driver_vtable = {
.base =
{
.init = qp_st7735_init,
@@ -117,8 +117,8 @@ painter_device_t qp_st7735_make_spi_device(uint16_t panel_width, uint16_t panel_
for (uint32_t i = 0; i < ST7735_NUM_DEVICES; ++i) {
tft_panel_dc_reset_painter_device_t *driver = &st7735_drivers[i];
if (!driver->base.driver_vtable) {
- driver->base.driver_vtable = (const struct painter_driver_vtable_t *)&st7735_driver_vtable;
- driver->base.comms_vtable = (const struct painter_comms_vtable_t *)&spi_comms_with_dc_vtable;
+ driver->base.driver_vtable = (const painter_driver_vtable_t *)&st7735_driver_vtable;
+ driver->base.comms_vtable = (const painter_comms_vtable_t *)&spi_comms_with_dc_vtable;
driver->base.panel_width = panel_width;
driver->base.panel_height = panel_height;
driver->base.rotation = QP_ROTATION_0;
@@ -134,6 +134,12 @@ painter_device_t qp_st7735_make_spi_device(uint16_t panel_width, uint16_t panel_
driver->spi_dc_reset_config.spi_config.mode = spi_mode;
driver->spi_dc_reset_config.dc_pin = dc_pin;
driver->spi_dc_reset_config.reset_pin = reset_pin;
+
+ if (!qp_internal_register_device((painter_device_t)driver)) {
+ memset(driver, 0, sizeof(tft_panel_dc_reset_painter_device_t));
+ return NULL;
+ }
+
return (painter_device_t)driver;
}
}
diff --git a/drivers/painter/st77xx/qp_st7789.c b/drivers/painter/st77xx/qp_st7789.c
index 9f474369d6..f9065f5178 100644
--- a/drivers/painter/st77xx/qp_st7789.c
+++ b/drivers/painter/st77xx/qp_st7789.c
@@ -1,5 +1,5 @@
// Copyright 2021 Paul Cotter (@gr1mr3aver)
-// Copyright 2021 Nick Brassel (@tzarc)
+// Copyright 2021-2023 Nick Brassel (@tzarc)
// SPDX-License-Identifier: GPL-2.0-or-later
#include "qp_internal.h"
@@ -24,7 +24,7 @@ tft_panel_dc_reset_painter_device_t st7789_drivers[ST7789_NUM_DEVICES] = {0};
#ifndef ST7789_NO_AUTOMATIC_OFFSETS
static inline void st7789_automatic_viewport_offsets(painter_device_t device, painter_rotation_t rotation) {
- struct painter_driver_t *driver = (struct painter_driver_t *)device;
+ painter_driver_t *driver = (painter_driver_t *)device;
// clang-format off
const struct {
@@ -81,7 +81,7 @@ __attribute__((weak)) bool qp_st7789_init(painter_device_t device, painter_rotat
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Driver vtable
-const struct tft_panel_dc_reset_painter_driver_vtable_t st7789_driver_vtable = {
+const tft_panel_dc_reset_painter_driver_vtable_t st7789_driver_vtable = {
.base =
{
.init = qp_st7789_init,
@@ -116,8 +116,8 @@ painter_device_t qp_st7789_make_spi_device(uint16_t panel_width, uint16_t panel_
for (uint32_t i = 0; i < ST7789_NUM_DEVICES; ++i) {
tft_panel_dc_reset_painter_device_t *driver = &st7789_drivers[i];
if (!driver->base.driver_vtable) {
- driver->base.driver_vtable = (const struct painter_driver_vtable_t *)&st7789_driver_vtable;
- driver->base.comms_vtable = (const struct painter_comms_vtable_t *)&spi_comms_with_dc_vtable;
+ driver->base.driver_vtable = (const painter_driver_vtable_t *)&st7789_driver_vtable;
+ driver->base.comms_vtable = (const painter_comms_vtable_t *)&spi_comms_with_dc_vtable;
driver->base.panel_width = panel_width;
driver->base.panel_height = panel_height;
driver->base.rotation = QP_ROTATION_0;
@@ -133,6 +133,12 @@ painter_device_t qp_st7789_make_spi_device(uint16_t panel_width, uint16_t panel_
driver->spi_dc_reset_config.spi_config.mode = spi_mode;
driver->spi_dc_reset_config.dc_pin = dc_pin;
driver->spi_dc_reset_config.reset_pin = reset_pin;
+
+ if (!qp_internal_register_device((painter_device_t)driver)) {
+ memset(driver, 0, sizeof(tft_panel_dc_reset_painter_device_t));
+ return NULL;
+ }
+
return (painter_device_t)driver;
}
}
diff --git a/drivers/painter/tft_panel/qp_tft_panel.c b/drivers/painter/tft_panel/qp_tft_panel.c
index 4a24cf9953..16dba9d6a6 100644
--- a/drivers/painter/tft_panel/qp_tft_panel.c
+++ b/drivers/painter/tft_panel/qp_tft_panel.c
@@ -12,15 +12,15 @@
// Power control
bool qp_tft_panel_power(painter_device_t device, bool power_on) {
- struct painter_driver_t * driver = (struct painter_driver_t *)device;
- struct tft_panel_dc_reset_painter_driver_vtable_t *vtable = (struct tft_panel_dc_reset_painter_driver_vtable_t *)driver->driver_vtable;
+ painter_driver_t * driver = (painter_driver_t *)device;
+ tft_panel_dc_reset_painter_driver_vtable_t *vtable = (tft_panel_dc_reset_painter_driver_vtable_t *)driver->driver_vtable;
qp_comms_command(device, power_on ? vtable->opcodes.display_on : vtable->opcodes.display_off);
return true;
}
// Screen clear
bool qp_tft_panel_clear(painter_device_t device) {
- struct painter_driver_t *driver = (struct painter_driver_t *)device;
+ painter_driver_t *driver = (painter_driver_t *)device;
driver->driver_vtable->init(device, driver->rotation); // Re-init the LCD
return true;
}
@@ -33,8 +33,8 @@ bool qp_tft_panel_flush(painter_device_t device) {
// Viewport to draw to
bool qp_tft_panel_viewport(painter_device_t device, uint16_t left, uint16_t top, uint16_t right, uint16_t bottom) {
- struct painter_driver_t * driver = (struct painter_driver_t *)device;
- struct tft_panel_dc_reset_painter_driver_vtable_t *vtable = (struct tft_panel_dc_reset_painter_driver_vtable_t *)driver->driver_vtable;
+ painter_driver_t * driver = (painter_driver_t *)device;
+ tft_panel_dc_reset_painter_driver_vtable_t *vtable = (tft_panel_dc_reset_painter_driver_vtable_t *)driver->driver_vtable;
// Fix up the drawing location if required
left += driver->offset_x;
@@ -80,7 +80,7 @@ bool qp_tft_panel_viewport(painter_device_t device, uint16_t left, uint16_t top,
// Stream pixel data to the current write position in GRAM
bool qp_tft_panel_pixdata(painter_device_t device, const void *pixel_data, uint32_t native_pixel_count) {
- struct painter_driver_t *driver = (struct painter_driver_t *)device;
+ painter_driver_t *driver = (painter_driver_t *)device;
qp_comms_send(device, pixel_data, native_pixel_count * driver->native_bits_per_pixel / 8);
return true;
}
diff --git a/drivers/painter/tft_panel/qp_tft_panel.h b/drivers/painter/tft_panel/qp_tft_panel.h
index 83b8dd5406..67168645b7 100644
--- a/drivers/painter/tft_panel/qp_tft_panel.h
+++ b/drivers/painter/tft_panel/qp_tft_panel.h
@@ -12,8 +12,8 @@
// Common TFT panel implementation using D/C, and RST pins.
// Driver vtable with extras
-struct tft_panel_dc_reset_painter_driver_vtable_t {
- struct painter_driver_vtable_t base; // must be first, so it can be cast to/from the painter_driver_vtable_t* type
+typedef struct tft_panel_dc_reset_painter_driver_vtable_t {
+ painter_driver_vtable_t base; // must be first, so it can be cast to/from the painter_driver_vtable_t* type
// Number of bytes for transmitting x/y coordinates
uint8_t num_window_bytes;
@@ -29,16 +29,16 @@ struct tft_panel_dc_reset_painter_driver_vtable_t {
uint8_t set_row_address;
uint8_t enable_writes;
} opcodes;
-};
+} tft_panel_dc_reset_painter_driver_vtable_t;
// Device definition
typedef struct tft_panel_dc_reset_painter_device_t {
- struct painter_driver_t base; // must be first, so it can be cast to/from the painter_device_t* type
+ painter_driver_t base; // must be first, so it can be cast to/from the painter_device_t* type
union {
#ifdef QUANTUM_PAINTER_SPI_ENABLE
// SPI-based configurables
- struct qp_comms_spi_dc_reset_config_t spi_dc_reset_config;
+ qp_comms_spi_dc_reset_config_t spi_dc_reset_config;
#endif // QUANTUM_PAINTER_SPI_ENABLE
// TODO: I2C/parallel etc.
diff --git a/drivers/ps2/ps2_interrupt.c b/drivers/ps2/ps2_interrupt.c
index 2810a0f126..f7400564ef 100644
--- a/drivers/ps2/ps2_interrupt.c
+++ b/drivers/ps2/ps2_interrupt.c
@@ -47,6 +47,7 @@ POSSIBILITY OF SUCH DAMAGE.
// chibiOS headers
# include "ch.h"
# include "hal.h"
+# include "gpio.h"
#endif
#include "ps2.h"
diff --git a/drivers/sensors/pmw3320.c b/drivers/sensors/pmw3320.c
new file mode 100644
index 0000000000..a4648ef425
--- /dev/null
+++ b/drivers/sensors/pmw3320.c
@@ -0,0 +1,192 @@
+/* Copyright 2021 Colin Lam (Ploopy Corporation)
+ * Copyright 2020 Christopher Courtney, aka Drashna Jael're (@drashna) <drashna@live.com>
+ * Copyright 2019 Sunjun Kim
+ * Copyright 2019 Hiroyuki Okada
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "pmw3320.h"
+#include "wait.h"
+#include "debug.h"
+#include "gpio.h"
+
+void pmw3320_init(void) {
+ // Initialize sensor serial pins.
+ setPinOutput(PMW3320_SCLK_PIN);
+ setPinOutput(PMW3320_SDIO_PIN);
+ setPinOutput(PMW3320_CS_PIN);
+
+ // reboot the sensor.
+ pmw3320_write_reg(REG_Power_Up_Reset, 0x5a);
+
+ // wait maximum time before sensor is ready.
+ // this ensures that the sensor is actually ready after reset.
+ wait_ms(55);
+
+ // read a burst from the sensor and then discard it.
+ // gets the sensor ready for write commands
+ // (for example, setting the dpi).
+ pmw3320_read_burst();
+
+ // Pretty sure that this shouldn't be in the driver.
+ // Probably device specific?
+ // Set rest mode to default
+ pmw3320_write_reg(REG_Rest_Mode_Status, 0x00);
+ // Set LED to be always on
+ pmw3320_write_reg(REG_Led_Control, 0x4);
+ // Disable rest mode
+ pmw3320_write_reg(REG_Performance, 0x80);
+}
+
+// Perform a synchronization with sensor.
+// Just as with the serial protocol, this is used by the slave to send a
+// synchronization signal to the master.
+void pmw3320_sync(void) {
+ writePinLow(PMW3320_CS_PIN);
+ wait_us(1);
+ writePinHigh(PMW3320_CS_PIN);
+}
+
+void pmw3320_cs_select(void) {
+ writePinLow(PMW3320_CS_PIN);
+}
+
+void pmw3320_cs_deselect(void) {
+ writePinHigh(PMW3320_CS_PIN);
+}
+
+uint8_t pmw3320_serial_read(void) {
+ setPinInput(PMW3320_SDIO_PIN);
+ uint8_t byte = 0;
+
+ for (uint8_t i = 0; i < 8; ++i) {
+ writePinLow(PMW3320_SCLK_PIN);
+ wait_us(1);
+
+ byte = (byte << 1) | readPin(PMW3320_SDIO_PIN);
+
+ writePinHigh(PMW3320_SCLK_PIN);
+ wait_us(1);
+ }
+
+ return byte;
+}
+
+void pmw3320_serial_write(uint8_t data) {
+ setPinOutput(PMW3320_SDIO_PIN);
+
+ for (int8_t b = 7; b >= 0; b--) {
+ writePinLow(PMW3320_SCLK_PIN);
+
+ if (data & (1 << b))
+ writePinHigh(PMW3320_SDIO_PIN);
+ else
+ writePinLow(PMW3320_SDIO_PIN);
+
+ wait_us(2);
+
+ writePinHigh(PMW3320_SCLK_PIN);
+ }
+
+ // This was taken from ADNS5050 driver.
+ // There's no any info in PMW3320 datasheet about this...
+ // tSWR. See page 15 of the ADNS5050 spec sheet.
+ // Technically, this is only necessary if the next operation is an SDIO
+ // read. This is not guaranteed to be the case, but we're being lazy.
+ wait_us(4);
+
+ // Note that tSWW is never necessary. All write operations require at
+ // least 32us, which exceeds tSWW, so there's never a need to wait for it.
+}
+
+// Read a byte of data from a register on the sensor.
+uint8_t pmw3320_read_reg(uint8_t reg_addr) {
+ pmw3320_cs_select();
+
+ pmw3320_serial_write(reg_addr);
+
+ uint8_t byte = pmw3320_serial_read();
+
+ // This was taken directly from ADNS5050 driver...
+ // tSRW & tSRR. See page 15 of the ADNS5050 spec sheet.
+ // Technically, this is only necessary if the next operation is an SDIO
+ // read or write. This is not guaranteed to be the case.
+ // Honestly, this wait could probably be removed.
+ wait_us(1);
+
+ pmw3320_cs_deselect();
+
+ return byte;
+}
+
+void pmw3320_write_reg(uint8_t reg_addr, uint8_t data) {
+ pmw3320_cs_select();
+ pmw3320_serial_write(0b10000000 | reg_addr);
+ pmw3320_serial_write(data);
+ pmw3320_cs_deselect();
+}
+
+report_pmw3320_t pmw3320_read_burst(void) {
+ pmw3320_cs_select();
+
+ report_pmw3320_t data;
+ data.dx = 0;
+ data.dy = 0;
+
+ pmw3320_serial_write(REG_Motion_Burst);
+
+ uint8_t x = pmw3320_serial_read();
+ uint8_t y = pmw3320_serial_read();
+
+ // Probably burst mode may include contents of delta_xy register,
+ // which contain HI parts of x/y deltas, but I had no luck finding it.
+ // Probably it's required to activate 12-bit mode to access this data.
+ // So we end burst mode early to not read unneeded information.
+ pmw3320_cs_deselect();
+
+ data.dx = convert_twoscomp(x);
+ data.dy = convert_twoscomp(y);
+
+ return data;
+}
+
+// Convert a two's complement byte from an unsigned data type into a signed
+// data type.
+int8_t convert_twoscomp(uint8_t data) {
+ if ((data & 0x80) == 0x80)
+ return -128 + (data & 0x7F);
+ else
+ return data;
+}
+
+uint16_t pmw3320_get_cpi(void) {
+ uint8_t cpival = pmw3320_read_reg(REG_Resolution);
+ // 0x1F is an inversion of 0x20 which is 0b100000
+ return (uint16_t)((cpival & 0x1F) * PMW3320_CPI_STEP);
+}
+
+void pmw3320_set_cpi(uint16_t cpi) {
+ uint8_t cpival = constrain((cpi / PMW3320_CPI_STEP) - 1U, 0, (PMW3320_CPI_MAX / PMW3320_CPI_STEP) - 1U);
+ // Fifth bit is probably a control bit.
+ // PMW3320 datasheet don't have any info on this, so this is a pure guess.
+ pmw3320_write_reg(REG_Resolution, 0x20 | cpival);
+}
+
+bool pmw3320_check_signature(void) {
+ uint8_t pid = pmw3320_read_reg(REG_Product_ID);
+ uint8_t pid2 = pmw3320_read_reg(REG_Inverse_Product_ID);
+
+ return (pid == 0x3b && pid2 == 0xc4);
+}
diff --git a/drivers/sensors/pmw3320.h b/drivers/sensors/pmw3320.h
new file mode 100644
index 0000000000..a1fd546919
--- /dev/null
+++ b/drivers/sensors/pmw3320.h
@@ -0,0 +1,119 @@
+/* Copyright 2021 Colin Lam (Ploopy Corporation)
+ * Copyright 2020 Christopher Courtney, aka Drashna Jael're (@drashna) <drashna@live.com>
+ * Copyright 2019 Sunjun Kim
+ * Copyright 2019 Hiroyuki Okada
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#define constrain(amt, low, high) ((amt) < (low) ? (low) : ((amt) > (high) ? (high) : (amt)))
+
+// Definitions for the PMW3320 serial line.
+#ifndef PMW3320_SCLK_PIN
+# ifdef POINTING_DEVICE_SCLK_PIN
+# define PMW3320_SCLK_PIN POINTING_DEVICE_SCLK_PIN
+# else
+# error "No clock pin defined -- missing POINTING_DEVICE_SCLK_PIN or PMW3320_SCLK_PIN"
+# endif
+#endif
+
+#ifndef PMW3320_SDIO_PIN
+# ifdef POINTING_DEVICE_SDIO_PIN
+# define PMW3320_SDIO_PIN POINTING_DEVICE_SDIO_PIN
+# else
+# error "No data pin defined -- missing POINTING_DEVICE_SDIO_PIN or PMW3320_SDIO_PIN"
+# endif
+#endif
+
+#ifndef PMW3320_CS_PIN
+# ifdef POINTING_DEVICE_CS_PIN
+# define PMW3320_CS_PIN POINTING_DEVICE_CS_PIN
+# else
+# error "No chip select pin defined -- missing POINTING_DEVICE_CS_PIN or PMW3320_CS_PIN define"
+# endif
+#endif
+
+typedef struct {
+ int8_t dx;
+ int8_t dy;
+} report_pmw3320_t;
+
+// A bunch of functions to implement the PMW3320-specific serial protocol.
+// Mostly taken from ADNS5050 driver.
+// Note that the "serial.h" driver is insufficient, because it does not
+// manually manipulate a serial clock signal.
+void pmw3320_init(void);
+void pmw3320_sync(void);
+uint8_t pmw3320_serial_read(void);
+void pmw3320_serial_write(uint8_t data);
+uint8_t pmw3320_read_reg(uint8_t reg_addr);
+void pmw3320_write_reg(uint8_t reg_addr, uint8_t data);
+report_pmw3320_t pmw3320_read_burst(void);
+void pmw3320_set_cpi(uint16_t cpi);
+uint16_t pmw3320_get_cpi(void);
+int8_t convert_twoscomp(uint8_t data);
+bool pmw3320_check_signature(void);
+
+#if !defined(PMW3320_CPI)
+# define PMW3320_CPI 1000
+#endif
+
+#define PMW3320_CPI_STEP 250
+#define PMW3320_CPI_MIN 250
+#define PMW3320_CPI_MAX 3500
+
+// PMW3320 register addresses
+// clang-format off
+#define REG_Product_ID 0x00
+#define REG_Revision_ID 0x01
+#define REG_Motion 0x02
+#define REG_Delta_X 0x03
+#define REG_Delta_Y 0x04
+#define REG_SQUAL 0x05
+#define REG_Shutter_Upper 0x06
+#define REG_Shutter_Lower 0x07
+#define REG_Maximum_Pixel 0x08
+#define REG_Pixel_Accum 0x09
+#define REG_Minimum_Pixel 0x0a
+#define REG_Pixel_Grab 0x0b
+#define REG_Delta_XY 0x0c
+#define REG_Resolution 0x0d
+#define REG_Run_Downshift 0x0e
+#define REG_Rest1_Period 0x0f
+#define REG_Rest1_Downshift 0x10
+#define REG_Rest2_Preiod 0x11
+#define REG_Rest2_Downshift 0x12
+#define REG_Rest3_Period 0x13
+#define REG_Min_SQ_Run 0x17
+#define REG_Axis_Control 0x1a
+#define REG_Performance 0x22
+#define REG_Low_Motion_Jitter 0x23
+#define REG_Shutter_Max_HI 0x36
+#define REG_Shutter_Max_LO 0x37
+#define REG_Frame_Rate 0x39
+#define REG_Power_Up_Reset 0x3a
+#define REG_Shutdown 0x3b
+#define REG_Inverse_Revision_ID 0x3f
+#define REG_Led_Control 0x40
+#define REG_Motion_Control 0x41
+#define REG_Burst_Read_First 0x42
+#define REG_Rest_Mode_Status 0x45
+#define REG_Inverse_Product_ID 0x4f
+#define REG_Motion_Burst 0x63
+// clang-format on
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-01 23:28:52 +0000